[deliverable/linux.git] / arch / openrisc / Kconfig

#
# For a description of the syntax of this configuration file,
# see Documentation/kbuild/kconfig-language.txt.
#

config OPENRISC
	def_bool y
	select OF
	select OF_EARLY_FLATTREE
	select IRQ_DOMAIN
	select HANDLE_DOMAIN_IRQ
	select HAVE_MEMBLOCK
	select ARCH_REQUIRE_GPIOLIB
        select HAVE_ARCH_TRACEHOOK
	select GENERIC_IRQ_CHIP
	select GENERIC_IRQ_PROBE
	select GENERIC_IRQ_SHOW
	select GENERIC_IOMAP
	select GENERIC_CPU_DEVICES
	select HAVE_UID16
	select GENERIC_ATOMIC64
	select GENERIC_CLOCKEVENTS
	select GENERIC_STRNCPY_FROM_USER
	select GENERIC_STRNLEN_USER
	select MODULES_USE_ELF_RELA
	select HAVE_DEBUG_STACKOVERFLOW
	select OR1K_PIC

config MMU
	def_bool y

config RWSEM_GENERIC_SPINLOCK
	def_bool y

config RWSEM_XCHGADD_ALGORITHM
	def_bool n

config GENERIC_HWEIGHT
	def_bool y

config NO_IOPORT_MAP
	def_bool y

config TRACE_IRQFLAGS_SUPPORT
        def_bool y

# For now, use generic checksum functions
#These can be reimplemented in assembly later if so inclined
config GENERIC_CSUM
        def_bool y

source "init/Kconfig"

source "kernel/Kconfig.freezer"

menu "Processor type and features"

choice
	prompt "Subarchitecture"
	default OR1K_1200

config OR1K_1200
	bool "OR1200"
	help
	  Generic OpenRISC 1200 architecture

endchoice

config OPENRISC_BUILTIN_DTB
        string "Builtin DTB"
        default ""

menu "Class II Instructions"

config OPENRISC_HAVE_INST_FF1
	bool "Have instruction l.ff1"
	default y
	help
	  Select this if your implementation has the Class II instruction l.ff1

config OPENRISC_HAVE_INST_FL1
	bool "Have instruction l.fl1"
	default y
	help
	  Select this if your implementation has the Class II instruction l.fl1

config OPENRISC_HAVE_INST_MUL
	bool "Have instruction l.mul for hardware multiply"
	default y
	help
	  Select this if your implementation has a hardware multiply instruction

config OPENRISC_HAVE_INST_DIV
	bool "Have instruction l.div for hardware divide"
	default y
	help
	  Select this if your implementation has a hardware divide instruction
endmenu


source kernel/Kconfig.hz
source kernel/Kconfig.preempt
source "mm/Kconfig"

config OPENRISC_NO_SPR_SR_DSX
	bool "use SPR_SR_DSX software emulation" if OR1K_1200
	default y
	help
	  SPR_SR_DSX bit is status register bit indicating whether
	  the last exception has happened in delay slot.

	  OpenRISC architecture makes it optional to have it implemented
	  in hardware and the OR1200 does not have it.

	  Say N here if you know that your OpenRISC processor has
	  SPR_SR_DSX bit implemented. Say Y if you are unsure.

config CMDLINE
        string "Default kernel command string"
        default ""
        help
          On some architectures there is currently no way for the boot loader
          to pass arguments to the kernel. For these architectures, you should
          supply some command-line options at build time by entering them
          here.

menu "Debugging options"

config JUMP_UPON_UNHANDLED_EXCEPTION
	bool "Try to die gracefully"
	default y
	help
	  Now this puts kernel into infinite loop after first oops. Till
	  your kernel crashes this doesn't have any influence.

	  Say Y if you are unsure.

config OPENRISC_ESR_EXCEPTION_BUG_CHECK
	bool "Check for possible ESR exception bug"
	default n
	help
	  This option enables some checks that might expose some problems
          in kernel.

	  Say N if you are unsure.

endmenu

endmenu

menu "Executable file formats"

source "fs/Kconfig.binfmt"

endmenu

source "net/Kconfig"

source "drivers/Kconfig"

source "fs/Kconfig"

source "security/Kconfig"

source "crypto/Kconfig"

source "lib/Kconfig"

menu "Kernel hacking"

source "lib/Kconfig.debug"

endmenu
Commit	Line	Data
f8c4a270 JB	1	#
f8c4a270 JB	2	# For a description of the syntax of this configuration file,
395cf969	3	# see Documentation/kbuild/kconfig-language.txt.
f8c4a270 JB	4	#
	5
	6	config OPENRISC
	7	def_bool y
	8	select OF
	9	select OF_EARLY_FLATTREE
b4c4c6ee	10	select IRQ_DOMAIN
d1f6f28f	11	select HANDLE_DOMAIN_IRQ
f8c4a270	12	select HAVE_MEMBLOCK
d4cb776f	13	select ARCH_REQUIRE_GPIOLIB
f8c4a270	14	select HAVE_ARCH_TRACEHOOK
f8c4a270 JB	15	select GENERIC_IRQ_CHIP
	16	select GENERIC_IRQ_PROBE
	17	select GENERIC_IRQ_SHOW
	18	select GENERIC_IOMAP
9f13a1fd	19	select GENERIC_CPU_DEVICES
04ea1e91	20	select HAVE_UID16
0662d33a	21	select GENERIC_ATOMIC64
5bf8f6bf	22	select GENERIC_CLOCKEVENTS
603d6637	23	select GENERIC_STRNCPY_FROM_USER
b48b2c3e	24	select GENERIC_STRNLEN_USER
786d35d4	25	select MODULES_USE_ELF_RELA
d1a1dc0b	26	select HAVE_DEBUG_STACKOVERFLOW
4db8e6d2	27	select OR1K_PIC
f8c4a270 JB	28
	29	config MMU
	30	def_bool y
	31
f8c4a270 JB	32	config RWSEM_GENERIC_SPINLOCK
	33	def_bool y
	34
	35	config RWSEM_XCHGADD_ALGORITHM
	36	def_bool n
	37
	38	config GENERIC_HWEIGHT
	39	def_bool y
	40
ce816fa8	41	config NO_IOPORT_MAP
f8c4a270 JB	42	def_bool y
f8c4a270 JB	43
f8c4a270 JB	44	config TRACE_IRQFLAGS_SUPPORT
	45	def_bool y
	46
	47	# For now, use generic checksum functions
	48	#These can be reimplemented in assembly later if so inclined
	49	config GENERIC_CSUM
	50	def_bool y
	51
f8c4a270 JB	52	source "init/Kconfig"
f8c4a270 JB	53
57a1a197	54	source "kernel/Kconfig.freezer"
f8c4a270 JB	55
	56	menu "Processor type and features"
	57
	58	choice
	59	prompt "Subarchitecture"
	60	default OR1K_1200
	61
	62	config OR1K_1200
	63	bool "OR1200"
	64	help
	65	Generic OpenRISC 1200 architecture
	66
	67	endchoice
	68
	69	config OPENRISC_BUILTIN_DTB
	70	string "Builtin DTB"
	71	default ""
	72
	73	menu "Class II Instructions"
	74
	75	config OPENRISC_HAVE_INST_FF1
	76	bool "Have instruction l.ff1"
	77	default y
	78	help
	79	Select this if your implementation has the Class II instruction l.ff1
	80
	81	config OPENRISC_HAVE_INST_FL1
	82	bool "Have instruction l.fl1"
	83	default y
	84	help
	85	Select this if your implementation has the Class II instruction l.fl1
	86
	87	config OPENRISC_HAVE_INST_MUL
	88	bool "Have instruction l.mul for hardware multiply"
	89	default y
	90	help
	91	Select this if your implementation has a hardware multiply instruction
	92
	93	config OPENRISC_HAVE_INST_DIV
	94	bool "Have instruction l.div for hardware divide"
	95	default y
	96	help
	97	Select this if your implementation has a hardware divide instruction
	98	endmenu
	99
	100
f8c4a270 JB	101	source kernel/Kconfig.hz
	102	source kernel/Kconfig.preempt
	103	source "mm/Kconfig"
	104
	105	config OPENRISC_NO_SPR_SR_DSX
	106	bool "use SPR_SR_DSX software emulation" if OR1K_1200
	107	default y
	108	help
	109	SPR_SR_DSX bit is status register bit indicating whether
	110	the last exception has happened in delay slot.
	111
	112	OpenRISC architecture makes it optional to have it implemented
	113	in hardware and the OR1200 does not have it.
	114
	115	Say N here if you know that your OpenRISC processor has
	116	SPR_SR_DSX bit implemented. Say Y if you are unsure.
	117
	118	config CMDLINE
	119	string "Default kernel command string"
	120	default ""
	121	help
	122	On some architectures there is currently no way for the boot loader
	123	to pass arguments to the kernel. For these architectures, you should
	124	supply some command-line options at build time by entering them
	125	here.
	126
	127	menu "Debugging options"
	128
f8c4a270 JB	129	config JUMP_UPON_UNHANDLED_EXCEPTION
	130	bool "Try to die gracefully"
	131	default y
	132	help
	133	Now this puts kernel into infinite loop after first oops. Till
	134	your kernel crashes this doesn't have any influence.
	135
	136	Say Y if you are unsure.
	137
f8c4a270 JB	138	config OPENRISC_ESR_EXCEPTION_BUG_CHECK
	139	bool "Check for possible ESR exception bug"
	140	default n
	141	help
	142	This option enables some checks that might expose some problems
	143	in kernel.
	144
	145	Say N if you are unsure.
	146
	147	endmenu
	148
	149	endmenu
	150
	151	menu "Executable file formats"
	152
	153	source "fs/Kconfig.binfmt"
	154
	155	endmenu
	156
	157	source "net/Kconfig"
	158
	159	source "drivers/Kconfig"
	160
	161	source "fs/Kconfig"
	162
	163	source "security/Kconfig"
	164
	165	source "crypto/Kconfig"
	166
	167	source "lib/Kconfig"
	168
	169	menu "Kernel hacking"
	170
	171	source "lib/Kconfig.debug"
	172
	173	endmenu