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1da177e4 LT |
1 | /* |
2 | * Code to handle x86 style IRQs plus some generic interrupt stuff. | |
3 | * | |
4 | * Copyright (C) 1992 Linus Torvalds | |
5 | * Copyright (C) 1994, 1995, 1996, 1997, 1998 Ralf Baechle | |
6 | * Copyright (C) 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org) | |
7 | * Copyright (C) 1999-2000 Grant Grundler | |
8 | * Copyright (c) 2005 Matthew Wilcox | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2, or (at your option) | |
13 | * any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
23 | */ | |
24 | #include <linux/bitops.h> | |
1da177e4 LT |
25 | #include <linux/errno.h> |
26 | #include <linux/init.h> | |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/kernel_stat.h> | |
29 | #include <linux/seq_file.h> | |
30 | #include <linux/spinlock.h> | |
31 | #include <linux/types.h> | |
c2ab64d0 | 32 | #include <asm/io.h> |
1da177e4 | 33 | |
1d4c452a KM |
34 | #include <asm/smp.h> |
35 | ||
1da177e4 LT |
36 | #undef PARISC_IRQ_CR16_COUNTS |
37 | ||
be577a52 MW |
38 | extern irqreturn_t timer_interrupt(int, void *); |
39 | extern irqreturn_t ipi_interrupt(int, void *); | |
1da177e4 LT |
40 | |
41 | #define EIEM_MASK(irq) (1UL<<(CPU_IRQ_MAX - irq)) | |
42 | ||
43 | /* Bits in EIEM correlate with cpu_irq_action[]. | |
44 | ** Numbered *Big Endian*! (ie bit 0 is MSB) | |
45 | */ | |
46 | static volatile unsigned long cpu_eiem = 0; | |
47 | ||
7085689e JB |
48 | /* |
49 | ** ack bitmap ... habitually set to 1, but reset to zero | |
50 | ** between ->ack() and ->end() of the interrupt to prevent | |
51 | ** re-interruption of a processing interrupt. | |
52 | */ | |
53 | static volatile unsigned long global_ack_eiem = ~0UL; | |
54 | /* | |
55 | ** Local bitmap, same as above but for per-cpu interrupts | |
56 | */ | |
57 | static DEFINE_PER_CPU(unsigned long, local_ack_eiem) = ~0UL; | |
58 | ||
d911aed8 | 59 | static void cpu_disable_irq(unsigned int irq) |
1da177e4 LT |
60 | { |
61 | unsigned long eirr_bit = EIEM_MASK(irq); | |
62 | ||
63 | cpu_eiem &= ~eirr_bit; | |
d911aed8 JB |
64 | /* Do nothing on the other CPUs. If they get this interrupt, |
65 | * The & cpu_eiem in the do_cpu_irq_mask() ensures they won't | |
66 | * handle it, and the set_eiem() at the bottom will ensure it | |
67 | * then gets disabled */ | |
1da177e4 LT |
68 | } |
69 | ||
70 | static void cpu_enable_irq(unsigned int irq) | |
71 | { | |
72 | unsigned long eirr_bit = EIEM_MASK(irq); | |
73 | ||
1da177e4 | 74 | cpu_eiem |= eirr_bit; |
d911aed8 | 75 | |
d911aed8 JB |
76 | /* This is just a simple NOP IPI. But what it does is cause |
77 | * all the other CPUs to do a set_eiem(cpu_eiem) at the end | |
78 | * of the interrupt handler */ | |
79 | smp_send_all_nop(); | |
1da177e4 LT |
80 | } |
81 | ||
82 | static unsigned int cpu_startup_irq(unsigned int irq) | |
83 | { | |
84 | cpu_enable_irq(irq); | |
85 | return 0; | |
86 | } | |
87 | ||
88 | void no_ack_irq(unsigned int irq) { } | |
89 | void no_end_irq(unsigned int irq) { } | |
90 | ||
7085689e JB |
91 | void cpu_ack_irq(unsigned int irq) |
92 | { | |
93 | unsigned long mask = EIEM_MASK(irq); | |
94 | int cpu = smp_processor_id(); | |
95 | ||
96 | /* Clear in EIEM so we can no longer process */ | |
97 | if (CHECK_IRQ_PER_CPU(irq_desc[irq].status)) | |
98 | per_cpu(local_ack_eiem, cpu) &= ~mask; | |
99 | else | |
100 | global_ack_eiem &= ~mask; | |
101 | ||
102 | /* disable the interrupt */ | |
103 | set_eiem(cpu_eiem & global_ack_eiem & per_cpu(local_ack_eiem, cpu)); | |
104 | /* and now ack it */ | |
105 | mtctl(mask, 23); | |
106 | } | |
107 | ||
108 | void cpu_end_irq(unsigned int irq) | |
109 | { | |
110 | unsigned long mask = EIEM_MASK(irq); | |
111 | int cpu = smp_processor_id(); | |
112 | ||
113 | /* set it in the eiems---it's no longer in process */ | |
114 | if (CHECK_IRQ_PER_CPU(irq_desc[irq].status)) | |
115 | per_cpu(local_ack_eiem, cpu) |= mask; | |
116 | else | |
117 | global_ack_eiem |= mask; | |
118 | ||
119 | /* enable the interrupt */ | |
120 | set_eiem(cpu_eiem & global_ack_eiem & per_cpu(local_ack_eiem, cpu)); | |
121 | } | |
122 | ||
c2ab64d0 JB |
123 | #ifdef CONFIG_SMP |
124 | int cpu_check_affinity(unsigned int irq, cpumask_t *dest) | |
125 | { | |
126 | int cpu_dest; | |
127 | ||
128 | /* timer and ipi have to always be received on all CPUs */ | |
7085689e | 129 | if (CHECK_IRQ_PER_CPU(irq)) { |
c2ab64d0 JB |
130 | /* Bad linux design decision. The mask has already |
131 | * been set; we must reset it */ | |
a53da52f | 132 | irq_desc[irq].affinity = CPU_MASK_ALL; |
c2ab64d0 JB |
133 | return -EINVAL; |
134 | } | |
135 | ||
136 | /* whatever mask they set, we just allow one CPU */ | |
137 | cpu_dest = first_cpu(*dest); | |
138 | *dest = cpumask_of_cpu(cpu_dest); | |
139 | ||
140 | return 0; | |
141 | } | |
142 | ||
143 | static void cpu_set_affinity_irq(unsigned int irq, cpumask_t dest) | |
144 | { | |
145 | if (cpu_check_affinity(irq, &dest)) | |
146 | return; | |
147 | ||
a53da52f | 148 | irq_desc[irq].affinity = dest; |
c2ab64d0 JB |
149 | } |
150 | #endif | |
151 | ||
1da177e4 LT |
152 | static struct hw_interrupt_type cpu_interrupt_type = { |
153 | .typename = "CPU", | |
154 | .startup = cpu_startup_irq, | |
155 | .shutdown = cpu_disable_irq, | |
156 | .enable = cpu_enable_irq, | |
157 | .disable = cpu_disable_irq, | |
7085689e JB |
158 | .ack = cpu_ack_irq, |
159 | .end = cpu_end_irq, | |
c2ab64d0 JB |
160 | #ifdef CONFIG_SMP |
161 | .set_affinity = cpu_set_affinity_irq, | |
162 | #endif | |
c0ad90a3 IM |
163 | /* XXX: Needs to be written. We managed without it so far, but |
164 | * we really ought to write it. | |
165 | */ | |
166 | .retrigger = NULL, | |
1da177e4 LT |
167 | }; |
168 | ||
169 | int show_interrupts(struct seq_file *p, void *v) | |
170 | { | |
171 | int i = *(loff_t *) v, j; | |
172 | unsigned long flags; | |
173 | ||
174 | if (i == 0) { | |
175 | seq_puts(p, " "); | |
176 | for_each_online_cpu(j) | |
177 | seq_printf(p, " CPU%d", j); | |
178 | ||
179 | #ifdef PARISC_IRQ_CR16_COUNTS | |
180 | seq_printf(p, " [min/avg/max] (CPU cycle counts)"); | |
181 | #endif | |
182 | seq_putc(p, '\n'); | |
183 | } | |
184 | ||
185 | if (i < NR_IRQS) { | |
186 | struct irqaction *action; | |
187 | ||
188 | spin_lock_irqsave(&irq_desc[i].lock, flags); | |
189 | action = irq_desc[i].action; | |
190 | if (!action) | |
191 | goto skip; | |
192 | seq_printf(p, "%3d: ", i); | |
193 | #ifdef CONFIG_SMP | |
194 | for_each_online_cpu(j) | |
195 | seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); | |
196 | #else | |
197 | seq_printf(p, "%10u ", kstat_irqs(i)); | |
198 | #endif | |
199 | ||
d1bef4ed | 200 | seq_printf(p, " %14s", irq_desc[i].chip->typename); |
1da177e4 LT |
201 | #ifndef PARISC_IRQ_CR16_COUNTS |
202 | seq_printf(p, " %s", action->name); | |
203 | ||
204 | while ((action = action->next)) | |
205 | seq_printf(p, ", %s", action->name); | |
206 | #else | |
207 | for ( ;action; action = action->next) { | |
208 | unsigned int k, avg, min, max; | |
209 | ||
210 | min = max = action->cr16_hist[0]; | |
211 | ||
212 | for (avg = k = 0; k < PARISC_CR16_HIST_SIZE; k++) { | |
213 | int hist = action->cr16_hist[k]; | |
214 | ||
215 | if (hist) { | |
216 | avg += hist; | |
217 | } else | |
218 | break; | |
219 | ||
220 | if (hist > max) max = hist; | |
221 | if (hist < min) min = hist; | |
222 | } | |
223 | ||
224 | avg /= k; | |
225 | seq_printf(p, " %s[%d/%d/%d]", action->name, | |
226 | min,avg,max); | |
227 | } | |
228 | #endif | |
229 | ||
230 | seq_putc(p, '\n'); | |
231 | skip: | |
232 | spin_unlock_irqrestore(&irq_desc[i].lock, flags); | |
233 | } | |
234 | ||
235 | return 0; | |
236 | } | |
237 | ||
238 | ||
239 | ||
240 | /* | |
241 | ** The following form a "set": Virtual IRQ, Transaction Address, Trans Data. | |
242 | ** Respectively, these map to IRQ region+EIRR, Processor HPA, EIRR bit. | |
243 | ** | |
244 | ** To use txn_XXX() interfaces, get a Virtual IRQ first. | |
245 | ** Then use that to get the Transaction address and data. | |
246 | */ | |
247 | ||
5cfe87d3 | 248 | int cpu_claim_irq(unsigned int irq, struct irq_chip *type, void *data) |
1da177e4 LT |
249 | { |
250 | if (irq_desc[irq].action) | |
251 | return -EBUSY; | |
d1bef4ed | 252 | if (irq_desc[irq].chip != &cpu_interrupt_type) |
1da177e4 LT |
253 | return -EBUSY; |
254 | ||
255 | if (type) { | |
d1bef4ed IM |
256 | irq_desc[irq].chip = type; |
257 | irq_desc[irq].chip_data = data; | |
1da177e4 LT |
258 | cpu_interrupt_type.enable(irq); |
259 | } | |
260 | return 0; | |
261 | } | |
262 | ||
263 | int txn_claim_irq(int irq) | |
264 | { | |
265 | return cpu_claim_irq(irq, NULL, NULL) ? -1 : irq; | |
266 | } | |
267 | ||
268 | /* | |
269 | * The bits_wide parameter accommodates the limitations of the HW/SW which | |
270 | * use these bits: | |
271 | * Legacy PA I/O (GSC/NIO): 5 bits (architected EIM register) | |
272 | * V-class (EPIC): 6 bits | |
273 | * N/L/A-class (iosapic): 8 bits | |
274 | * PCI 2.2 MSI: 16 bits | |
275 | * Some PCI devices: 32 bits (Symbios SCSI/ATM/HyperFabric) | |
276 | * | |
277 | * On the service provider side: | |
278 | * o PA 1.1 (and PA2.0 narrow mode) 5-bits (width of EIR register) | |
279 | * o PA 2.0 wide mode 6-bits (per processor) | |
280 | * o IA64 8-bits (0-256 total) | |
281 | * | |
282 | * So a Legacy PA I/O device on a PA 2.0 box can't use all the bits supported | |
283 | * by the processor...and the N/L-class I/O subsystem supports more bits than | |
284 | * PA2.0 has. The first case is the problem. | |
285 | */ | |
286 | int txn_alloc_irq(unsigned int bits_wide) | |
287 | { | |
288 | int irq; | |
289 | ||
290 | /* never return irq 0 cause that's the interval timer */ | |
291 | for (irq = CPU_IRQ_BASE + 1; irq <= CPU_IRQ_MAX; irq++) { | |
292 | if (cpu_claim_irq(irq, NULL, NULL) < 0) | |
293 | continue; | |
294 | if ((irq - CPU_IRQ_BASE) >= (1 << bits_wide)) | |
295 | continue; | |
296 | return irq; | |
297 | } | |
298 | ||
299 | /* unlikely, but be prepared */ | |
300 | return -1; | |
301 | } | |
302 | ||
03afe22f | 303 | |
c2ab64d0 JB |
304 | unsigned long txn_affinity_addr(unsigned int irq, int cpu) |
305 | { | |
03afe22f | 306 | #ifdef CONFIG_SMP |
a53da52f | 307 | irq_desc[irq].affinity = cpumask_of_cpu(cpu); |
03afe22f | 308 | #endif |
c2ab64d0 JB |
309 | |
310 | return cpu_data[cpu].txn_addr; | |
311 | } | |
312 | ||
03afe22f | 313 | |
1da177e4 LT |
314 | unsigned long txn_alloc_addr(unsigned int virt_irq) |
315 | { | |
316 | static int next_cpu = -1; | |
317 | ||
318 | next_cpu++; /* assign to "next" CPU we want this bugger on */ | |
319 | ||
320 | /* validate entry */ | |
321 | while ((next_cpu < NR_CPUS) && (!cpu_data[next_cpu].txn_addr || | |
322 | !cpu_online(next_cpu))) | |
323 | next_cpu++; | |
324 | ||
325 | if (next_cpu >= NR_CPUS) | |
326 | next_cpu = 0; /* nothing else, assign monarch */ | |
327 | ||
c2ab64d0 | 328 | return txn_affinity_addr(virt_irq, next_cpu); |
1da177e4 LT |
329 | } |
330 | ||
331 | ||
332 | unsigned int txn_alloc_data(unsigned int virt_irq) | |
333 | { | |
334 | return virt_irq - CPU_IRQ_BASE; | |
335 | } | |
336 | ||
7085689e JB |
337 | static inline int eirr_to_irq(unsigned long eirr) |
338 | { | |
0c2de3c6 | 339 | int bit = fls_long(eirr); |
7085689e JB |
340 | return (BITS_PER_LONG - bit) + TIMER_IRQ; |
341 | } | |
342 | ||
1da177e4 LT |
343 | /* ONLY called from entry.S:intr_extint() */ |
344 | void do_cpu_irq_mask(struct pt_regs *regs) | |
345 | { | |
e11e30a0 | 346 | struct pt_regs *old_regs; |
1da177e4 | 347 | unsigned long eirr_val; |
7085689e | 348 | int irq, cpu = smp_processor_id(); |
03afe22f | 349 | #ifdef CONFIG_SMP |
7085689e | 350 | cpumask_t dest; |
03afe22f | 351 | #endif |
1da177e4 | 352 | |
e11e30a0 | 353 | old_regs = set_irq_regs(regs); |
7085689e JB |
354 | local_irq_disable(); |
355 | irq_enter(); | |
1da177e4 | 356 | |
7085689e JB |
357 | eirr_val = mfctl(23) & cpu_eiem & global_ack_eiem & |
358 | per_cpu(local_ack_eiem, cpu); | |
359 | if (!eirr_val) | |
360 | goto set_out; | |
361 | irq = eirr_to_irq(eirr_val); | |
c2ab64d0 | 362 | |
7085689e JB |
363 | #ifdef CONFIG_SMP |
364 | dest = irq_desc[irq].affinity; | |
365 | if (CHECK_IRQ_PER_CPU(irq_desc[irq].status) && | |
366 | !cpu_isset(smp_processor_id(), dest)) { | |
367 | int cpu = first_cpu(dest); | |
368 | ||
369 | printk(KERN_DEBUG "redirecting irq %d from CPU %d to %d\n", | |
370 | irq, smp_processor_id(), cpu); | |
371 | gsc_writel(irq + CPU_IRQ_BASE, | |
372 | cpu_data[cpu].hpa); | |
373 | goto set_out; | |
1da177e4 | 374 | } |
7085689e | 375 | #endif |
be577a52 | 376 | __do_IRQ(irq); |
3f902886 | 377 | |
7085689e | 378 | out: |
1da177e4 | 379 | irq_exit(); |
e11e30a0 | 380 | set_irq_regs(old_regs); |
7085689e | 381 | return; |
1da177e4 | 382 | |
7085689e JB |
383 | set_out: |
384 | set_eiem(cpu_eiem & global_ack_eiem & per_cpu(local_ack_eiem, cpu)); | |
385 | goto out; | |
386 | } | |
1da177e4 LT |
387 | |
388 | static struct irqaction timer_action = { | |
389 | .handler = timer_interrupt, | |
390 | .name = "timer", | |
57501c70 | 391 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_PERCPU | IRQF_IRQPOLL, |
1da177e4 LT |
392 | }; |
393 | ||
394 | #ifdef CONFIG_SMP | |
395 | static struct irqaction ipi_action = { | |
396 | .handler = ipi_interrupt, | |
397 | .name = "IPI", | |
7085689e | 398 | .flags = IRQF_DISABLED | IRQF_PERCPU, |
1da177e4 LT |
399 | }; |
400 | #endif | |
401 | ||
402 | static void claim_cpu_irqs(void) | |
403 | { | |
404 | int i; | |
405 | for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) { | |
d1bef4ed | 406 | irq_desc[i].chip = &cpu_interrupt_type; |
1da177e4 LT |
407 | } |
408 | ||
409 | irq_desc[TIMER_IRQ].action = &timer_action; | |
410 | irq_desc[TIMER_IRQ].status |= IRQ_PER_CPU; | |
411 | #ifdef CONFIG_SMP | |
412 | irq_desc[IPI_IRQ].action = &ipi_action; | |
413 | irq_desc[IPI_IRQ].status = IRQ_PER_CPU; | |
414 | #endif | |
415 | } | |
416 | ||
417 | void __init init_IRQ(void) | |
418 | { | |
419 | local_irq_disable(); /* PARANOID - should already be disabled */ | |
420 | mtctl(~0UL, 23); /* EIRR : clear all pending external intr */ | |
421 | claim_cpu_irqs(); | |
422 | #ifdef CONFIG_SMP | |
423 | if (!cpu_eiem) | |
424 | cpu_eiem = EIEM_MASK(IPI_IRQ) | EIEM_MASK(TIMER_IRQ); | |
425 | #else | |
426 | cpu_eiem = EIEM_MASK(TIMER_IRQ); | |
427 | #endif | |
428 | set_eiem(cpu_eiem); /* EIEM : enable all external intr */ | |
429 | ||
430 | } | |
431 | ||
1da177e4 LT |
432 | void ack_bad_irq(unsigned int irq) |
433 | { | |
434 | printk("unexpected IRQ %d\n", irq); | |
435 | } |