[deliverable/linux.git] / arch / parisc / kernel / irq.c

/* 
 * Code to handle x86 style IRQs plus some generic interrupt stuff.
 *
 * Copyright (C) 1992 Linus Torvalds
 * Copyright (C) 1994, 1995, 1996, 1997, 1998 Ralf Baechle
 * Copyright (C) 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org)
 * Copyright (C) 1999-2000 Grant Grundler
 * Copyright (c) 2005 Matthew Wilcox
 *
 *    This program is free software; you can redistribute it and/or modify
 *    it under the terms of the GNU General Public License as published by
 *    the Free Software Foundation; either version 2, or (at your option)
 *    any later version.
 *
 *    This program is distributed in the hope that it will be useful,
 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *    GNU General Public License for more details.
 *
 *    You should have received a copy of the GNU General Public License
 *    along with this program; if not, write to the Free Software
 *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */
#include <linux/bitops.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/seq_file.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#include <asm/io.h>

#include <asm/smp.h>

#undef PARISC_IRQ_CR16_COUNTS

extern irqreturn_t timer_interrupt(int, void *);
extern irqreturn_t ipi_interrupt(int, void *);

#define EIEM_MASK(irq)       (1UL<<(CPU_IRQ_MAX - irq))

/* Bits in EIEM correlate with cpu_irq_action[].
** Numbered *Big Endian*! (ie bit 0 is MSB)
*/
static volatile unsigned long cpu_eiem = 0;

/*
** local ACK bitmap ... habitually set to 1, but reset to zero
** between ->ack() and ->end() of the interrupt to prevent
** re-interruption of a processing interrupt.
*/
static DEFINE_PER_CPU(unsigned long, local_ack_eiem) = ~0UL;

static void cpu_mask_irq(struct irq_data *d)
{
	unsigned long eirr_bit = EIEM_MASK(d->irq);

	cpu_eiem &= ~eirr_bit;
	/* Do nothing on the other CPUs.  If they get this interrupt,
	 * The & cpu_eiem in the do_cpu_irq_mask() ensures they won't
	 * handle it, and the set_eiem() at the bottom will ensure it
	 * then gets disabled */
}

static void __cpu_unmask_irq(unsigned int irq)
{
	unsigned long eirr_bit = EIEM_MASK(irq);

	cpu_eiem |= eirr_bit;

	/* This is just a simple NOP IPI.  But what it does is cause
	 * all the other CPUs to do a set_eiem(cpu_eiem) at the end
	 * of the interrupt handler */
	smp_send_all_nop();
}

static void cpu_unmask_irq(struct irq_data *d)
{
	__cpu_unmask_irq(d->irq);
}

void cpu_ack_irq(struct irq_data *d)
{
	unsigned long mask = EIEM_MASK(d->irq);
	int cpu = smp_processor_id();

	/* Clear in EIEM so we can no longer process */
	per_cpu(local_ack_eiem, cpu) &= ~mask;

	/* disable the interrupt */
	set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));

	/* and now ack it */
	mtctl(mask, 23);
}

void cpu_eoi_irq(struct irq_data *d)
{
	unsigned long mask = EIEM_MASK(d->irq);
	int cpu = smp_processor_id();

	/* set it in the eiems---it's no longer in process */
	per_cpu(local_ack_eiem, cpu) |= mask;

	/* enable the interrupt */
	set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
}

#ifdef CONFIG_SMP
int cpu_check_affinity(struct irq_data *d, const struct cpumask *dest)
{
	int cpu_dest;

	/* timer and ipi have to always be received on all CPUs */
	if (CHECK_IRQ_PER_CPU(irq_to_desc(d->irq)->status)) {
		/* Bad linux design decision.  The mask has already
		 * been set; we must reset it. Will fix - tglx
		 */
		cpumask_setall(d->affinity);
		return -EINVAL;
	}

	/* whatever mask they set, we just allow one CPU */
	cpu_dest = first_cpu(*dest);

	return cpu_dest;
}

static int cpu_set_affinity_irq(struct irq_data *d, const struct cpumask *dest,
				bool force)
{
	int cpu_dest;

	cpu_dest = cpu_check_affinity(d, dest);
	if (cpu_dest < 0)
		return -1;

	cpumask_copy(d->affinity, dest);

	return 0;
}
#endif

static struct irq_chip cpu_interrupt_type = {
	.name			= "CPU",
	.irq_mask		= cpu_mask_irq,
	.irq_unmask		= cpu_unmask_irq,
	.irq_ack		= cpu_ack_irq,
	.irq_eoi		= cpu_eoi_irq,
#ifdef CONFIG_SMP
	.irq_set_affinity	= cpu_set_affinity_irq,
#endif
	/* XXX: Needs to be written.  We managed without it so far, but
	 * we really ought to write it.
	 */
	.irq_retrigger	= NULL,
};

int show_interrupts(struct seq_file *p, void *v)
{
	int i = *(loff_t *) v, j;
	unsigned long flags;

	if (i == 0) {
		seq_puts(p, "    ");
		for_each_online_cpu(j)
			seq_printf(p, "       CPU%d", j);

#ifdef PARISC_IRQ_CR16_COUNTS
		seq_printf(p, " [min/avg/max] (CPU cycle counts)");
#endif
		seq_putc(p, '\n');
	}

	if (i < NR_IRQS) {
		struct irqaction *action;

		raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
		action = irq_desc[i].action;
		if (!action)
			goto skip;
		seq_printf(p, "%3d: ", i);
#ifdef CONFIG_SMP
		for_each_online_cpu(j)
			seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
#else
		seq_printf(p, "%10u ", kstat_irqs(i));
#endif

		seq_printf(p, " %14s", irq_desc[i].irq_data.chip->name);
#ifndef PARISC_IRQ_CR16_COUNTS
		seq_printf(p, "  %s", action->name);

		while ((action = action->next))
			seq_printf(p, ", %s", action->name);
#else
		for ( ;action; action = action->next) {
			unsigned int k, avg, min, max;

			min = max = action->cr16_hist[0];

			for (avg = k = 0; k < PARISC_CR16_HIST_SIZE; k++) {
				int hist = action->cr16_hist[k];

				if (hist) {
					avg += hist;
				} else
					break;

				if (hist > max) max = hist;
				if (hist < min) min = hist;
			}

			avg /= k;
			seq_printf(p, " %s[%d/%d/%d]", action->name,
					min,avg,max);
		}
#endif

		seq_putc(p, '\n');
 skip:
		raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
	}

	return 0;
}


/*
** The following form a "set": Virtual IRQ, Transaction Address, Trans Data.
** Respectively, these map to IRQ region+EIRR, Processor HPA, EIRR bit.
**
** To use txn_XXX() interfaces, get a Virtual IRQ first.
** Then use that to get the Transaction address and data.
*/

int cpu_claim_irq(unsigned int irq, struct irq_chip *type, void *data)
{
	if (irq_desc[irq].action)
		return -EBUSY;
	if (get_irq_chip(irq) != &cpu_interrupt_type)
		return -EBUSY;

	/* for iosapic interrupts */
	if (type) {
		set_irq_chip_and_handler(irq, type, handle_percpu_irq);
		set_irq_chip_data(irq, data);
		__cpu_unmask_irq(irq);
	}
	return 0;
}

int txn_claim_irq(int irq)
{
	return cpu_claim_irq(irq, NULL, NULL) ? -1 : irq;
}

/*
 * The bits_wide parameter accommodates the limitations of the HW/SW which
 * use these bits:
 * Legacy PA I/O (GSC/NIO): 5 bits (architected EIM register)
 * V-class (EPIC):          6 bits
 * N/L/A-class (iosapic):   8 bits
 * PCI 2.2 MSI:            16 bits
 * Some PCI devices:       32 bits (Symbios SCSI/ATM/HyperFabric)
 *
 * On the service provider side:
 * o PA 1.1 (and PA2.0 narrow mode)     5-bits (width of EIR register)
 * o PA 2.0 wide mode                   6-bits (per processor)
 * o IA64                               8-bits (0-256 total)
 *
 * So a Legacy PA I/O device on a PA 2.0 box can't use all the bits supported
 * by the processor...and the N/L-class I/O subsystem supports more bits than
 * PA2.0 has. The first case is the problem.
 */
int txn_alloc_irq(unsigned int bits_wide)
{
	int irq;

	/* never return irq 0 cause that's the interval timer */
	for (irq = CPU_IRQ_BASE + 1; irq <= CPU_IRQ_MAX; irq++) {
		if (cpu_claim_irq(irq, NULL, NULL) < 0)
			continue;
		if ((irq - CPU_IRQ_BASE) >= (1 << bits_wide))
			continue;
		return irq;
	}

	/* unlikely, but be prepared */
	return -1;
}


unsigned long txn_affinity_addr(unsigned int irq, int cpu)
{
#ifdef CONFIG_SMP
	struct irq_data *d = irq_get_irq_data(irq);
	cpumask_copy(d->affinity, cpumask_of(cpu));
#endif

	return per_cpu(cpu_data, cpu).txn_addr;
}


unsigned long txn_alloc_addr(unsigned int virt_irq)
{
	static int next_cpu = -1;

	next_cpu++; /* assign to "next" CPU we want this bugger on */

	/* validate entry */
	while ((next_cpu < nr_cpu_ids) &&
		(!per_cpu(cpu_data, next_cpu).txn_addr ||
		 !cpu_online(next_cpu)))
		next_cpu++;

	if (next_cpu >= nr_cpu_ids) 
		next_cpu = 0;	/* nothing else, assign monarch */

	return txn_affinity_addr(virt_irq, next_cpu);
}


unsigned int txn_alloc_data(unsigned int virt_irq)
{
	return virt_irq - CPU_IRQ_BASE;
}

static inline int eirr_to_irq(unsigned long eirr)
{
	int bit = fls_long(eirr);
	return (BITS_PER_LONG - bit) + TIMER_IRQ;
}

/* ONLY called from entry.S:intr_extint() */
void do_cpu_irq_mask(struct pt_regs *regs)
{
	struct pt_regs *old_regs;
	unsigned long eirr_val;
	int irq, cpu = smp_processor_id();
#ifdef CONFIG_SMP
	struct irq_desc *desc;
	cpumask_t dest;
#endif

	old_regs = set_irq_regs(regs);
	local_irq_disable();
	irq_enter();

	eirr_val = mfctl(23) & cpu_eiem & per_cpu(local_ack_eiem, cpu);
	if (!eirr_val)
		goto set_out;
	irq = eirr_to_irq(eirr_val);

#ifdef CONFIG_SMP
	desc = irq_to_desc(irq);
	cpumask_copy(&dest, desc->irq_data.affinity);
	if (CHECK_IRQ_PER_CPU(desc->status) &&
	    !cpu_isset(smp_processor_id(), dest)) {
		int cpu = first_cpu(dest);

		printk(KERN_DEBUG "redirecting irq %d from CPU %d to %d\n",
		       irq, smp_processor_id(), cpu);
		gsc_writel(irq + CPU_IRQ_BASE,
			   per_cpu(cpu_data, cpu).hpa);
		goto set_out;
	}
#endif
	generic_handle_irq(irq);

 out:
	irq_exit();
	set_irq_regs(old_regs);
	return;

 set_out:
	set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
	goto out;
}

static struct irqaction timer_action = {
	.handler = timer_interrupt,
	.name = "timer",
	.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_PERCPU | IRQF_IRQPOLL,
};

#ifdef CONFIG_SMP
static struct irqaction ipi_action = {
	.handler = ipi_interrupt,
	.name = "IPI",
	.flags = IRQF_DISABLED | IRQF_PERCPU,
};
#endif

static void claim_cpu_irqs(void)
{
	int i;
	for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) {
		set_irq_chip_and_handler(i, &cpu_interrupt_type,
					 handle_percpu_irq);
	}

	set_irq_handler(TIMER_IRQ, handle_percpu_irq);
	setup_irq(TIMER_IRQ, &timer_action);
#ifdef CONFIG_SMP
	set_irq_handler(IPI_IRQ, handle_percpu_irq);
	setup_irq(IPI_IRQ, &ipi_action);
#endif
}

void __init init_IRQ(void)
{
	local_irq_disable();	/* PARANOID - should already be disabled */
	mtctl(~0UL, 23);	/* EIRR : clear all pending external intr */
	claim_cpu_irqs();
#ifdef CONFIG_SMP
	if (!cpu_eiem)
		cpu_eiem = EIEM_MASK(IPI_IRQ) | EIEM_MASK(TIMER_IRQ);
#else
	cpu_eiem = EIEM_MASK(TIMER_IRQ);
#endif
        set_eiem(cpu_eiem);	/* EIEM : enable all external intr */

}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Code to handle x86 style IRQs plus some generic interrupt stuff.
	3	*
	4	* Copyright (C) 1992 Linus Torvalds
	5	* Copyright (C) 1994, 1995, 1996, 1997, 1998 Ralf Baechle
	6	* Copyright (C) 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org)
	7	* Copyright (C) 1999-2000 Grant Grundler
	8	* Copyright (c) 2005 Matthew Wilcox
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; either version 2, or (at your option)
	13	* any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	23	*/
	24	#include <linux/bitops.h>
1da177e4 LT	25	#include <linux/errno.h>
	26	#include <linux/init.h>
	27	#include <linux/interrupt.h>
	28	#include <linux/kernel_stat.h>
	29	#include <linux/seq_file.h>
	30	#include <linux/spinlock.h>
	31	#include <linux/types.h>
c2ab64d0	32	#include <asm/io.h>
1da177e4	33
1d4c452a KM	34	#include <asm/smp.h>
1d4c452a KM	35
1da177e4 LT	36	#undef PARISC_IRQ_CR16_COUNTS
1da177e4 LT	37
be577a52 MW	38	extern irqreturn_t timer_interrupt(int, void *);
be577a52 MW	39	extern irqreturn_t ipi_interrupt(int, void *);
1da177e4 LT	40
	41	#define EIEM_MASK(irq) (1UL<<(CPU_IRQ_MAX - irq))
	42
	43	/* Bits in EIEM correlate with cpu_irq_action[].
	44	** Numbered Big Endian! (ie bit 0 is MSB)
	45	*/
	46	static volatile unsigned long cpu_eiem = 0;
	47
7085689e	48	/*
462b529f	49	** local ACK bitmap ... habitually set to 1, but reset to zero
7085689e JB	50	** between ->ack() and ->end() of the interrupt to prevent
	51	** re-interruption of a processing interrupt.
	52	*/
7085689e JB	53	static DEFINE_PER_CPU(unsigned long, local_ack_eiem) = ~0UL;
7085689e JB	54
4c4231ea	55	static void cpu_mask_irq(struct irq_data *d)
1da177e4	56	{
4c4231ea	57	unsigned long eirr_bit = EIEM_MASK(d->irq);
1da177e4 LT	58
1da177e4 LT	59	cpu_eiem &= ~eirr_bit;
d911aed8 JB	60	/* Do nothing on the other CPUs. If they get this interrupt,
	61	* The & cpu_eiem in the do_cpu_irq_mask() ensures they won't
	62	* handle it, and the set_eiem() at the bottom will ensure it
	63	* then gets disabled */
1da177e4 LT	64	}
1da177e4 LT	65
4c4231ea	66	static void __cpu_unmask_irq(unsigned int irq)
1da177e4 LT	67	{
	68	unsigned long eirr_bit = EIEM_MASK(irq);
	69
1da177e4	70	cpu_eiem \|= eirr_bit;
d911aed8	71
d911aed8 JB	72	/* This is just a simple NOP IPI. But what it does is cause
	73	* all the other CPUs to do a set_eiem(cpu_eiem) at the end
	74	* of the interrupt handler */
	75	smp_send_all_nop();
1da177e4 LT	76	}
1da177e4 LT	77
4c4231ea TG	78	static void cpu_unmask_irq(struct irq_data *d)
	79	{
	80	__cpu_unmask_irq(d->irq);
	81	}
	82
	83	void cpu_ack_irq(struct irq_data *d)
7085689e	84	{
4c4231ea	85	unsigned long mask = EIEM_MASK(d->irq);
7085689e JB	86	int cpu = smp_processor_id();
	87
	88	/* Clear in EIEM so we can no longer process */
462b529f	89	per_cpu(local_ack_eiem, cpu) &= ~mask;
7085689e JB	90
7085689e JB	91	/* disable the interrupt */
462b529f GG	92	set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
462b529f GG	93
7085689e JB	94	/* and now ack it */
	95	mtctl(mask, 23);
	96	}
	97
4c4231ea	98	void cpu_eoi_irq(struct irq_data *d)
7085689e	99	{
4c4231ea	100	unsigned long mask = EIEM_MASK(d->irq);
7085689e JB	101	int cpu = smp_processor_id();
	102
	103	/* set it in the eiems---it's no longer in process */
462b529f	104	per_cpu(local_ack_eiem, cpu) \|= mask;
7085689e JB	105
7085689e JB	106	/* enable the interrupt */
462b529f	107	set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
7085689e JB	108	}
7085689e JB	109
c2ab64d0	110	#ifdef CONFIG_SMP
4c4231ea	111	int cpu_check_affinity(struct irq_data d, const struct cpumask dest)
c2ab64d0 JB	112	{
	113	int cpu_dest;
	114
	115	/* timer and ipi have to always be received on all CPUs */
4c4231ea	116	if (CHECK_IRQ_PER_CPU(irq_to_desc(d->irq)->status)) {
c2ab64d0	117	/* Bad linux design decision. The mask has already
4c4231ea TG	118	* been set; we must reset it. Will fix - tglx
	119	*/
	120	cpumask_setall(d->affinity);
c2ab64d0 JB	121	return -EINVAL;
	122	}
	123
	124	/* whatever mask they set, we just allow one CPU */
	125	cpu_dest = first_cpu(*dest);
c2ab64d0	126
8b6649c5	127	return cpu_dest;
c2ab64d0 JB	128	}
c2ab64d0 JB	129
4c4231ea TG	130	static int cpu_set_affinity_irq(struct irq_data d, const struct cpumask dest,
4c4231ea TG	131	bool force)
c2ab64d0	132	{
8b6649c5 KM	133	int cpu_dest;
8b6649c5 KM	134
4c4231ea	135	cpu_dest = cpu_check_affinity(d, dest);
8b6649c5	136	if (cpu_dest < 0)
d5dedd45	137	return -1;
c2ab64d0	138
4c4231ea	139	cpumask_copy(d->affinity, dest);
d5dedd45 YL	140
d5dedd45 YL	141	return 0;
c2ab64d0 JB	142	}
	143	#endif
	144
dfe07565	145	static struct irq_chip cpu_interrupt_type = {
4c4231ea TG	146	.name = "CPU",
	147	.irq_mask = cpu_mask_irq,
	148	.irq_unmask = cpu_unmask_irq,
	149	.irq_ack = cpu_ack_irq,
	150	.irq_eoi = cpu_eoi_irq,
c2ab64d0	151	#ifdef CONFIG_SMP
4c4231ea	152	.irq_set_affinity = cpu_set_affinity_irq,
c2ab64d0	153	#endif
c0ad90a3 IM	154	/* XXX: Needs to be written. We managed without it so far, but
	155	* we really ought to write it.
	156	*/
4c4231ea	157	.irq_retrigger = NULL,
1da177e4 LT	158	};
	159
	160	int show_interrupts(struct seq_file p, void v)
	161	{
	162	int i = (loff_t ) v, j;
	163	unsigned long flags;
	164
	165	if (i == 0) {
	166	seq_puts(p, " ");
	167	for_each_online_cpu(j)
	168	seq_printf(p, " CPU%d", j);
	169
	170	#ifdef PARISC_IRQ_CR16_COUNTS
	171	seq_printf(p, " [min/avg/max] (CPU cycle counts)");
	172	#endif
	173	seq_putc(p, '\n');
	174	}
	175
	176	if (i < NR_IRQS) {
	177	struct irqaction *action;
	178
239007b8	179	raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
1da177e4 LT	180	action = irq_desc[i].action;
	181	if (!action)
	182	goto skip;
	183	seq_printf(p, "%3d: ", i);
	184	#ifdef CONFIG_SMP
	185	for_each_online_cpu(j)
dee4102a	186	seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
1da177e4 LT	187	#else
	188	seq_printf(p, "%10u ", kstat_irqs(i));
	189	#endif
	190
4c4231ea	191	seq_printf(p, " %14s", irq_desc[i].irq_data.chip->name);
1da177e4 LT	192	#ifndef PARISC_IRQ_CR16_COUNTS
	193	seq_printf(p, " %s", action->name);
	194
	195	while ((action = action->next))
	196	seq_printf(p, ", %s", action->name);
	197	#else
	198	for ( ;action; action = action->next) {
	199	unsigned int k, avg, min, max;
	200
	201	min = max = action->cr16_hist[0];
	202
	203	for (avg = k = 0; k < PARISC_CR16_HIST_SIZE; k++) {
	204	int hist = action->cr16_hist[k];
	205
	206	if (hist) {
	207	avg += hist;
	208	} else
	209	break;
	210
	211	if (hist > max) max = hist;
	212	if (hist < min) min = hist;
	213	}
	214
	215	avg /= k;
	216	seq_printf(p, " %s[%d/%d/%d]", action->name,
	217	min,avg,max);
	218	}
	219	#endif
	220
	221	seq_putc(p, '\n');
	222	skip:
239007b8	223	raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
1da177e4 LT	224	}
	225
	226	return 0;
	227	}
	228
	229
	230
	231	/*
	232	** The following form a "set": Virtual IRQ, Transaction Address, Trans Data.
	233	** Respectively, these map to IRQ region+EIRR, Processor HPA, EIRR bit.
	234	**
	235	** To use txn_XXX() interfaces, get a Virtual IRQ first.
	236	** Then use that to get the Transaction address and data.
	237	*/
	238
5cfe87d3	239	int cpu_claim_irq(unsigned int irq, struct irq_chip type, void data)
1da177e4 LT	240	{
	241	if (irq_desc[irq].action)
	242	return -EBUSY;
4c4231ea	243	if (get_irq_chip(irq) != &cpu_interrupt_type)
1da177e4 LT	244	return -EBUSY;
1da177e4 LT	245
ba20085c	246	/* for iosapic interrupts */
1da177e4	247	if (type) {
51890613	248	set_irq_chip_and_handler(irq, type, handle_percpu_irq);
ba20085c	249	set_irq_chip_data(irq, data);
4c4231ea	250	__cpu_unmask_irq(irq);
1da177e4 LT	251	}
	252	return 0;
	253	}
	254
	255	int txn_claim_irq(int irq)
	256	{
	257	return cpu_claim_irq(irq, NULL, NULL) ? -1 : irq;
	258	}
	259
	260	/*
	261	* The bits_wide parameter accommodates the limitations of the HW/SW which
	262	* use these bits:
	263	* Legacy PA I/O (GSC/NIO): 5 bits (architected EIM register)
	264	* V-class (EPIC): 6 bits
	265	* N/L/A-class (iosapic): 8 bits
	266	* PCI 2.2 MSI: 16 bits
	267	* Some PCI devices: 32 bits (Symbios SCSI/ATM/HyperFabric)
	268	*
	269	* On the service provider side:
	270	* o PA 1.1 (and PA2.0 narrow mode) 5-bits (width of EIR register)
	271	* o PA 2.0 wide mode 6-bits (per processor)
	272	* o IA64 8-bits (0-256 total)
	273	*
	274	* So a Legacy PA I/O device on a PA 2.0 box can't use all the bits supported
	275	* by the processor...and the N/L-class I/O subsystem supports more bits than
	276	* PA2.0 has. The first case is the problem.
	277	*/
	278	int txn_alloc_irq(unsigned int bits_wide)
	279	{
	280	int irq;
	281
	282	/* never return irq 0 cause that's the interval timer */
	283	for (irq = CPU_IRQ_BASE + 1; irq <= CPU_IRQ_MAX; irq++) {
	284	if (cpu_claim_irq(irq, NULL, NULL) < 0)
	285	continue;
	286	if ((irq - CPU_IRQ_BASE) >= (1 << bits_wide))
	287	continue;
	288	return irq;
	289	}
	290
	291	/* unlikely, but be prepared */
	292	return -1;
	293	}
	294
03afe22f	295
c2ab64d0 JB	296	unsigned long txn_affinity_addr(unsigned int irq, int cpu)
c2ab64d0 JB	297	{
03afe22f	298	#ifdef CONFIG_SMP
4c4231ea TG	299	struct irq_data *d = irq_get_irq_data(irq);
4c4231ea TG	300	cpumask_copy(d->affinity, cpumask_of(cpu));
03afe22f	301	#endif
c2ab64d0	302
ef017beb	303	return per_cpu(cpu_data, cpu).txn_addr;
c2ab64d0 JB	304	}
c2ab64d0 JB	305
03afe22f	306
1da177e4 LT	307	unsigned long txn_alloc_addr(unsigned int virt_irq)
	308	{
	309	static int next_cpu = -1;
	310
	311	next_cpu++; /* assign to "next" CPU we want this bugger on */
	312
	313	/* validate entry */
bd071e1a	314	while ((next_cpu < nr_cpu_ids) &&
ef017beb HD	315	(!per_cpu(cpu_data, next_cpu).txn_addr \|\|
ef017beb HD	316	!cpu_online(next_cpu)))
1da177e4 LT	317	next_cpu++;
1da177e4 LT	318
bd071e1a	319	if (next_cpu >= nr_cpu_ids)
1da177e4 LT	320	next_cpu = 0; /* nothing else, assign monarch */
1da177e4 LT	321
c2ab64d0	322	return txn_affinity_addr(virt_irq, next_cpu);
1da177e4 LT	323	}
	324
	325
	326	unsigned int txn_alloc_data(unsigned int virt_irq)
	327	{
	328	return virt_irq - CPU_IRQ_BASE;
	329	}
	330
7085689e JB	331	static inline int eirr_to_irq(unsigned long eirr)
7085689e JB	332	{
0c2de3c6	333	int bit = fls_long(eirr);
7085689e JB	334	return (BITS_PER_LONG - bit) + TIMER_IRQ;
	335	}
	336
1da177e4 LT	337	/* ONLY called from entry.S:intr_extint() */
	338	void do_cpu_irq_mask(struct pt_regs *regs)
	339	{
e11e30a0	340	struct pt_regs *old_regs;
1da177e4	341	unsigned long eirr_val;
7085689e	342	int irq, cpu = smp_processor_id();
03afe22f	343	#ifdef CONFIG_SMP
4c4231ea	344	struct irq_desc *desc;
7085689e	345	cpumask_t dest;
03afe22f	346	#endif
1da177e4	347
e11e30a0	348	old_regs = set_irq_regs(regs);
7085689e JB	349	local_irq_disable();
7085689e JB	350	irq_enter();
1da177e4	351
462b529f	352	eirr_val = mfctl(23) & cpu_eiem & per_cpu(local_ack_eiem, cpu);
7085689e JB	353	if (!eirr_val)
	354	goto set_out;
	355	irq = eirr_to_irq(eirr_val);
c2ab64d0	356
7085689e	357	#ifdef CONFIG_SMP
4c4231ea TG	358	desc = irq_to_desc(irq);
	359	cpumask_copy(&dest, desc->irq_data.affinity);
	360	if (CHECK_IRQ_PER_CPU(desc->status) &&
7085689e JB	361	!cpu_isset(smp_processor_id(), dest)) {
	362	int cpu = first_cpu(dest);
	363
	364	printk(KERN_DEBUG "redirecting irq %d from CPU %d to %d\n",
	365	irq, smp_processor_id(), cpu);
	366	gsc_writel(irq + CPU_IRQ_BASE,
ef017beb	367	per_cpu(cpu_data, cpu).hpa);
7085689e	368	goto set_out;
1da177e4	369	}
7085689e	370	#endif
ba20085c	371	generic_handle_irq(irq);
3f902886	372
7085689e	373	out:
1da177e4	374	irq_exit();
e11e30a0	375	set_irq_regs(old_regs);
7085689e	376	return;
1da177e4	377
7085689e	378	set_out:
462b529f	379	set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
7085689e JB	380	goto out;
7085689e JB	381	}
1da177e4 LT	382
	383	static struct irqaction timer_action = {
	384	.handler = timer_interrupt,
	385	.name = "timer",
57501c70	386	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_PERCPU \| IRQF_IRQPOLL,
1da177e4 LT	387	};
	388
	389	#ifdef CONFIG_SMP
	390	static struct irqaction ipi_action = {
	391	.handler = ipi_interrupt,
	392	.name = "IPI",
7085689e	393	.flags = IRQF_DISABLED \| IRQF_PERCPU,
1da177e4 LT	394	};
	395	#endif
	396
	397	static void claim_cpu_irqs(void)
	398	{
	399	int i;
	400	for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) {
4d4f681d	401	set_irq_chip_and_handler(i, &cpu_interrupt_type,
d16cd297	402	handle_percpu_irq);
1da177e4 LT	403	}
1da177e4 LT	404
ba20085c KM	405	set_irq_handler(TIMER_IRQ, handle_percpu_irq);
ba20085c KM	406	setup_irq(TIMER_IRQ, &timer_action);
1da177e4	407	#ifdef CONFIG_SMP
ba20085c KM	408	set_irq_handler(IPI_IRQ, handle_percpu_irq);
ba20085c KM	409	setup_irq(IPI_IRQ, &ipi_action);
1da177e4 LT	410	#endif
	411	}
	412
	413	void __init init_IRQ(void)
	414	{
	415	local_irq_disable(); /* PARANOID - should already be disabled */
	416	mtctl(~0UL, 23); /* EIRR : clear all pending external intr */
	417	claim_cpu_irqs();
	418	#ifdef CONFIG_SMP
	419	if (!cpu_eiem)
	420	cpu_eiem = EIEM_MASK(IPI_IRQ) \| EIEM_MASK(TIMER_IRQ);
	421	#else
	422	cpu_eiem = EIEM_MASK(TIMER_IRQ);
	423	#endif
	424	set_eiem(cpu_eiem); /* EIEM : enable all external intr */
	425
	426	}
ba20085c	427