[deliverable/linux.git] / arch / parisc / kernel / irq.c

/* 
 * Code to handle x86 style IRQs plus some generic interrupt stuff.
 *
 * Copyright (C) 1992 Linus Torvalds
 * Copyright (C) 1994, 1995, 1996, 1997, 1998 Ralf Baechle
 * Copyright (C) 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org)
 * Copyright (C) 1999-2000 Grant Grundler
 * Copyright (c) 2005 Matthew Wilcox
 *
 *    This program is free software; you can redistribute it and/or modify
 *    it under the terms of the GNU General Public License as published by
 *    the Free Software Foundation; either version 2, or (at your option)
 *    any later version.
 *
 *    This program is distributed in the hope that it will be useful,
 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *    GNU General Public License for more details.
 *
 *    You should have received a copy of the GNU General Public License
 *    along with this program; if not, write to the Free Software
 *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */
#include <linux/bitops.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/seq_file.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#include <asm/io.h>

#include <asm/smp.h>

#undef PARISC_IRQ_CR16_COUNTS

extern irqreturn_t timer_interrupt(int, void *);
extern irqreturn_t ipi_interrupt(int, void *);

#define EIEM_MASK(irq)       (1UL<<(CPU_IRQ_MAX - irq))

/* Bits in EIEM correlate with cpu_irq_action[].
** Numbered *Big Endian*! (ie bit 0 is MSB)
*/
static volatile unsigned long cpu_eiem = 0;

/*
** local ACK bitmap ... habitually set to 1, but reset to zero
** between ->ack() and ->end() of the interrupt to prevent
** re-interruption of a processing interrupt.
*/
static DEFINE_PER_CPU(unsigned long, local_ack_eiem) = ~0UL;

static void cpu_mask_irq(struct irq_data *d)
{
	unsigned long eirr_bit = EIEM_MASK(d->irq);

	cpu_eiem &= ~eirr_bit;
	/* Do nothing on the other CPUs.  If they get this interrupt,
	 * The & cpu_eiem in the do_cpu_irq_mask() ensures they won't
	 * handle it, and the set_eiem() at the bottom will ensure it
	 * then gets disabled */
}

static void __cpu_unmask_irq(unsigned int irq)
{
	unsigned long eirr_bit = EIEM_MASK(irq);

	cpu_eiem |= eirr_bit;

	/* This is just a simple NOP IPI.  But what it does is cause
	 * all the other CPUs to do a set_eiem(cpu_eiem) at the end
	 * of the interrupt handler */
	smp_send_all_nop();
}

static void cpu_unmask_irq(struct irq_data *d)
{
	__cpu_unmask_irq(d->irq);
}

void cpu_ack_irq(struct irq_data *d)
{
	unsigned long mask = EIEM_MASK(d->irq);
	int cpu = smp_processor_id();

	/* Clear in EIEM so we can no longer process */
	per_cpu(local_ack_eiem, cpu) &= ~mask;

	/* disable the interrupt */
	set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));

	/* and now ack it */
	mtctl(mask, 23);
}

void cpu_eoi_irq(struct irq_data *d)
{
	unsigned long mask = EIEM_MASK(d->irq);
	int cpu = smp_processor_id();

	/* set it in the eiems---it's no longer in process */
	per_cpu(local_ack_eiem, cpu) |= mask;

	/* enable the interrupt */
	set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
}

#ifdef CONFIG_SMP
int cpu_check_affinity(struct irq_data *d, const struct cpumask *dest)
{
	int cpu_dest;

	/* timer and ipi have to always be received on all CPUs */
	if (irqd_is_per_cpu(d))
		return -EINVAL;

	/* whatever mask they set, we just allow one CPU */
	cpu_dest = first_cpu(*dest);

	return cpu_dest;
}

static int cpu_set_affinity_irq(struct irq_data *d, const struct cpumask *dest,
				bool force)
{
	int cpu_dest;

	cpu_dest = cpu_check_affinity(d, dest);
	if (cpu_dest < 0)
		return -1;

	cpumask_copy(d->affinity, dest);

	return 0;
}
#endif

static struct irq_chip cpu_interrupt_type = {
	.name			= "CPU",
	.irq_mask		= cpu_mask_irq,
	.irq_unmask		= cpu_unmask_irq,
	.irq_ack		= cpu_ack_irq,
	.irq_eoi		= cpu_eoi_irq,
#ifdef CONFIG_SMP
	.irq_set_affinity	= cpu_set_affinity_irq,
#endif
	/* XXX: Needs to be written.  We managed without it so far, but
	 * we really ought to write it.
	 */
	.irq_retrigger	= NULL,
};

int show_interrupts(struct seq_file *p, void *v)
{
	int i = *(loff_t *) v, j;
	unsigned long flags;

	if (i == 0) {
		seq_puts(p, "    ");
		for_each_online_cpu(j)
			seq_printf(p, "       CPU%d", j);

#ifdef PARISC_IRQ_CR16_COUNTS
		seq_printf(p, " [min/avg/max] (CPU cycle counts)");
#endif
		seq_putc(p, '\n');
	}

	if (i < NR_IRQS) {
		struct irq_desc *desc = irq_to_desc(i);
		struct irqaction *action;

		raw_spin_lock_irqsave(&desc->lock, flags);
		action = desc->action;
		if (!action)
			goto skip;
		seq_printf(p, "%3d: ", i);
#ifdef CONFIG_SMP
		for_each_online_cpu(j)
			seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
#else
		seq_printf(p, "%10u ", kstat_irqs(i));
#endif

		seq_printf(p, " %14s", irq_desc_get_chip(desc)->name);
#ifndef PARISC_IRQ_CR16_COUNTS
		seq_printf(p, "  %s", action->name);

		while ((action = action->next))
			seq_printf(p, ", %s", action->name);
#else
		for ( ;action; action = action->next) {
			unsigned int k, avg, min, max;

			min = max = action->cr16_hist[0];

			for (avg = k = 0; k < PARISC_CR16_HIST_SIZE; k++) {
				int hist = action->cr16_hist[k];

				if (hist) {
					avg += hist;
				} else
					break;

				if (hist > max) max = hist;
				if (hist < min) min = hist;
			}

			avg /= k;
			seq_printf(p, " %s[%d/%d/%d]", action->name,
					min,avg,max);
		}
#endif

		seq_putc(p, '\n');
 skip:
		raw_spin_unlock_irqrestore(&desc->lock, flags);
	}

	return 0;
}


/*
** The following form a "set": Virtual IRQ, Transaction Address, Trans Data.
** Respectively, these map to IRQ region+EIRR, Processor HPA, EIRR bit.
**
** To use txn_XXX() interfaces, get a Virtual IRQ first.
** Then use that to get the Transaction address and data.
*/

int cpu_claim_irq(unsigned int irq, struct irq_chip *type, void *data)
{
	if (irq_has_action(irq))
		return -EBUSY;
	if (irq_get_chip(irq) != &cpu_interrupt_type)
		return -EBUSY;

	/* for iosapic interrupts */
	if (type) {
		irq_set_chip_and_handler(irq, type, handle_percpu_irq);
		irq_set_chip_data(irq, data);
		__cpu_unmask_irq(irq);
	}
	return 0;
}

int txn_claim_irq(int irq)
{
	return cpu_claim_irq(irq, NULL, NULL) ? -1 : irq;
}

/*
 * The bits_wide parameter accommodates the limitations of the HW/SW which
 * use these bits:
 * Legacy PA I/O (GSC/NIO): 5 bits (architected EIM register)
 * V-class (EPIC):          6 bits
 * N/L/A-class (iosapic):   8 bits
 * PCI 2.2 MSI:            16 bits
 * Some PCI devices:       32 bits (Symbios SCSI/ATM/HyperFabric)
 *
 * On the service provider side:
 * o PA 1.1 (and PA2.0 narrow mode)     5-bits (width of EIR register)
 * o PA 2.0 wide mode                   6-bits (per processor)
 * o IA64                               8-bits (0-256 total)
 *
 * So a Legacy PA I/O device on a PA 2.0 box can't use all the bits supported
 * by the processor...and the N/L-class I/O subsystem supports more bits than
 * PA2.0 has. The first case is the problem.
 */
int txn_alloc_irq(unsigned int bits_wide)
{
	int irq;

	/* never return irq 0 cause that's the interval timer */
	for (irq = CPU_IRQ_BASE + 1; irq <= CPU_IRQ_MAX; irq++) {
		if (cpu_claim_irq(irq, NULL, NULL) < 0)
			continue;
		if ((irq - CPU_IRQ_BASE) >= (1 << bits_wide))
			continue;
		return irq;
	}

	/* unlikely, but be prepared */
	return -1;
}


unsigned long txn_affinity_addr(unsigned int irq, int cpu)
{
#ifdef CONFIG_SMP
	struct irq_data *d = irq_get_irq_data(irq);
	cpumask_copy(d->affinity, cpumask_of(cpu));
#endif

	return per_cpu(cpu_data, cpu).txn_addr;
}


unsigned long txn_alloc_addr(unsigned int virt_irq)
{
	static int next_cpu = -1;

	next_cpu++; /* assign to "next" CPU we want this bugger on */

	/* validate entry */
	while ((next_cpu < nr_cpu_ids) &&
		(!per_cpu(cpu_data, next_cpu).txn_addr ||
		 !cpu_online(next_cpu)))
		next_cpu++;

	if (next_cpu >= nr_cpu_ids) 
		next_cpu = 0;	/* nothing else, assign monarch */

	return txn_affinity_addr(virt_irq, next_cpu);
}


unsigned int txn_alloc_data(unsigned int virt_irq)
{
	return virt_irq - CPU_IRQ_BASE;
}

static inline int eirr_to_irq(unsigned long eirr)
{
	int bit = fls_long(eirr);
	return (BITS_PER_LONG - bit) + TIMER_IRQ;
}

/* ONLY called from entry.S:intr_extint() */
void do_cpu_irq_mask(struct pt_regs *regs)
{
	struct pt_regs *old_regs;
	unsigned long eirr_val;
	int irq, cpu = smp_processor_id();
#ifdef CONFIG_SMP
	struct irq_desc *desc;
	cpumask_t dest;
#endif

	old_regs = set_irq_regs(regs);
	local_irq_disable();
	irq_enter();

	eirr_val = mfctl(23) & cpu_eiem & per_cpu(local_ack_eiem, cpu);
	if (!eirr_val)
		goto set_out;
	irq = eirr_to_irq(eirr_val);

#ifdef CONFIG_SMP
	desc = irq_to_desc(irq);
	cpumask_copy(&dest, desc->irq_data.affinity);
	if (irqd_is_per_cpu(&desc->irq_data) &&
	    !cpu_isset(smp_processor_id(), dest)) {
		int cpu = first_cpu(dest);

		printk(KERN_DEBUG "redirecting irq %d from CPU %d to %d\n",
		       irq, smp_processor_id(), cpu);
		gsc_writel(irq + CPU_IRQ_BASE,
			   per_cpu(cpu_data, cpu).hpa);
		goto set_out;
	}
#endif
	generic_handle_irq(irq);

 out:
	irq_exit();
	set_irq_regs(old_regs);
	return;

 set_out:
	set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
	goto out;
}

static struct irqaction timer_action = {
	.handler = timer_interrupt,
	.name = "timer",
	.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_PERCPU | IRQF_IRQPOLL,
};

#ifdef CONFIG_SMP
static struct irqaction ipi_action = {
	.handler = ipi_interrupt,
	.name = "IPI",
	.flags = IRQF_DISABLED | IRQF_PERCPU,
};
#endif

static void claim_cpu_irqs(void)
{
	int i;
	for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) {
		irq_set_chip_and_handler(i, &cpu_interrupt_type,
					 handle_percpu_irq);
	}

	irq_set_handler(TIMER_IRQ, handle_percpu_irq);
	setup_irq(TIMER_IRQ, &timer_action);
#ifdef CONFIG_SMP
	irq_set_handler(IPI_IRQ, handle_percpu_irq);
	setup_irq(IPI_IRQ, &ipi_action);
#endif
}

void __init init_IRQ(void)
{
	local_irq_disable();	/* PARANOID - should already be disabled */
	mtctl(~0UL, 23);	/* EIRR : clear all pending external intr */
#ifdef CONFIG_SMP
	if (!cpu_eiem) {
		claim_cpu_irqs();
		cpu_eiem = EIEM_MASK(IPI_IRQ) | EIEM_MASK(TIMER_IRQ);
	}
#else
	claim_cpu_irqs();
	cpu_eiem = EIEM_MASK(TIMER_IRQ);
#endif
        set_eiem(cpu_eiem);	/* EIEM : enable all external intr */

}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Code to handle x86 style IRQs plus some generic interrupt stuff.
	3	*
	4	* Copyright (C) 1992 Linus Torvalds
	5	* Copyright (C) 1994, 1995, 1996, 1997, 1998 Ralf Baechle
	6	* Copyright (C) 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org)
	7	* Copyright (C) 1999-2000 Grant Grundler
	8	* Copyright (c) 2005 Matthew Wilcox
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; either version 2, or (at your option)
	13	* any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	23	*/
	24	#include <linux/bitops.h>
1da177e4 LT	25	#include <linux/errno.h>
	26	#include <linux/init.h>
	27	#include <linux/interrupt.h>
	28	#include <linux/kernel_stat.h>
	29	#include <linux/seq_file.h>
	30	#include <linux/spinlock.h>
	31	#include <linux/types.h>
c2ab64d0	32	#include <asm/io.h>
1da177e4	33
1d4c452a KM	34	#include <asm/smp.h>
1d4c452a KM	35
1da177e4 LT	36	#undef PARISC_IRQ_CR16_COUNTS
1da177e4 LT	37
be577a52 MW	38	extern irqreturn_t timer_interrupt(int, void *);
be577a52 MW	39	extern irqreturn_t ipi_interrupt(int, void *);
1da177e4 LT	40
	41	#define EIEM_MASK(irq) (1UL<<(CPU_IRQ_MAX - irq))
	42
	43	/* Bits in EIEM correlate with cpu_irq_action[].
	44	** Numbered Big Endian! (ie bit 0 is MSB)
	45	*/
	46	static volatile unsigned long cpu_eiem = 0;
	47
7085689e	48	/*
462b529f	49	** local ACK bitmap ... habitually set to 1, but reset to zero
7085689e JB	50	** between ->ack() and ->end() of the interrupt to prevent
	51	** re-interruption of a processing interrupt.
	52	*/
7085689e JB	53	static DEFINE_PER_CPU(unsigned long, local_ack_eiem) = ~0UL;
7085689e JB	54
4c4231ea	55	static void cpu_mask_irq(struct irq_data *d)
1da177e4	56	{
4c4231ea	57	unsigned long eirr_bit = EIEM_MASK(d->irq);
1da177e4 LT	58
1da177e4 LT	59	cpu_eiem &= ~eirr_bit;
d911aed8 JB	60	/* Do nothing on the other CPUs. If they get this interrupt,
	61	* The & cpu_eiem in the do_cpu_irq_mask() ensures they won't
	62	* handle it, and the set_eiem() at the bottom will ensure it
	63	* then gets disabled */
1da177e4 LT	64	}
1da177e4 LT	65
4c4231ea	66	static void __cpu_unmask_irq(unsigned int irq)
1da177e4 LT	67	{
	68	unsigned long eirr_bit = EIEM_MASK(irq);
	69
1da177e4	70	cpu_eiem \|= eirr_bit;
d911aed8	71
d911aed8 JB	72	/* This is just a simple NOP IPI. But what it does is cause
	73	* all the other CPUs to do a set_eiem(cpu_eiem) at the end
	74	* of the interrupt handler */
	75	smp_send_all_nop();
1da177e4 LT	76	}
1da177e4 LT	77
4c4231ea TG	78	static void cpu_unmask_irq(struct irq_data *d)
	79	{
	80	__cpu_unmask_irq(d->irq);
	81	}
	82
	83	void cpu_ack_irq(struct irq_data *d)
7085689e	84	{
4c4231ea	85	unsigned long mask = EIEM_MASK(d->irq);
7085689e JB	86	int cpu = smp_processor_id();
	87
	88	/* Clear in EIEM so we can no longer process */
462b529f	89	per_cpu(local_ack_eiem, cpu) &= ~mask;
7085689e JB	90
7085689e JB	91	/* disable the interrupt */
462b529f GG	92	set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
462b529f GG	93
7085689e JB	94	/* and now ack it */
	95	mtctl(mask, 23);
	96	}
	97
4c4231ea	98	void cpu_eoi_irq(struct irq_data *d)
7085689e	99	{
4c4231ea	100	unsigned long mask = EIEM_MASK(d->irq);
7085689e JB	101	int cpu = smp_processor_id();
	102
	103	/* set it in the eiems---it's no longer in process */
462b529f	104	per_cpu(local_ack_eiem, cpu) \|= mask;
7085689e JB	105
7085689e JB	106	/* enable the interrupt */
462b529f	107	set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
7085689e JB	108	}
7085689e JB	109
c2ab64d0	110	#ifdef CONFIG_SMP
4c4231ea	111	int cpu_check_affinity(struct irq_data d, const struct cpumask dest)
c2ab64d0 JB	112	{
	113	int cpu_dest;
	114
	115	/* timer and ipi have to always be received on all CPUs */
337ce681	116	if (irqd_is_per_cpu(d))
c2ab64d0	117	return -EINVAL;
c2ab64d0 JB	118
	119	/* whatever mask they set, we just allow one CPU */
	120	cpu_dest = first_cpu(*dest);
c2ab64d0	121
8b6649c5	122	return cpu_dest;
c2ab64d0 JB	123	}
c2ab64d0 JB	124
4c4231ea TG	125	static int cpu_set_affinity_irq(struct irq_data d, const struct cpumask dest,
4c4231ea TG	126	bool force)
c2ab64d0	127	{
8b6649c5 KM	128	int cpu_dest;
8b6649c5 KM	129
4c4231ea	130	cpu_dest = cpu_check_affinity(d, dest);
8b6649c5	131	if (cpu_dest < 0)
d5dedd45	132	return -1;
c2ab64d0	133
4c4231ea	134	cpumask_copy(d->affinity, dest);
d5dedd45 YL	135
d5dedd45 YL	136	return 0;
c2ab64d0 JB	137	}
	138	#endif
	139
dfe07565	140	static struct irq_chip cpu_interrupt_type = {
4c4231ea TG	141	.name = "CPU",
	142	.irq_mask = cpu_mask_irq,
	143	.irq_unmask = cpu_unmask_irq,
	144	.irq_ack = cpu_ack_irq,
	145	.irq_eoi = cpu_eoi_irq,
c2ab64d0	146	#ifdef CONFIG_SMP
4c4231ea	147	.irq_set_affinity = cpu_set_affinity_irq,
c2ab64d0	148	#endif
c0ad90a3 IM	149	/* XXX: Needs to be written. We managed without it so far, but
	150	* we really ought to write it.
	151	*/
4c4231ea	152	.irq_retrigger = NULL,
1da177e4 LT	153	};
	154
	155	int show_interrupts(struct seq_file p, void v)
	156	{
	157	int i = (loff_t ) v, j;
	158	unsigned long flags;
	159
	160	if (i == 0) {
	161	seq_puts(p, " ");
	162	for_each_online_cpu(j)
	163	seq_printf(p, " CPU%d", j);
	164
	165	#ifdef PARISC_IRQ_CR16_COUNTS
	166	seq_printf(p, " [min/avg/max] (CPU cycle counts)");
	167	#endif
	168	seq_putc(p, '\n');
	169	}
	170
	171	if (i < NR_IRQS) {
68f20f43	172	struct irq_desc *desc = irq_to_desc(i);
1da177e4 LT	173	struct irqaction *action;
1da177e4 LT	174
68f20f43 TG	175	raw_spin_lock_irqsave(&desc->lock, flags);
68f20f43 TG	176	action = desc->action;
1da177e4 LT	177	if (!action)
	178	goto skip;
	179	seq_printf(p, "%3d: ", i);
	180	#ifdef CONFIG_SMP
	181	for_each_online_cpu(j)
dee4102a	182	seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
1da177e4 LT	183	#else
	184	seq_printf(p, "%10u ", kstat_irqs(i));
	185	#endif
	186
68f20f43	187	seq_printf(p, " %14s", irq_desc_get_chip(desc)->name);
1da177e4 LT	188	#ifndef PARISC_IRQ_CR16_COUNTS
	189	seq_printf(p, " %s", action->name);
	190
	191	while ((action = action->next))
	192	seq_printf(p, ", %s", action->name);
	193	#else
	194	for ( ;action; action = action->next) {
	195	unsigned int k, avg, min, max;
	196
	197	min = max = action->cr16_hist[0];
	198
	199	for (avg = k = 0; k < PARISC_CR16_HIST_SIZE; k++) {
	200	int hist = action->cr16_hist[k];
	201
	202	if (hist) {
	203	avg += hist;
	204	} else
	205	break;
	206
	207	if (hist > max) max = hist;
	208	if (hist < min) min = hist;
	209	}
	210
	211	avg /= k;
	212	seq_printf(p, " %s[%d/%d/%d]", action->name,
	213	min,avg,max);
	214	}
	215	#endif
	216
	217	seq_putc(p, '\n');
	218	skip:
68f20f43	219	raw_spin_unlock_irqrestore(&desc->lock, flags);
1da177e4 LT	220	}
	221
	222	return 0;
	223	}
	224
	225
	226
	227	/*
	228	** The following form a "set": Virtual IRQ, Transaction Address, Trans Data.
	229	** Respectively, these map to IRQ region+EIRR, Processor HPA, EIRR bit.
	230	**
	231	** To use txn_XXX() interfaces, get a Virtual IRQ first.
	232	** Then use that to get the Transaction address and data.
	233	*/
	234
5cfe87d3	235	int cpu_claim_irq(unsigned int irq, struct irq_chip type, void data)
1da177e4	236	{
68f20f43	237	if (irq_has_action(irq))
1da177e4	238	return -EBUSY;
e2f571d2	239	if (irq_get_chip(irq) != &cpu_interrupt_type)
1da177e4 LT	240	return -EBUSY;
1da177e4 LT	241
ba20085c	242	/* for iosapic interrupts */
1da177e4	243	if (type) {
e2f571d2 TG	244	irq_set_chip_and_handler(irq, type, handle_percpu_irq);
e2f571d2 TG	245	irq_set_chip_data(irq, data);
4c4231ea	246	__cpu_unmask_irq(irq);
1da177e4 LT	247	}
	248	return 0;
	249	}
	250
	251	int txn_claim_irq(int irq)
	252	{
	253	return cpu_claim_irq(irq, NULL, NULL) ? -1 : irq;
	254	}
	255
	256	/*
	257	* The bits_wide parameter accommodates the limitations of the HW/SW which
	258	* use these bits:
	259	* Legacy PA I/O (GSC/NIO): 5 bits (architected EIM register)
	260	* V-class (EPIC): 6 bits
	261	* N/L/A-class (iosapic): 8 bits
	262	* PCI 2.2 MSI: 16 bits
	263	* Some PCI devices: 32 bits (Symbios SCSI/ATM/HyperFabric)
	264	*
	265	* On the service provider side:
	266	* o PA 1.1 (and PA2.0 narrow mode) 5-bits (width of EIR register)
	267	* o PA 2.0 wide mode 6-bits (per processor)
	268	* o IA64 8-bits (0-256 total)
	269	*
	270	* So a Legacy PA I/O device on a PA 2.0 box can't use all the bits supported
	271	* by the processor...and the N/L-class I/O subsystem supports more bits than
	272	* PA2.0 has. The first case is the problem.
	273	*/
	274	int txn_alloc_irq(unsigned int bits_wide)
	275	{
	276	int irq;
	277
	278	/* never return irq 0 cause that's the interval timer */
	279	for (irq = CPU_IRQ_BASE + 1; irq <= CPU_IRQ_MAX; irq++) {
	280	if (cpu_claim_irq(irq, NULL, NULL) < 0)
	281	continue;
	282	if ((irq - CPU_IRQ_BASE) >= (1 << bits_wide))
	283	continue;
	284	return irq;
	285	}
	286
	287	/* unlikely, but be prepared */
	288	return -1;
	289	}
	290
03afe22f	291
c2ab64d0 JB	292	unsigned long txn_affinity_addr(unsigned int irq, int cpu)
c2ab64d0 JB	293	{
03afe22f	294	#ifdef CONFIG_SMP
4c4231ea TG	295	struct irq_data *d = irq_get_irq_data(irq);
4c4231ea TG	296	cpumask_copy(d->affinity, cpumask_of(cpu));
03afe22f	297	#endif
c2ab64d0	298
ef017beb	299	return per_cpu(cpu_data, cpu).txn_addr;
c2ab64d0 JB	300	}
c2ab64d0 JB	301
03afe22f	302
1da177e4 LT	303	unsigned long txn_alloc_addr(unsigned int virt_irq)
	304	{
	305	static int next_cpu = -1;
	306
	307	next_cpu++; /* assign to "next" CPU we want this bugger on */
	308
	309	/* validate entry */
bd071e1a	310	while ((next_cpu < nr_cpu_ids) &&
ef017beb HD	311	(!per_cpu(cpu_data, next_cpu).txn_addr \|\|
ef017beb HD	312	!cpu_online(next_cpu)))
1da177e4 LT	313	next_cpu++;
1da177e4 LT	314
bd071e1a	315	if (next_cpu >= nr_cpu_ids)
1da177e4 LT	316	next_cpu = 0; /* nothing else, assign monarch */
1da177e4 LT	317
c2ab64d0	318	return txn_affinity_addr(virt_irq, next_cpu);
1da177e4 LT	319	}
	320
	321
	322	unsigned int txn_alloc_data(unsigned int virt_irq)
	323	{
	324	return virt_irq - CPU_IRQ_BASE;
	325	}
	326
7085689e JB	327	static inline int eirr_to_irq(unsigned long eirr)
7085689e JB	328	{
0c2de3c6	329	int bit = fls_long(eirr);
7085689e JB	330	return (BITS_PER_LONG - bit) + TIMER_IRQ;
	331	}
	332
1da177e4 LT	333	/* ONLY called from entry.S:intr_extint() */
	334	void do_cpu_irq_mask(struct pt_regs *regs)
	335	{
e11e30a0	336	struct pt_regs *old_regs;
1da177e4	337	unsigned long eirr_val;
7085689e	338	int irq, cpu = smp_processor_id();
03afe22f	339	#ifdef CONFIG_SMP
4c4231ea	340	struct irq_desc *desc;
7085689e	341	cpumask_t dest;
03afe22f	342	#endif
1da177e4	343
e11e30a0	344	old_regs = set_irq_regs(regs);
7085689e JB	345	local_irq_disable();
7085689e JB	346	irq_enter();
1da177e4	347
462b529f	348	eirr_val = mfctl(23) & cpu_eiem & per_cpu(local_ack_eiem, cpu);
7085689e JB	349	if (!eirr_val)
	350	goto set_out;
	351	irq = eirr_to_irq(eirr_val);
c2ab64d0	352
7085689e	353	#ifdef CONFIG_SMP
4c4231ea TG	354	desc = irq_to_desc(irq);
4c4231ea TG	355	cpumask_copy(&dest, desc->irq_data.affinity);
337ce681	356	if (irqd_is_per_cpu(&desc->irq_data) &&
7085689e JB	357	!cpu_isset(smp_processor_id(), dest)) {
	358	int cpu = first_cpu(dest);
	359
	360	printk(KERN_DEBUG "redirecting irq %d from CPU %d to %d\n",
	361	irq, smp_processor_id(), cpu);
	362	gsc_writel(irq + CPU_IRQ_BASE,
ef017beb	363	per_cpu(cpu_data, cpu).hpa);
7085689e	364	goto set_out;
1da177e4	365	}
7085689e	366	#endif
ba20085c	367	generic_handle_irq(irq);
3f902886	368
7085689e	369	out:
1da177e4	370	irq_exit();
e11e30a0	371	set_irq_regs(old_regs);
7085689e	372	return;
1da177e4	373
7085689e	374	set_out:
462b529f	375	set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
7085689e JB	376	goto out;
7085689e JB	377	}
1da177e4 LT	378
	379	static struct irqaction timer_action = {
	380	.handler = timer_interrupt,
	381	.name = "timer",
57501c70	382	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_PERCPU \| IRQF_IRQPOLL,
1da177e4 LT	383	};
	384
	385	#ifdef CONFIG_SMP
	386	static struct irqaction ipi_action = {
	387	.handler = ipi_interrupt,
	388	.name = "IPI",
7085689e	389	.flags = IRQF_DISABLED \| IRQF_PERCPU,
1da177e4 LT	390	};
	391	#endif
	392
	393	static void claim_cpu_irqs(void)
	394	{
	395	int i;
	396	for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) {
e2f571d2	397	irq_set_chip_and_handler(i, &cpu_interrupt_type,
d16cd297	398	handle_percpu_irq);
1da177e4 LT	399	}
1da177e4 LT	400
e2f571d2	401	irq_set_handler(TIMER_IRQ, handle_percpu_irq);
ba20085c	402	setup_irq(TIMER_IRQ, &timer_action);
1da177e4	403	#ifdef CONFIG_SMP
e2f571d2	404	irq_set_handler(IPI_IRQ, handle_percpu_irq);
ba20085c	405	setup_irq(IPI_IRQ, &ipi_action);
1da177e4 LT	406	#endif
	407	}
	408
	409	void __init init_IRQ(void)
	410	{
	411	local_irq_disable(); /* PARANOID - should already be disabled */
	412	mtctl(~0UL, 23); /* EIRR : clear all pending external intr */
1da177e4	413	#ifdef CONFIG_SMP
cac1f12b JDA	414	if (!cpu_eiem) {
cac1f12b JDA	415	claim_cpu_irqs();
1da177e4	416	cpu_eiem = EIEM_MASK(IPI_IRQ) \| EIEM_MASK(TIMER_IRQ);
cac1f12b	417	}
1da177e4	418	#else
cac1f12b	419	claim_cpu_irqs();
1da177e4 LT	420	cpu_eiem = EIEM_MASK(TIMER_IRQ);
	421	#endif
	422	set_eiem(cpu_eiem); /* EIEM : enable all external intr */
	423
	424	}
ba20085c	425