[deliverable/linux.git] / arch / parisc / kernel / irq.c

/* 
 * Code to handle x86 style IRQs plus some generic interrupt stuff.
 *
 * Copyright (C) 1992 Linus Torvalds
 * Copyright (C) 1994, 1995, 1996, 1997, 1998 Ralf Baechle
 * Copyright (C) 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org)
 * Copyright (C) 1999-2000 Grant Grundler
 * Copyright (c) 2005 Matthew Wilcox
 *
 *    This program is free software; you can redistribute it and/or modify
 *    it under the terms of the GNU General Public License as published by
 *    the Free Software Foundation; either version 2, or (at your option)
 *    any later version.
 *
 *    This program is distributed in the hope that it will be useful,
 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *    GNU General Public License for more details.
 *
 *    You should have received a copy of the GNU General Public License
 *    along with this program; if not, write to the Free Software
 *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */
#include <linux/bitops.h>
#include <linux/config.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/seq_file.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#include <asm/io.h>

#include <asm/smp.h>

#undef PARISC_IRQ_CR16_COUNTS

extern irqreturn_t timer_interrupt(int, void *, struct pt_regs *);
extern irqreturn_t ipi_interrupt(int, void *, struct pt_regs *);

#define EIEM_MASK(irq)       (1UL<<(CPU_IRQ_MAX - irq))

/* Bits in EIEM correlate with cpu_irq_action[].
** Numbered *Big Endian*! (ie bit 0 is MSB)
*/
static volatile unsigned long cpu_eiem = 0;

static void cpu_disable_irq(unsigned int irq)
{
	unsigned long eirr_bit = EIEM_MASK(irq);

	cpu_eiem &= ~eirr_bit;
	/* Do nothing on the other CPUs.  If they get this interrupt,
	 * The & cpu_eiem in the do_cpu_irq_mask() ensures they won't
	 * handle it, and the set_eiem() at the bottom will ensure it
	 * then gets disabled */
}

static void cpu_enable_irq(unsigned int irq)
{
	unsigned long eirr_bit = EIEM_MASK(irq);

	cpu_eiem |= eirr_bit;

	/* FIXME: while our interrupts aren't nested, we cannot reset
	 * the eiem mask if we're already in an interrupt.  Once we
	 * implement nested interrupts, this can go away
	 */
	if (!in_interrupt())
		set_eiem(cpu_eiem);

	/* This is just a simple NOP IPI.  But what it does is cause
	 * all the other CPUs to do a set_eiem(cpu_eiem) at the end
	 * of the interrupt handler */
	smp_send_all_nop();
}

static unsigned int cpu_startup_irq(unsigned int irq)
{
	cpu_enable_irq(irq);
	return 0;
}

void no_ack_irq(unsigned int irq) { }
void no_end_irq(unsigned int irq) { }

#ifdef CONFIG_SMP
int cpu_check_affinity(unsigned int irq, cpumask_t *dest)
{
	int cpu_dest;

	/* timer and ipi have to always be received on all CPUs */
	if (irq == TIMER_IRQ || irq == IPI_IRQ) {
		/* Bad linux design decision.  The mask has already
		 * been set; we must reset it */
		irq_affinity[irq] = CPU_MASK_ALL;
		return -EINVAL;
	}

	/* whatever mask they set, we just allow one CPU */
	cpu_dest = first_cpu(*dest);
	*dest = cpumask_of_cpu(cpu_dest);

	return 0;
}

static void cpu_set_affinity_irq(unsigned int irq, cpumask_t dest)
{
	if (cpu_check_affinity(irq, &dest))
		return;

	irq_affinity[irq] = dest;
}
#endif

static struct hw_interrupt_type cpu_interrupt_type = {
	.typename	= "CPU",
	.startup	= cpu_startup_irq,
	.shutdown	= cpu_disable_irq,
	.enable		= cpu_enable_irq,
	.disable	= cpu_disable_irq,
	.ack		= no_ack_irq,
	.end		= no_end_irq,
#ifdef CONFIG_SMP
	.set_affinity	= cpu_set_affinity_irq,
#endif
};

int show_interrupts(struct seq_file *p, void *v)
{
	int i = *(loff_t *) v, j;
	unsigned long flags;

	if (i == 0) {
		seq_puts(p, "    ");
		for_each_online_cpu(j)
			seq_printf(p, "       CPU%d", j);

#ifdef PARISC_IRQ_CR16_COUNTS
		seq_printf(p, " [min/avg/max] (CPU cycle counts)");
#endif
		seq_putc(p, '\n');
	}

	if (i < NR_IRQS) {
		struct irqaction *action;

		spin_lock_irqsave(&irq_desc[i].lock, flags);
		action = irq_desc[i].action;
		if (!action)
			goto skip;
		seq_printf(p, "%3d: ", i);
#ifdef CONFIG_SMP
		for_each_online_cpu(j)
			seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
#else
		seq_printf(p, "%10u ", kstat_irqs(i));
#endif

		seq_printf(p, " %14s", irq_desc[i].handler->typename);
#ifndef PARISC_IRQ_CR16_COUNTS
		seq_printf(p, "  %s", action->name);

		while ((action = action->next))
			seq_printf(p, ", %s", action->name);
#else
		for ( ;action; action = action->next) {
			unsigned int k, avg, min, max;

			min = max = action->cr16_hist[0];

			for (avg = k = 0; k < PARISC_CR16_HIST_SIZE; k++) {
				int hist = action->cr16_hist[k];

				if (hist) {
					avg += hist;
				} else
					break;

				if (hist > max) max = hist;
				if (hist < min) min = hist;
			}

			avg /= k;
			seq_printf(p, " %s[%d/%d/%d]", action->name,
					min,avg,max);
		}
#endif

		seq_putc(p, '\n');
 skip:
		spin_unlock_irqrestore(&irq_desc[i].lock, flags);
	}

	return 0;
}


/*
** The following form a "set": Virtual IRQ, Transaction Address, Trans Data.
** Respectively, these map to IRQ region+EIRR, Processor HPA, EIRR bit.
**
** To use txn_XXX() interfaces, get a Virtual IRQ first.
** Then use that to get the Transaction address and data.
*/

int cpu_claim_irq(unsigned int irq, struct hw_interrupt_type *type, void *data)
{
	if (irq_desc[irq].action)
		return -EBUSY;
	if (irq_desc[irq].handler != &cpu_interrupt_type)
		return -EBUSY;

	if (type) {
		irq_desc[irq].handler = type;
		irq_desc[irq].handler_data = data;
		cpu_interrupt_type.enable(irq);
	}
	return 0;
}

int txn_claim_irq(int irq)
{
	return cpu_claim_irq(irq, NULL, NULL) ? -1 : irq;
}

/*
 * The bits_wide parameter accommodates the limitations of the HW/SW which
 * use these bits:
 * Legacy PA I/O (GSC/NIO): 5 bits (architected EIM register)
 * V-class (EPIC):          6 bits
 * N/L/A-class (iosapic):   8 bits
 * PCI 2.2 MSI:            16 bits
 * Some PCI devices:       32 bits (Symbios SCSI/ATM/HyperFabric)
 *
 * On the service provider side:
 * o PA 1.1 (and PA2.0 narrow mode)     5-bits (width of EIR register)
 * o PA 2.0 wide mode                   6-bits (per processor)
 * o IA64                               8-bits (0-256 total)
 *
 * So a Legacy PA I/O device on a PA 2.0 box can't use all the bits supported
 * by the processor...and the N/L-class I/O subsystem supports more bits than
 * PA2.0 has. The first case is the problem.
 */
int txn_alloc_irq(unsigned int bits_wide)
{
	int irq;

	/* never return irq 0 cause that's the interval timer */
	for (irq = CPU_IRQ_BASE + 1; irq <= CPU_IRQ_MAX; irq++) {
		if (cpu_claim_irq(irq, NULL, NULL) < 0)
			continue;
		if ((irq - CPU_IRQ_BASE) >= (1 << bits_wide))
			continue;
		return irq;
	}

	/* unlikely, but be prepared */
	return -1;
}


unsigned long txn_affinity_addr(unsigned int irq, int cpu)
{
#ifdef CONFIG_SMP
	irq_affinity[irq] = cpumask_of_cpu(cpu);
#endif

	return cpu_data[cpu].txn_addr;
}


unsigned long txn_alloc_addr(unsigned int virt_irq)
{
	static int next_cpu = -1;

	next_cpu++; /* assign to "next" CPU we want this bugger on */

	/* validate entry */
	while ((next_cpu < NR_CPUS) && (!cpu_data[next_cpu].txn_addr || 
		!cpu_online(next_cpu)))
		next_cpu++;

	if (next_cpu >= NR_CPUS) 
		next_cpu = 0;	/* nothing else, assign monarch */

	return txn_affinity_addr(virt_irq, next_cpu);
}


unsigned int txn_alloc_data(unsigned int virt_irq)
{
	return virt_irq - CPU_IRQ_BASE;
}

/* ONLY called from entry.S:intr_extint() */
void do_cpu_irq_mask(struct pt_regs *regs)
{
	unsigned long eirr_val;

	irq_enter();

	/*
	 * Don't allow TIMER or IPI nested interrupts.
	 * Allowing any single interrupt to nest can lead to that CPU
	 * handling interrupts with all enabled interrupts unmasked.
	 */
	set_eiem(0UL);

	/* 1) only process IRQs that are enabled/unmasked (cpu_eiem)
	 * 2) We loop here on EIRR contents in order to avoid
	 *    nested interrupts or having to take another interrupt
	 *    when we could have just handled it right away.
	 */
	for (;;) {
		unsigned long bit = (1UL << (BITS_PER_LONG - 1));
		unsigned int irq;
		eirr_val = mfctl(23) & cpu_eiem;
		if (!eirr_val)
			break;

		mtctl(eirr_val, 23); /* reset bits we are going to process */

		/* Work our way from MSb to LSb...same order we alloc EIRs */
		for (irq = TIMER_IRQ; eirr_val && bit; bit>>=1, irq++) {
#ifdef CONFIG_SMP
			cpumask_t dest = irq_affinity[irq];
#endif
			if (!(bit & eirr_val))
				continue;

			/* clear bit in mask - can exit loop sooner */
			eirr_val &= ~bit;

#ifdef CONFIG_SMP
			/* FIXME: because generic set affinity mucks
			 * with the affinity before sending it to us
			 * we can get the situation where the affinity is
			 * wrong for our CPU type interrupts */
			if (irq != TIMER_IRQ && irq != IPI_IRQ &&
			    !cpu_isset(smp_processor_id(), dest)) {
				int cpu = first_cpu(dest);

				printk(KERN_DEBUG "redirecting irq %d from CPU %d to %d\n",
				       irq, smp_processor_id(), cpu);
				gsc_writel(irq + CPU_IRQ_BASE,
					   cpu_data[cpu].hpa);
				continue;
			}
#endif

			__do_IRQ(irq, regs);
		}
	}

	set_eiem(cpu_eiem);	/* restore original mask */
	irq_exit();
}


static struct irqaction timer_action = {
	.handler = timer_interrupt,
	.name = "timer",
	.flags = SA_INTERRUPT,
};

#ifdef CONFIG_SMP
static struct irqaction ipi_action = {
	.handler = ipi_interrupt,
	.name = "IPI",
	.flags = SA_INTERRUPT,
};
#endif

static void claim_cpu_irqs(void)
{
	int i;
	for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) {
		irq_desc[i].handler = &cpu_interrupt_type;
	}

	irq_desc[TIMER_IRQ].action = &timer_action;
	irq_desc[TIMER_IRQ].status |= IRQ_PER_CPU;
#ifdef CONFIG_SMP
	irq_desc[IPI_IRQ].action = &ipi_action;
	irq_desc[IPI_IRQ].status = IRQ_PER_CPU;
#endif
}

void __init init_IRQ(void)
{
	local_irq_disable();	/* PARANOID - should already be disabled */
	mtctl(~0UL, 23);	/* EIRR : clear all pending external intr */
	claim_cpu_irqs();
#ifdef CONFIG_SMP
	if (!cpu_eiem)
		cpu_eiem = EIEM_MASK(IPI_IRQ) | EIEM_MASK(TIMER_IRQ);
#else
	cpu_eiem = EIEM_MASK(TIMER_IRQ);
#endif
        set_eiem(cpu_eiem);	/* EIEM : enable all external intr */

}

void hw_resend_irq(struct hw_interrupt_type *type, unsigned int irq)
{
	/* XXX: Needs to be written.  We managed without it so far, but
	 * we really ought to write it.
	 */
}

void ack_bad_irq(unsigned int irq)
{
	printk("unexpected IRQ %d\n", irq);
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Code to handle x86 style IRQs plus some generic interrupt stuff.
	3	*
	4	* Copyright (C) 1992 Linus Torvalds
	5	* Copyright (C) 1994, 1995, 1996, 1997, 1998 Ralf Baechle
	6	* Copyright (C) 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org)
	7	* Copyright (C) 1999-2000 Grant Grundler
	8	* Copyright (c) 2005 Matthew Wilcox
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; either version 2, or (at your option)
	13	* any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	23	*/
	24	#include <linux/bitops.h>
	25	#include <linux/config.h>
	26	#include <linux/errno.h>
	27	#include <linux/init.h>
	28	#include <linux/interrupt.h>
	29	#include <linux/kernel_stat.h>
	30	#include <linux/seq_file.h>
	31	#include <linux/spinlock.h>
	32	#include <linux/types.h>
c2ab64d0	33	#include <asm/io.h>
1da177e4	34
1d4c452a KM	35	#include <asm/smp.h>
1d4c452a KM	36
1da177e4 LT	37	#undef PARISC_IRQ_CR16_COUNTS
	38
	39	extern irqreturn_t timer_interrupt(int, void , struct pt_regs );
	40	extern irqreturn_t ipi_interrupt(int, void , struct pt_regs );
	41
	42	#define EIEM_MASK(irq) (1UL<<(CPU_IRQ_MAX - irq))
	43
	44	/* Bits in EIEM correlate with cpu_irq_action[].
	45	** Numbered Big Endian! (ie bit 0 is MSB)
	46	*/
	47	static volatile unsigned long cpu_eiem = 0;
	48
d911aed8	49	static void cpu_disable_irq(unsigned int irq)
1da177e4 LT	50	{
	51	unsigned long eirr_bit = EIEM_MASK(irq);
	52
	53	cpu_eiem &= ~eirr_bit;
d911aed8 JB	54	/* Do nothing on the other CPUs. If they get this interrupt,
	55	* The & cpu_eiem in the do_cpu_irq_mask() ensures they won't
	56	* handle it, and the set_eiem() at the bottom will ensure it
	57	* then gets disabled */
1da177e4 LT	58	}
	59
	60	static void cpu_enable_irq(unsigned int irq)
	61	{
	62	unsigned long eirr_bit = EIEM_MASK(irq);
	63
1da177e4	64	cpu_eiem \|= eirr_bit;
d911aed8 JB	65
	66	/* FIXME: while our interrupts aren't nested, we cannot reset
	67	* the eiem mask if we're already in an interrupt. Once we
	68	* implement nested interrupts, this can go away
	69	*/
	70	if (!in_interrupt())
	71	set_eiem(cpu_eiem);
	72
	73	/* This is just a simple NOP IPI. But what it does is cause
	74	* all the other CPUs to do a set_eiem(cpu_eiem) at the end
	75	* of the interrupt handler */
	76	smp_send_all_nop();
1da177e4 LT	77	}
	78
	79	static unsigned int cpu_startup_irq(unsigned int irq)
	80	{
	81	cpu_enable_irq(irq);
	82	return 0;
	83	}
	84
	85	void no_ack_irq(unsigned int irq) { }
	86	void no_end_irq(unsigned int irq) { }
	87
c2ab64d0 JB	88	#ifdef CONFIG_SMP
	89	int cpu_check_affinity(unsigned int irq, cpumask_t *dest)
	90	{
	91	int cpu_dest;
	92
	93	/* timer and ipi have to always be received on all CPUs */
	94	if (irq == TIMER_IRQ \|\| irq == IPI_IRQ) {
	95	/* Bad linux design decision. The mask has already
	96	* been set; we must reset it */
	97	irq_affinity[irq] = CPU_MASK_ALL;
	98	return -EINVAL;
	99	}
	100
	101	/* whatever mask they set, we just allow one CPU */
	102	cpu_dest = first_cpu(*dest);
	103	*dest = cpumask_of_cpu(cpu_dest);
	104
	105	return 0;
	106	}
	107
	108	static void cpu_set_affinity_irq(unsigned int irq, cpumask_t dest)
	109	{
	110	if (cpu_check_affinity(irq, &dest))
	111	return;
	112
	113	irq_affinity[irq] = dest;
	114	}
	115	#endif
	116
1da177e4 LT	117	static struct hw_interrupt_type cpu_interrupt_type = {
	118	.typename = "CPU",
	119	.startup = cpu_startup_irq,
	120	.shutdown = cpu_disable_irq,
	121	.enable = cpu_enable_irq,
	122	.disable = cpu_disable_irq,
	123	.ack = no_ack_irq,
	124	.end = no_end_irq,
c2ab64d0 JB	125	#ifdef CONFIG_SMP
	126	.set_affinity = cpu_set_affinity_irq,
	127	#endif
1da177e4 LT	128	};
	129
	130	int show_interrupts(struct seq_file p, void v)
	131	{
	132	int i = (loff_t ) v, j;
	133	unsigned long flags;
	134
	135	if (i == 0) {
	136	seq_puts(p, " ");
	137	for_each_online_cpu(j)
	138	seq_printf(p, " CPU%d", j);
	139
	140	#ifdef PARISC_IRQ_CR16_COUNTS
	141	seq_printf(p, " [min/avg/max] (CPU cycle counts)");
	142	#endif
	143	seq_putc(p, '\n');
	144	}
	145
	146	if (i < NR_IRQS) {
	147	struct irqaction *action;
	148
	149	spin_lock_irqsave(&irq_desc[i].lock, flags);
	150	action = irq_desc[i].action;
	151	if (!action)
	152	goto skip;
	153	seq_printf(p, "%3d: ", i);
	154	#ifdef CONFIG_SMP
	155	for_each_online_cpu(j)
	156	seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
	157	#else
	158	seq_printf(p, "%10u ", kstat_irqs(i));
	159	#endif
	160
	161	seq_printf(p, " %14s", irq_desc[i].handler->typename);
	162	#ifndef PARISC_IRQ_CR16_COUNTS
	163	seq_printf(p, " %s", action->name);
	164
	165	while ((action = action->next))
	166	seq_printf(p, ", %s", action->name);
	167	#else
	168	for ( ;action; action = action->next) {
	169	unsigned int k, avg, min, max;
	170
	171	min = max = action->cr16_hist[0];
	172
	173	for (avg = k = 0; k < PARISC_CR16_HIST_SIZE; k++) {
	174	int hist = action->cr16_hist[k];
	175
	176	if (hist) {
	177	avg += hist;
	178	} else
	179	break;
	180
	181	if (hist > max) max = hist;
	182	if (hist < min) min = hist;
	183	}
	184
	185	avg /= k;
	186	seq_printf(p, " %s[%d/%d/%d]", action->name,
	187	min,avg,max);
	188	}
	189	#endif
	190
	191	seq_putc(p, '\n');
192	skip:
193	spin_unlock_irqrestore(&irq_desc[i].lock, flags);
194	}
195
196	return 0;
197	}
198
199
200
201	/*
202	** The following form a "set": Virtual IRQ, Transaction Address, Trans Data.
203	** Respectively, these map to IRQ region+EIRR, Processor HPA, EIRR bit.
204	**
205	** To use txn_XXX() interfaces, get a Virtual IRQ first.
206	** Then use that to get the Transaction address and data.
207	*/
208
209	int cpu_claim_irq(unsigned int irq, struct hw_interrupt_type type, void data)
210	{
211	if (irq_desc[irq].action)
212	return -EBUSY;
213	if (irq_desc[irq].handler != &cpu_interrupt_type)
214	return -EBUSY;
215
216	if (type) {
217	irq_desc[irq].handler = type;
218	irq_desc[irq].handler_data = data;
219	cpu_interrupt_type.enable(irq);
220	}
221	return 0;
222	}
223
224	int txn_claim_irq(int irq)
225	{
226	return cpu_claim_irq(irq, NULL, NULL) ? -1 : irq;
227	}
228
229	/*
230	* The bits_wide parameter accommodates the limitations of the HW/SW which
231	* use these bits:
232	* Legacy PA I/O (GSC/NIO): 5 bits (architected EIM register)
233	* V-class (EPIC): 6 bits
234	* N/L/A-class (iosapic): 8 bits
235	* PCI 2.2 MSI: 16 bits
236	* Some PCI devices: 32 bits (Symbios SCSI/ATM/HyperFabric)
237	*
238	* On the service provider side:
239	* o PA 1.1 (and PA2.0 narrow mode) 5-bits (width of EIR register)
240	* o PA 2.0 wide mode 6-bits (per processor)
241	* o IA64 8-bits (0-256 total)
242	*
243	* So a Legacy PA I/O device on a PA 2.0 box can't use all the bits supported
244	* by the processor...and the N/L-class I/O subsystem supports more bits than
245	* PA2.0 has. The first case is the problem.
246	*/
247	int txn_alloc_irq(unsigned int bits_wide)
248	{
249	int irq;
250
251	/* never return irq 0 cause that's the interval timer */
252	for (irq = CPU_IRQ_BASE + 1; irq <= CPU_IRQ_MAX; irq++) {
253	if (cpu_claim_irq(irq, NULL, NULL) < 0)
254	continue;
255	if ((irq - CPU_IRQ_BASE) >= (1 << bits_wide))
256	continue;
257	return irq;
258	}
259
260	/* unlikely, but be prepared */
261	return -1;
262	}
263
03afe22f	264
c2ab64d0 JB	265	unsigned long txn_affinity_addr(unsigned int irq, int cpu)
c2ab64d0 JB	266	{
03afe22f	267	#ifdef CONFIG_SMP
c2ab64d0	268	irq_affinity[irq] = cpumask_of_cpu(cpu);
03afe22f	269	#endif
c2ab64d0 JB	270
	271	return cpu_data[cpu].txn_addr;
	272	}
	273
03afe22f	274
1da177e4 LT	275	unsigned long txn_alloc_addr(unsigned int virt_irq)
	276	{
	277	static int next_cpu = -1;
	278
	279	next_cpu++; /* assign to "next" CPU we want this bugger on */
	280
	281	/* validate entry */
	282	while ((next_cpu < NR_CPUS) && (!cpu_data[next_cpu].txn_addr \|\|
	283	!cpu_online(next_cpu)))
	284	next_cpu++;
	285
	286	if (next_cpu >= NR_CPUS)
	287	next_cpu = 0; /* nothing else, assign monarch */
	288
c2ab64d0	289	return txn_affinity_addr(virt_irq, next_cpu);
1da177e4 LT	290	}
	291
	292
	293	unsigned int txn_alloc_data(unsigned int virt_irq)
	294	{
	295	return virt_irq - CPU_IRQ_BASE;
	296	}
	297
	298	/* ONLY called from entry.S:intr_extint() */
	299	void do_cpu_irq_mask(struct pt_regs *regs)
	300	{
	301	unsigned long eirr_val;
	302
	303	irq_enter();
	304
	305	/*
3f902886 GG	306	* Don't allow TIMER or IPI nested interrupts.
	307	* Allowing any single interrupt to nest can lead to that CPU
	308	* handling interrupts with all enabled interrupts unmasked.
1da177e4	309	*/
3f902886	310	set_eiem(0UL);
1da177e4 LT	311
	312	/* 1) only process IRQs that are enabled/unmasked (cpu_eiem)
	313	* 2) We loop here on EIRR contents in order to avoid
	314	* nested interrupts or having to take another interrupt
	315	* when we could have just handled it right away.
	316	*/
	317	for (;;) {
	318	unsigned long bit = (1UL << (BITS_PER_LONG - 1));
	319	unsigned int irq;
	320	eirr_val = mfctl(23) & cpu_eiem;
	321	if (!eirr_val)
	322	break;
	323
1da177e4 LT	324	mtctl(eirr_val, 23); /* reset bits we are going to process */
	325
	326	/* Work our way from MSb to LSb...same order we alloc EIRs */
	327	for (irq = TIMER_IRQ; eirr_val && bit; bit>>=1, irq++) {
03afe22f	328	#ifdef CONFIG_SMP
c2ab64d0	329	cpumask_t dest = irq_affinity[irq];
03afe22f	330	#endif
1da177e4 LT	331	if (!(bit & eirr_val))
	332	continue;
	333
	334	/* clear bit in mask - can exit loop sooner */
	335	eirr_val &= ~bit;
	336
03afe22f	337	#ifdef CONFIG_SMP
c2ab64d0 JB	338	/* FIXME: because generic set affinity mucks
	339	* with the affinity before sending it to us
	340	* we can get the situation where the affinity is
	341	* wrong for our CPU type interrupts */
	342	if (irq != TIMER_IRQ && irq != IPI_IRQ &&
	343	!cpu_isset(smp_processor_id(), dest)) {
	344	int cpu = first_cpu(dest);
	345
75be99a8	346	printk(KERN_DEBUG "redirecting irq %d from CPU %d to %d\n",
c2ab64d0 JB	347	irq, smp_processor_id(), cpu);
	348	gsc_writel(irq + CPU_IRQ_BASE,
	349	cpu_data[cpu].hpa);
	350	continue;
	351	}
03afe22f	352	#endif
c2ab64d0	353
1da177e4 LT	354	__do_IRQ(irq, regs);
	355	}
	356	}
3f902886 GG	357
3f902886 GG	358	set_eiem(cpu_eiem); /* restore original mask */
1da177e4 LT	359	irq_exit();
	360	}
	361
	362
	363	static struct irqaction timer_action = {
	364	.handler = timer_interrupt,
	365	.name = "timer",
9a8b4584	366	.flags = SA_INTERRUPT,
1da177e4 LT	367	};
	368
	369	#ifdef CONFIG_SMP
	370	static struct irqaction ipi_action = {
	371	.handler = ipi_interrupt,
	372	.name = "IPI",
9a8b4584	373	.flags = SA_INTERRUPT,
1da177e4 LT	374	};
	375	#endif
	376
	377	static void claim_cpu_irqs(void)
	378	{
	379	int i;
	380	for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) {
	381	irq_desc[i].handler = &cpu_interrupt_type;
	382	}
	383
	384	irq_desc[TIMER_IRQ].action = &timer_action;
	385	irq_desc[TIMER_IRQ].status \|= IRQ_PER_CPU;
	386	#ifdef CONFIG_SMP
	387	irq_desc[IPI_IRQ].action = &ipi_action;
	388	irq_desc[IPI_IRQ].status = IRQ_PER_CPU;
	389	#endif
	390	}
	391
	392	void __init init_IRQ(void)
	393	{
	394	local_irq_disable(); /* PARANOID - should already be disabled */
	395	mtctl(~0UL, 23); /* EIRR : clear all pending external intr */
	396	claim_cpu_irqs();
	397	#ifdef CONFIG_SMP
	398	if (!cpu_eiem)
	399	cpu_eiem = EIEM_MASK(IPI_IRQ) \| EIEM_MASK(TIMER_IRQ);
	400	#else
	401	cpu_eiem = EIEM_MASK(TIMER_IRQ);
	402	#endif
	403	set_eiem(cpu_eiem); /* EIEM : enable all external intr */
	404
	405	}
	406
	407	void hw_resend_irq(struct hw_interrupt_type *type, unsigned int irq)
	408	{
	409	/* XXX: Needs to be written. We managed without it so far, but
	410	* we really ought to write it.
	411	*/
	412	}
	413
	414	void ack_bad_irq(unsigned int irq)
	415	{
	416	printk("unexpected IRQ %d\n", irq);
	417	}