[deliverable/linux.git] / arch / parisc / kernel / smp.c

/*
** SMP Support
**
** Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
** Copyright (C) 1999 David Mosberger-Tang <davidm@hpl.hp.com>
** Copyright (C) 2001,2004 Grant Grundler <grundler@parisc-linux.org>
** 
** Lots of stuff stolen from arch/alpha/kernel/smp.c
** ...and then parisc stole from arch/ia64/kernel/smp.c. Thanks David! :^)
**
** Thanks to John Curry and Ullas Ponnadi. I learned a lot from their work.
** -grant (1/12/2001)
**
**	This program is free software; you can redistribute it and/or modify
**	it under the terms of the GNU General Public License as published by
**      the Free Software Foundation; either version 2 of the License, or
**      (at your option) any later version.
*/
#include <linux/types.h>
#include <linux/spinlock.h>

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/smp.h>
#include <linux/kernel_stat.h>
#include <linux/mm.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/bitops.h>
#include <linux/ftrace.h>
#include <linux/cpu.h>

#include <linux/atomic.h>
#include <asm/current.h>
#include <asm/delay.h>
#include <asm/tlbflush.h>

#include <asm/io.h>
#include <asm/irq.h>		/* for CPU_IRQ_REGION and friends */
#include <asm/mmu_context.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/pgalloc.h>
#include <asm/processor.h>
#include <asm/ptrace.h>
#include <asm/unistd.h>
#include <asm/cacheflush.h>

#undef DEBUG_SMP
#ifdef DEBUG_SMP
static int smp_debug_lvl = 0;
#define smp_debug(lvl, printargs...)		\
		if (lvl >= smp_debug_lvl)	\
			printk(printargs);
#else
#define smp_debug(lvl, ...)	do { } while(0)
#endif /* DEBUG_SMP */

volatile struct task_struct *smp_init_current_idle_task;

/* track which CPU is booting */
static volatile int cpu_now_booting __cpuinitdata;

static int parisc_max_cpus __cpuinitdata = 1;

static DEFINE_PER_CPU(spinlock_t, ipi_lock);

enum ipi_message_type {
	IPI_NOP=0,
	IPI_RESCHEDULE=1,
	IPI_CALL_FUNC,
	IPI_CALL_FUNC_SINGLE,
	IPI_CPU_START,
	IPI_CPU_STOP,
	IPI_CPU_TEST
};


/********** SMP inter processor interrupt and communication routines */

#undef PER_CPU_IRQ_REGION
#ifdef PER_CPU_IRQ_REGION
/* XXX REVISIT Ignore for now.
**    *May* need this "hook" to register IPI handler
**    once we have perCPU ExtIntr switch tables.
*/
static void
ipi_init(int cpuid)
{
#error verify IRQ_OFFSET(IPI_IRQ) is ipi_interrupt() in new IRQ region

	if(cpu_online(cpuid) )
	{
		switch_to_idle_task(current);
	}

	return;
}
#endif


/*
** Yoink this CPU from the runnable list... 
**
*/
static void
halt_processor(void) 
{
	/* REVISIT : redirect I/O Interrupts to another CPU? */
	/* REVISIT : does PM *know* this CPU isn't available? */
	set_cpu_online(smp_processor_id(), false);
	local_irq_disable();
	for (;;)
		;
}


irqreturn_t __irq_entry
ipi_interrupt(int irq, void *dev_id) 
{
	int this_cpu = smp_processor_id();
	struct cpuinfo_parisc *p = &per_cpu(cpu_data, this_cpu);
	unsigned long ops;
	unsigned long flags;

	/* Count this now; we may make a call that never returns. */
	p->ipi_count++;

	mb();	/* Order interrupt and bit testing. */

	for (;;) {
		spinlock_t *lock = &per_cpu(ipi_lock, this_cpu);
		spin_lock_irqsave(lock, flags);
		ops = p->pending_ipi;
		p->pending_ipi = 0;
		spin_unlock_irqrestore(lock, flags);

		mb(); /* Order bit clearing and data access. */

		if (!ops)
		    break;

		while (ops) {
			unsigned long which = ffz(~ops);

			ops &= ~(1 << which);

			switch (which) {
			case IPI_NOP:
				smp_debug(100, KERN_DEBUG "CPU%d IPI_NOP\n", this_cpu);
				break;
				
			case IPI_RESCHEDULE:
				smp_debug(100, KERN_DEBUG "CPU%d IPI_RESCHEDULE\n", this_cpu);
				scheduler_ipi();
				break;

			case IPI_CALL_FUNC:
				smp_debug(100, KERN_DEBUG "CPU%d IPI_CALL_FUNC\n", this_cpu);
				generic_smp_call_function_interrupt();
				break;

			case IPI_CALL_FUNC_SINGLE:
				smp_debug(100, KERN_DEBUG "CPU%d IPI_CALL_FUNC_SINGLE\n", this_cpu);
				generic_smp_call_function_single_interrupt();
				break;

			case IPI_CPU_START:
				smp_debug(100, KERN_DEBUG "CPU%d IPI_CPU_START\n", this_cpu);
				break;

			case IPI_CPU_STOP:
				smp_debug(100, KERN_DEBUG "CPU%d IPI_CPU_STOP\n", this_cpu);
				halt_processor();
				break;

			case IPI_CPU_TEST:
				smp_debug(100, KERN_DEBUG "CPU%d is alive!\n", this_cpu);
				break;

			default:
				printk(KERN_CRIT "Unknown IPI num on CPU%d: %lu\n",
					this_cpu, which);
				return IRQ_NONE;
			} /* Switch */
		/* let in any pending interrupts */
		local_irq_enable();
		local_irq_disable();
		} /* while (ops) */
	}
	return IRQ_HANDLED;
}


static inline void
ipi_send(int cpu, enum ipi_message_type op)
{
	struct cpuinfo_parisc *p = &per_cpu(cpu_data, cpu);
	spinlock_t *lock = &per_cpu(ipi_lock, cpu);
	unsigned long flags;

	spin_lock_irqsave(lock, flags);
	p->pending_ipi |= 1 << op;
	gsc_writel(IPI_IRQ - CPU_IRQ_BASE, p->hpa);
	spin_unlock_irqrestore(lock, flags);
}

static void
send_IPI_mask(const struct cpumask *mask, enum ipi_message_type op)
{
	int cpu;

	for_each_cpu(cpu, mask)
		ipi_send(cpu, op);
}

static inline void
send_IPI_single(int dest_cpu, enum ipi_message_type op)
{
	BUG_ON(dest_cpu == NO_PROC_ID);

	ipi_send(dest_cpu, op);
}

static inline void
send_IPI_allbutself(enum ipi_message_type op)
{
	int i;
	
	for_each_online_cpu(i) {
		if (i != smp_processor_id())
			send_IPI_single(i, op);
	}
}


inline void 
smp_send_stop(void)	{ send_IPI_allbutself(IPI_CPU_STOP); }

static inline void
smp_send_start(void)	{ send_IPI_allbutself(IPI_CPU_START); }

void 
smp_send_reschedule(int cpu) { send_IPI_single(cpu, IPI_RESCHEDULE); }

void
smp_send_all_nop(void)
{
	send_IPI_allbutself(IPI_NOP);
}

void arch_send_call_function_ipi_mask(const struct cpumask *mask)
{
	send_IPI_mask(mask, IPI_CALL_FUNC);
}

void arch_send_call_function_single_ipi(int cpu)
{
	send_IPI_single(cpu, IPI_CALL_FUNC_SINGLE);
}

/*
 * Flush all other CPU's tlb and then mine.  Do this with on_each_cpu()
 * as we want to ensure all TLB's flushed before proceeding.
 */

void
smp_flush_tlb_all(void)
{
	on_each_cpu(flush_tlb_all_local, NULL, 1);
}

/*
 * Called by secondaries to update state and initialize CPU registers.
 */
static void __init
smp_cpu_init(int cpunum)
{
	extern int init_per_cpu(int);  /* arch/parisc/kernel/processor.c */
	extern void init_IRQ(void);    /* arch/parisc/kernel/irq.c */
	extern void start_cpu_itimer(void); /* arch/parisc/kernel/time.c */

	/* Set modes and Enable floating point coprocessor */
	(void) init_per_cpu(cpunum);

	disable_sr_hashing();

	mb();

	/* Well, support 2.4 linux scheme as well. */
	if (cpu_online(cpunum))	{
		extern void machine_halt(void); /* arch/parisc.../process.c */

		printk(KERN_CRIT "CPU#%d already initialized!\n", cpunum);
		machine_halt();
	}

	notify_cpu_starting(cpunum);

	set_cpu_online(cpunum, true);

	/* Initialise the idle task for this CPU */
	atomic_inc(&init_mm.mm_count);
	current->active_mm = &init_mm;
	BUG_ON(current->mm);
	enter_lazy_tlb(&init_mm, current);

	init_IRQ();   /* make sure no IRQs are enabled or pending */
	start_cpu_itimer();
}


/*
 * Slaves start using C here. Indirectly called from smp_slave_stext.
 * Do what start_kernel() and main() do for boot strap processor (aka monarch)
 */
void __init smp_callin(void)
{
	int slave_id = cpu_now_booting;

	smp_cpu_init(slave_id);
	preempt_disable();

	flush_cache_all_local(); /* start with known state */
	flush_tlb_all_local(NULL);

	local_irq_enable();  /* Interrupts have been off until now */

	cpu_idle();      /* Wait for timer to schedule some work */

	/* NOTREACHED */
	panic("smp_callin() AAAAaaaaahhhh....\n");
}

/*
 * Bring one cpu online.
 */
int __cpuinit smp_boot_one_cpu(int cpuid, struct task_struct *idle)
{
	const struct cpuinfo_parisc *p = &per_cpu(cpu_data, cpuid);
	long timeout;

	task_thread_info(idle)->cpu = cpuid;

	/* Let _start know what logical CPU we're booting
	** (offset into init_tasks[],cpu_data[])
	*/
	cpu_now_booting = cpuid;

	/* 
	** boot strap code needs to know the task address since
	** it also contains the process stack.
	*/
	smp_init_current_idle_task = idle ;
	mb();

	printk(KERN_INFO "Releasing cpu %d now, hpa=%lx\n", cpuid, p->hpa);

	/*
	** This gets PDC to release the CPU from a very tight loop.
	**
	** From the PA-RISC 2.0 Firmware Architecture Reference Specification:
	** "The MEM_RENDEZ vector specifies the location of OS_RENDEZ which 
	** is executed after receiving the rendezvous signal (an interrupt to 
	** EIR{0}). MEM_RENDEZ is valid only when it is nonzero and the 
	** contents of memory are valid."
	*/
	gsc_writel(TIMER_IRQ - CPU_IRQ_BASE, p->hpa);
	mb();

	/* 
	 * OK, wait a bit for that CPU to finish staggering about. 
	 * Slave will set a bit when it reaches smp_cpu_init().
	 * Once the "monarch CPU" sees the bit change, it can move on.
	 */
	for (timeout = 0; timeout < 10000; timeout++) {
		if(cpu_online(cpuid)) {
			/* Which implies Slave has started up */
			cpu_now_booting = 0;
			smp_init_current_idle_task = NULL;
			goto alive ;
		}
		udelay(100);
		barrier();
	}
	printk(KERN_CRIT "SMP: CPU:%d is stuck.\n", cpuid);
	return -1;

alive:
	/* Remember the Slave data */
	smp_debug(100, KERN_DEBUG "SMP: CPU:%d came alive after %ld _us\n",
		cpuid, timeout * 100);
	return 0;
}

void __init smp_prepare_boot_cpu(void)
{
	int bootstrap_processor = per_cpu(cpu_data, 0).cpuid;

	/* Setup BSP mappings */
	printk(KERN_INFO "SMP: bootstrap CPU ID is %d\n", bootstrap_processor);

	set_cpu_online(bootstrap_processor, true);
	set_cpu_present(bootstrap_processor, true);
}


/*
** inventory.c:do_inventory() hasn't yet been run and thus we
** don't 'discover' the additional CPUs until later.
*/
void __init smp_prepare_cpus(unsigned int max_cpus)
{
	int cpu;

	for_each_possible_cpu(cpu)
		spin_lock_init(&per_cpu(ipi_lock, cpu));

	init_cpu_present(cpumask_of(0));

	parisc_max_cpus = max_cpus;
	if (!max_cpus)
		printk(KERN_INFO "SMP mode deactivated.\n");
}


void smp_cpus_done(unsigned int cpu_max)
{
	return;
}


int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *tidle)
{
	if (cpu != 0 && cpu < parisc_max_cpus)
		smp_boot_one_cpu(cpu, tidle);

	return cpu_online(cpu) ? 0 : -ENOSYS;
}

#ifdef CONFIG_PROC_FS
int __init
setup_profiling_timer(unsigned int multiplier)
{
	return -EINVAL;
}
#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	** SMP Support
	3	**
	4	** Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
	5	** Copyright (C) 1999 David Mosberger-Tang <davidm@hpl.hp.com>
	6	** Copyright (C) 2001,2004 Grant Grundler <grundler@parisc-linux.org>
	7	**
	8	** Lots of stuff stolen from arch/alpha/kernel/smp.c
	9	** ...and then parisc stole from arch/ia64/kernel/smp.c. Thanks David! :^)
	10	**
7022672e	11	** Thanks to John Curry and Ullas Ponnadi. I learned a lot from their work.
1da177e4 LT	12	** -grant (1/12/2001)
	13	**
	14	** This program is free software; you can redistribute it and/or modify
	15	** it under the terms of the GNU General Public License as published by
	16	** the Free Software Foundation; either version 2 of the License, or
	17	** (at your option) any later version.
	18	*/
1da177e4 LT	19	#include <linux/types.h>
1da177e4 LT	20	#include <linux/spinlock.h>
1da177e4 LT	21
	22	#include <linux/kernel.h>
	23	#include <linux/module.h>
	24	#include <linux/sched.h>
	25	#include <linux/init.h>
	26	#include <linux/interrupt.h>
	27	#include <linux/smp.h>
	28	#include <linux/kernel_stat.h>
	29	#include <linux/mm.h>
4e950f6f	30	#include <linux/err.h>
1da177e4 LT	31	#include <linux/delay.h>
1da177e4 LT	32	#include <linux/bitops.h>
d75f054a	33	#include <linux/ftrace.h>
ec2e0f98	34	#include <linux/cpu.h>
1da177e4	35
60063497	36	#include <linux/atomic.h>
1da177e4 LT	37	#include <asm/current.h>
1da177e4 LT	38	#include <asm/delay.h>
1b2425e3	39	#include <asm/tlbflush.h>
1da177e4 LT	40
	41	#include <asm/io.h>
	42	#include <asm/irq.h> /* for CPU_IRQ_REGION and friends */
	43	#include <asm/mmu_context.h>
	44	#include <asm/page.h>
	45	#include <asm/pgtable.h>
	46	#include <asm/pgalloc.h>
	47	#include <asm/processor.h>
	48	#include <asm/ptrace.h>
	49	#include <asm/unistd.h>
	50	#include <asm/cacheflush.h>
	51
5492a0f0 KM	52	#undef DEBUG_SMP
	53	#ifdef DEBUG_SMP
	54	static int smp_debug_lvl = 0;
	55	#define smp_debug(lvl, printargs...) \
	56	if (lvl >= smp_debug_lvl) \
	57	printk(printargs);
	58	#else
ef017beb	59	#define smp_debug(lvl, ...) do { } while(0)
5492a0f0	60	#endif /* DEBUG_SMP */
1da177e4	61
1da177e4 LT	62	volatile struct task_struct *smp_init_current_idle_task;
1da177e4 LT	63
ef017beb HD	64	/* track which CPU is booting */
ef017beb HD	65	static volatile int cpu_now_booting __cpuinitdata;
1da177e4	66
ef017beb	67	static int parisc_max_cpus __cpuinitdata = 1;
1da177e4	68
6ad6c424	69	static DEFINE_PER_CPU(spinlock_t, ipi_lock);
1da177e4	70
1da177e4 LT	71	enum ipi_message_type {
	72	IPI_NOP=0,
	73	IPI_RESCHEDULE=1,
	74	IPI_CALL_FUNC,
dbcf4787	75	IPI_CALL_FUNC_SINGLE,
1da177e4 LT	76	IPI_CPU_START,
	77	IPI_CPU_STOP,
	78	IPI_CPU_TEST
	79	};
	80
	81
	82	/********** SMP inter processor interrupt and communication routines */
	83
	84	#undef PER_CPU_IRQ_REGION
	85	#ifdef PER_CPU_IRQ_REGION
	86	/* XXX REVISIT Ignore for now.
	87	** May need this "hook" to register IPI handler
	88	** once we have perCPU ExtIntr switch tables.
	89	*/
	90	static void
	91	ipi_init(int cpuid)
	92	{
1da177e4 LT	93	#error verify IRQ_OFFSET(IPI_IRQ) is ipi_interrupt() in new IRQ region
	94
	95	if(cpu_online(cpuid) )
	96	{
	97	switch_to_idle_task(current);
	98	}
	99
	100	return;
	101	}
	102	#endif
	103
	104
	105	/*
	106	** Yoink this CPU from the runnable list...
	107	**
	108	*/
	109	static void
	110	halt_processor(void)
	111	{
1da177e4 LT	112	/* REVISIT : redirect I/O Interrupts to another CPU? */
1da177e4 LT	113	/* REVISIT : does PM know this CPU isn't available? */
9bc181d8	114	set_cpu_online(smp_processor_id(), false);
1da177e4 LT	115	local_irq_disable();
	116	for (;;)
	117	;
1da177e4 LT	118	}
	119
	120
d75f054a	121	irqreturn_t __irq_entry
c7753f18	122	ipi_interrupt(int irq, void *dev_id)
1da177e4 LT	123	{
1da177e4 LT	124	int this_cpu = smp_processor_id();
ef017beb	125	struct cpuinfo_parisc *p = &per_cpu(cpu_data, this_cpu);
1da177e4 LT	126	unsigned long ops;
	127	unsigned long flags;
	128
	129	/* Count this now; we may make a call that never returns. */
	130	p->ipi_count++;
	131
	132	mb(); /* Order interrupt and bit testing. */
	133
	134	for (;;) {
3c97b5e9 KM	135	spinlock_t *lock = &per_cpu(ipi_lock, this_cpu);
3c97b5e9 KM	136	spin_lock_irqsave(lock, flags);
1da177e4 LT	137	ops = p->pending_ipi;
1da177e4 LT	138	p->pending_ipi = 0;
3c97b5e9	139	spin_unlock_irqrestore(lock, flags);
1da177e4 LT	140
	141	mb(); /* Order bit clearing and data access. */
	142
	143	if (!ops)
	144	break;
	145
	146	while (ops) {
	147	unsigned long which = ffz(~ops);
	148
d911aed8 JB	149	ops &= ~(1 << which);
d911aed8 JB	150
1da177e4	151	switch (which) {
d911aed8	152	case IPI_NOP:
5492a0f0	153	smp_debug(100, KERN_DEBUG "CPU%d IPI_NOP\n", this_cpu);
d911aed8 JB	154	break;
d911aed8 JB	155
1da177e4	156	case IPI_RESCHEDULE:
5492a0f0	157	smp_debug(100, KERN_DEBUG "CPU%d IPI_RESCHEDULE\n", this_cpu);
184748cc	158	scheduler_ipi();
1da177e4 LT	159	break;
	160
	161	case IPI_CALL_FUNC:
5492a0f0	162	smp_debug(100, KERN_DEBUG "CPU%d IPI_CALL_FUNC\n", this_cpu);
dbcf4787 JA	163	generic_smp_call_function_interrupt();
	164	break;
	165
	166	case IPI_CALL_FUNC_SINGLE:
	167	smp_debug(100, KERN_DEBUG "CPU%d IPI_CALL_FUNC_SINGLE\n", this_cpu);
	168	generic_smp_call_function_single_interrupt();
1da177e4 LT	169	break;
	170
	171	case IPI_CPU_START:
5492a0f0	172	smp_debug(100, KERN_DEBUG "CPU%d IPI_CPU_START\n", this_cpu);
1da177e4 LT	173	break;
	174
	175	case IPI_CPU_STOP:
5492a0f0	176	smp_debug(100, KERN_DEBUG "CPU%d IPI_CPU_STOP\n", this_cpu);
1da177e4	177	halt_processor();
1da177e4 LT	178	break;
	179
	180	case IPI_CPU_TEST:
5492a0f0	181	smp_debug(100, KERN_DEBUG "CPU%d is alive!\n", this_cpu);
1da177e4 LT	182	break;
	183
	184	default:
	185	printk(KERN_CRIT "Unknown IPI num on CPU%d: %lu\n",
	186	this_cpu, which);
1da177e4 LT	187	return IRQ_NONE;
1da177e4 LT	188	} /* Switch */
7085689e JB	189	/* let in any pending interrupts */
	190	local_irq_enable();
	191	local_irq_disable();
1da177e4 LT	192	} /* while (ops) */
	193	}
	194	return IRQ_HANDLED;
	195	}
	196
	197
	198	static inline void
	199	ipi_send(int cpu, enum ipi_message_type op)
	200	{
ef017beb	201	struct cpuinfo_parisc *p = &per_cpu(cpu_data, cpu);
3c97b5e9	202	spinlock_t *lock = &per_cpu(ipi_lock, cpu);
1da177e4 LT	203	unsigned long flags;
1da177e4 LT	204
3c97b5e9	205	spin_lock_irqsave(lock, flags);
1da177e4	206	p->pending_ipi \|= 1 << op;
ef017beb	207	gsc_writel(IPI_IRQ - CPU_IRQ_BASE, p->hpa);
3c97b5e9	208	spin_unlock_irqrestore(lock, flags);
1da177e4 LT	209	}
1da177e4 LT	210
dbcf4787	211	static void
91887a36	212	send_IPI_mask(const struct cpumask *mask, enum ipi_message_type op)
dbcf4787 JA	213	{
	214	int cpu;
	215
91887a36	216	for_each_cpu(cpu, mask)
dbcf4787 JA	217	ipi_send(cpu, op);
dbcf4787 JA	218	}
1da177e4 LT	219
	220	static inline void
	221	send_IPI_single(int dest_cpu, enum ipi_message_type op)
	222	{
7f2347a4	223	BUG_ON(dest_cpu == NO_PROC_ID);
1da177e4 LT	224
	225	ipi_send(dest_cpu, op);
	226	}
	227
	228	static inline void
	229	send_IPI_allbutself(enum ipi_message_type op)
	230	{
	231	int i;
	232
394e3902 AM	233	for_each_online_cpu(i) {
394e3902 AM	234	if (i != smp_processor_id())
1da177e4 LT	235	send_IPI_single(i, op);
	236	}
	237	}
	238
	239
	240	inline void
	241	smp_send_stop(void) { send_IPI_allbutself(IPI_CPU_STOP); }
	242
	243	static inline void
	244	smp_send_start(void) { send_IPI_allbutself(IPI_CPU_START); }
	245
	246	void
	247	smp_send_reschedule(int cpu) { send_IPI_single(cpu, IPI_RESCHEDULE); }
	248
d911aed8 JB	249	void
	250	smp_send_all_nop(void)
	251	{
	252	send_IPI_allbutself(IPI_NOP);
	253	}
	254
91887a36	255	void arch_send_call_function_ipi_mask(const struct cpumask *mask)
1da177e4	256	{
dbcf4787	257	send_IPI_mask(mask, IPI_CALL_FUNC);
1da177e4 LT	258	}
1da177e4 LT	259
dbcf4787 JA	260	void arch_send_call_function_single_ipi(int cpu)
	261	{
	262	send_IPI_single(cpu, IPI_CALL_FUNC_SINGLE);
	263	}
1da177e4 LT	264
	265	/*
	266	* Flush all other CPU's tlb and then mine. Do this with on_each_cpu()
	267	* as we want to ensure all TLB's flushed before proceeding.
	268	*/
	269
1da177e4 LT	270	void
	271	smp_flush_tlb_all(void)
	272	{
15c8b6c1	273	on_each_cpu(flush_tlb_all_local, NULL, 1);
1da177e4 LT	274	}
1da177e4 LT	275
1da177e4 LT	276	/*
	277	* Called by secondaries to update state and initialize CPU registers.
	278	*/
	279	static void __init
	280	smp_cpu_init(int cpunum)
	281	{
56f335c8	282	extern int init_per_cpu(int); /* arch/parisc/kernel/processor.c */
1da177e4	283	extern void init_IRQ(void); /* arch/parisc/kernel/irq.c */
56f335c8	284	extern void start_cpu_itimer(void); /* arch/parisc/kernel/time.c */
1da177e4 LT	285
	286	/* Set modes and Enable floating point coprocessor */
	287	(void) init_per_cpu(cpunum);
	288
	289	disable_sr_hashing();
	290
	291	mb();
	292
	293	/* Well, support 2.4 linux scheme as well. */
7ec6118c	294	if (cpu_online(cpunum)) {
1da177e4 LT	295	extern void machine_halt(void); /* arch/parisc.../process.c */
	296
	297	printk(KERN_CRIT "CPU#%d already initialized!\n", cpunum);
	298	machine_halt();
ec2e0f98 SB	299	}
	300
	301	notify_cpu_starting(cpunum);
	302
9bc181d8	303	set_cpu_online(cpunum, true);
1da177e4 LT	304
	305	/* Initialise the idle task for this CPU */
	306	atomic_inc(&init_mm.mm_count);
	307	current->active_mm = &init_mm;
7f2347a4	308	BUG_ON(current->mm);
1da177e4 LT	309	enter_lazy_tlb(&init_mm, current);
1da177e4 LT	310
7022672e	311	init_IRQ(); /* make sure no IRQs are enabled or pending */
56f335c8	312	start_cpu_itimer();
1da177e4 LT	313	}
	314
	315
	316	/*
	317	* Slaves start using C here. Indirectly called from smp_slave_stext.
	318	* Do what start_kernel() and main() do for boot strap processor (aka monarch)
	319	*/
	320	void __init smp_callin(void)
	321	{
	322	int slave_id = cpu_now_booting;
1da177e4 LT	323
1da177e4 LT	324	smp_cpu_init(slave_id);
5bfb5d69	325	preempt_disable();
1da177e4	326
1da177e4	327	flush_cache_all_local(); /* start with known state */
1b2425e3	328	flush_tlb_all_local(NULL);
1da177e4 LT	329
	330	local_irq_enable(); /* Interrupts have been off until now */
	331
	332	cpu_idle(); /* Wait for timer to schedule some work */
	333
	334	/* NOTREACHED */
	335	panic("smp_callin() AAAAaaaaahhhh....\n");
	336	}
	337
	338	/*
	339	* Bring one cpu online.
	340	*/
9a134723	341	int __cpuinit smp_boot_one_cpu(int cpuid, struct task_struct *idle)
1da177e4	342	{
ef017beb	343	const struct cpuinfo_parisc *p = &per_cpu(cpu_data, cpuid);
1da177e4 LT	344	long timeout;
1da177e4 LT	345
40f1f0de	346	task_thread_info(idle)->cpu = cpuid;
1da177e4 LT	347
	348	/* Let _start know what logical CPU we're booting
	349	** (offset into init_tasks[],cpu_data[])
	350	*/
	351	cpu_now_booting = cpuid;
	352
	353	/*
	354	** boot strap code needs to know the task address since
	355	** it also contains the process stack.
	356	*/
	357	smp_init_current_idle_task = idle ;
	358	mb();
	359
ef017beb	360	printk(KERN_INFO "Releasing cpu %d now, hpa=%lx\n", cpuid, p->hpa);
1da177e4 LT	361
	362	/*
	363	** This gets PDC to release the CPU from a very tight loop.
	364	**
	365	** From the PA-RISC 2.0 Firmware Architecture Reference Specification:
	366	** "The MEM_RENDEZ vector specifies the location of OS_RENDEZ which
	367	** is executed after receiving the rendezvous signal (an interrupt to
	368	** EIR{0}). MEM_RENDEZ is valid only when it is nonzero and the
	369	** contents of memory are valid."
	370	*/
ef017beb	371	gsc_writel(TIMER_IRQ - CPU_IRQ_BASE, p->hpa);
1da177e4 LT	372	mb();
	373
	374	/*
	375	* OK, wait a bit for that CPU to finish staggering about.
	376	* Slave will set a bit when it reaches smp_cpu_init().
	377	* Once the "monarch CPU" sees the bit change, it can move on.
	378	*/
	379	for (timeout = 0; timeout < 10000; timeout++) {
	380	if(cpu_online(cpuid)) {
	381	/* Which implies Slave has started up */
	382	cpu_now_booting = 0;
	383	smp_init_current_idle_task = NULL;
	384	goto alive ;
	385	}
	386	udelay(100);
	387	barrier();
	388	}
1da177e4 LT	389	printk(KERN_CRIT "SMP: CPU:%d is stuck.\n", cpuid);
	390	return -1;
	391
	392	alive:
	393	/* Remember the Slave data */
5492a0f0	394	smp_debug(100, KERN_DEBUG "SMP: CPU:%d came alive after %ld _us\n",
1da177e4	395	cpuid, timeout * 100);
1da177e4 LT	396	return 0;
	397	}
	398
ef017beb	399	void __init smp_prepare_boot_cpu(void)
1da177e4	400	{
ef017beb	401	int bootstrap_processor = per_cpu(cpu_data, 0).cpuid;
1da177e4	402
1da177e4	403	/* Setup BSP mappings */
ef017beb	404	printk(KERN_INFO "SMP: bootstrap CPU ID is %d\n", bootstrap_processor);
1da177e4	405
9bc181d8 RR	406	set_cpu_online(bootstrap_processor, true);
9bc181d8 RR	407	set_cpu_present(bootstrap_processor, true);
1da177e4 LT	408	}
	409
	410
	411
	412	/*
	413	** inventory.c:do_inventory() hasn't yet been run and thus we
7022672e	414	** don't 'discover' the additional CPUs until later.
1da177e4 LT	415	*/
	416	void __init smp_prepare_cpus(unsigned int max_cpus)
	417	{
6ad6c424 TG	418	int cpu;
	419
	420	for_each_possible_cpu(cpu)
	421	spin_lock_init(&per_cpu(ipi_lock, cpu));
	422
9bc181d8	423	init_cpu_present(cpumask_of(0));
1da177e4 LT	424
	425	parisc_max_cpus = max_cpus;
	426	if (!max_cpus)
	427	printk(KERN_INFO "SMP mode deactivated.\n");
	428	}
	429
	430
	431	void smp_cpus_done(unsigned int cpu_max)
	432	{
	433	return;
	434	}
	435
	436
8239c25f	437	int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *tidle)
1da177e4 LT	438	{
1da177e4 LT	439	if (cpu != 0 && cpu < parisc_max_cpus)
9a134723	440	smp_boot_one_cpu(cpu, tidle);
1da177e4 LT	441
	442	return cpu_online(cpu) ? 0 : -ENOSYS;
	443	}
	444
1da177e4 LT	445	#ifdef CONFIG_PROC_FS
	446	int __init
	447	setup_profiling_timer(unsigned int multiplier)
	448	{
	449	return -EINVAL;
	450	}
	451	#endif