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[PARISC] Whitespace clean up in asm/pgtable.h
[deliverable/linux.git] / arch / parisc / kernel / unaligned.c
CommitLineData
1da177e4
LT		 1/*
2 * Unaligned memory access handler
3 *
4 * Copyright (C) 2001 Randolph Chung <tausq@debian.org>
5 * Significantly tweaked by LaMont Jones <lamont@debian.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 *
21 */
22
23#include <linux/config.h>
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <asm/uaccess.h>
27
28/* #define DEBUG_UNALIGNED 1 */
29
30#ifdef DEBUG_UNALIGNED
31#define DPRINTF(fmt, args...) do { printk(KERN_DEBUG "%s:%d:%s ", __FILE__, __LINE__, __FUNCTION__ ); printk(KERN_DEBUG fmt, ##args ); } while (0)
32#else
33#define DPRINTF(fmt, args...)
34#endif
35
36#ifdef __LP64__
37#define RFMT "%016lx"
38#else
39#define RFMT "%08lx"
40#endif
41
42#define FIXUP_BRANCH(lbl) \
43 "\tldil L%%" #lbl ", %%r1\n" \
44 "\tldo R%%" #lbl "(%%r1), %%r1\n" \
45 "\tbv,n %%r0(%%r1)\n"
46
47/* 1111 1100 0000 0000 0001 0011 1100 0000 */
48#define OPCODE1(a,b,c) ((a)<<26|(b)<<12|(c)<<6)
49#define OPCODE2(a,b) ((a)<<26|(b)<<1)
50#define OPCODE3(a,b) ((a)<<26|(b)<<2)
51#define OPCODE4(a) ((a)<<26)
52#define OPCODE1_MASK OPCODE1(0x3f,1,0xf)
53#define OPCODE2_MASK OPCODE2(0x3f,1)
54#define OPCODE3_MASK OPCODE3(0x3f,1)
55#define OPCODE4_MASK OPCODE4(0x3f)
56
57/* skip LDB - never unaligned (index) */
58#define OPCODE_LDH_I OPCODE1(0x03,0,0x1)
59#define OPCODE_LDW_I OPCODE1(0x03,0,0x2)
60#define OPCODE_LDD_I OPCODE1(0x03,0,0x3)
61#define OPCODE_LDDA_I OPCODE1(0x03,0,0x4)
62#define OPCODE_LDCD_I OPCODE1(0x03,0,0x5)
63#define OPCODE_LDWA_I OPCODE1(0x03,0,0x6)
64#define OPCODE_LDCW_I OPCODE1(0x03,0,0x7)
65/* skip LDB - never unaligned (short) */
66#define OPCODE_LDH_S OPCODE1(0x03,1,0x1)
67#define OPCODE_LDW_S OPCODE1(0x03,1,0x2)
68#define OPCODE_LDD_S OPCODE1(0x03,1,0x3)
69#define OPCODE_LDDA_S OPCODE1(0x03,1,0x4)
70#define OPCODE_LDCD_S OPCODE1(0x03,1,0x5)
71#define OPCODE_LDWA_S OPCODE1(0x03,1,0x6)
72#define OPCODE_LDCW_S OPCODE1(0x03,1,0x7)
73/* skip STB - never unaligned */
74#define OPCODE_STH OPCODE1(0x03,1,0x9)
75#define OPCODE_STW OPCODE1(0x03,1,0xa)
76#define OPCODE_STD OPCODE1(0x03,1,0xb)
77/* skip STBY - never unaligned */
78/* skip STDBY - never unaligned */
79#define OPCODE_STWA OPCODE1(0x03,1,0xe)
80#define OPCODE_STDA OPCODE1(0x03,1,0xf)
81
82#define OPCODE_FLDWX OPCODE1(0x09,0,0x0)
83#define OPCODE_FLDWXR OPCODE1(0x09,0,0x1)
84#define OPCODE_FSTWX OPCODE1(0x09,0,0x8)
85#define OPCODE_FSTWXR OPCODE1(0x09,0,0x9)
86#define OPCODE_FLDWS OPCODE1(0x09,1,0x0)
87#define OPCODE_FLDWSR OPCODE1(0x09,1,0x1)
88#define OPCODE_FSTWS OPCODE1(0x09,1,0x8)
89#define OPCODE_FSTWSR OPCODE1(0x09,1,0x9)
90#define OPCODE_FLDDX OPCODE1(0x0b,0,0x0)
91#define OPCODE_FSTDX OPCODE1(0x0b,0,0x8)
92#define OPCODE_FLDDS OPCODE1(0x0b,1,0x0)
93#define OPCODE_FSTDS OPCODE1(0x0b,1,0x8)
94
95#define OPCODE_LDD_L OPCODE2(0x14,0)
96#define OPCODE_FLDD_L OPCODE2(0x14,1)
97#define OPCODE_STD_L OPCODE2(0x1c,0)
98#define OPCODE_FSTD_L OPCODE2(0x1c,1)
99
100#define OPCODE_LDW_M OPCODE3(0x17,1)
101#define OPCODE_FLDW_L OPCODE3(0x17,0)
102#define OPCODE_FSTW_L OPCODE3(0x1f,0)
103#define OPCODE_STW_M OPCODE3(0x1f,1)
104
105#define OPCODE_LDH_L OPCODE4(0x11)
106#define OPCODE_LDW_L OPCODE4(0x12)
107#define OPCODE_LDWM OPCODE4(0x13)
108#define OPCODE_STH_L OPCODE4(0x19)
109#define OPCODE_STW_L OPCODE4(0x1A)
110#define OPCODE_STWM OPCODE4(0x1B)
111
112#define MAJOR_OP(i) (((i)>>26)&0x3f)
113#define R1(i) (((i)>>21)&0x1f)
114#define R2(i) (((i)>>16)&0x1f)
115#define R3(i) ((i)&0x1f)
116#define FR3(i) ((((i)<<1)&0x1f)|(((i)>>6)&1))
117#define IM(i,n) (((i)>>1&((1<<(n-1))-1))|((i)&1?((0-1L)<<(n-1)):0))
118#define IM5_2(i) IM((i)>>16,5)
119#define IM5_3(i) IM((i),5)
120#define IM14(i) IM((i),14)
121
122#define ERR_NOTHANDLED -1
123#define ERR_PAGEFAULT -2
124
8039de10 125int unaligned_enabled __read_mostly = 1;
1da177e4
LT		 126
127void die_if_kernel (char *str, struct pt_regs *regs, long err);
128
129static int emulate_ldh(struct pt_regs *regs, int toreg)
130{
131 unsigned long saddr = regs->ior;
132 unsigned long val = 0;
133 int ret;
134
135 DPRINTF("load " RFMT ":" RFMT " to r%d for 2 bytes\n",
136 regs->isr, regs->ior, toreg);
137
138 __asm__ __volatile__ (
139" mtsp %4, %%sr1\n"
140"1: ldbs 0(%%sr1,%3), %%r20\n"
141"2: ldbs 1(%%sr1,%3), %0\n"
142" depw %%r20, 23, 24, %0\n"
143" copy %%r0, %1\n"
144"3: \n"
145" .section .fixup,\"ax\"\n"
146"4: ldi -2, %1\n"
147 FIXUP_BRANCH(3b)
148" .previous\n"
149" .section __ex_table,\"aw\"\n"
150#ifdef __LP64__
151" .dword 1b,4b\n"
152" .dword 2b,4b\n"
153#else
154" .word 1b,4b\n"
155" .word 2b,4b\n"
156#endif
157" .previous\n"
158 : "=r" (val), "=r" (ret)
159 : "0" (val), "r" (saddr), "r" (regs->isr)
160 : "r20" );
161
162 DPRINTF("val = 0x" RFMT "\n", val);
163
164 if (toreg)
165 regs->gr[toreg] = val;
166
167 return ret;
168}
169
170static int emulate_ldw(struct pt_regs *regs, int toreg, int flop)
171{
172 unsigned long saddr = regs->ior;
173 unsigned long val = 0;
174 int ret;
175
176 DPRINTF("load " RFMT ":" RFMT " to r%d for 4 bytes\n",
177 regs->isr, regs->ior, toreg);
178
179 __asm__ __volatile__ (
180" zdep %3,28,2,%%r19\n" /* r19=(ofs&3)*8 */
181" mtsp %4, %%sr1\n"
182" depw %%r0,31,2,%3\n"
183"1: ldw 0(%%sr1,%3),%0\n"
184"2: ldw 4(%%sr1,%3),%%r20\n"
185" subi 32,%%r19,%%r19\n"
186" mtctl %%r19,11\n"
187" vshd %0,%%r20,%0\n"
188" copy %%r0, %1\n"
189"3: \n"
190" .section .fixup,\"ax\"\n"
191"4: ldi -2, %1\n"
192 FIXUP_BRANCH(3b)
193" .previous\n"
194" .section __ex_table,\"aw\"\n"
195#ifdef __LP64__
196" .dword 1b,4b\n"
197" .dword 2b,4b\n"
198#else
199" .word 1b,4b\n"
200" .word 2b,4b\n"
201#endif
202" .previous\n"
203 : "=r" (val), "=r" (ret)
204 : "0" (val), "r" (saddr), "r" (regs->isr)
205 : "r19", "r20" );
206
207 DPRINTF("val = 0x" RFMT "\n", val);
208
209 if (flop)
210 ((__u32*)(regs->fr))[toreg] = val;
211 else if (toreg)
212 regs->gr[toreg] = val;
213
214 return ret;
215}
216static int emulate_ldd(struct pt_regs *regs, int toreg, int flop)
217{
218 unsigned long saddr = regs->ior;
219 __u64 val = 0;
220 int ret;
221
222 DPRINTF("load " RFMT ":" RFMT " to r%d for 8 bytes\n",
223 regs->isr, regs->ior, toreg);
224#ifdef CONFIG_PA20
225
226#ifndef __LP64__
227 if (!flop)
228 return -1;
229#endif
230 __asm__ __volatile__ (
231" depd,z %3,60,3,%%r19\n" /* r19=(ofs&7)*8 */
232" mtsp %4, %%sr1\n"
233" depd %%r0,63,3,%3\n"
234"1: ldd 0(%%sr1,%3),%0\n"
235"2: ldd 8(%%sr1,%3),%%r20\n"
236" subi 64,%%r19,%%r19\n"
237" mtsar %%r19\n"
238" shrpd %0,%%r20,%%sar,%0\n"
239" copy %%r0, %1\n"
240"3: \n"
241" .section .fixup,\"ax\"\n"
242"4: ldi -2, %1\n"
243 FIXUP_BRANCH(3b)
244" .previous\n"
245" .section __ex_table,\"aw\"\n"
246#ifdef __LP64__
247" .dword 1b,4b\n"
248" .dword 2b,4b\n"
249#else
250" .word 1b,4b\n"
251" .word 2b,4b\n"
252#endif
253" .previous\n"
254 : "=r" (val), "=r" (ret)
255 : "0" (val), "r" (saddr), "r" (regs->isr)
256 : "r19", "r20" );
257#else
258 {
259 unsigned long valh=0,vall=0;
260 __asm__ __volatile__ (
261" zdep %5,29,2,%%r19\n" /* r19=(ofs&3)*8 */
262" mtsp %6, %%sr1\n"
263" dep %%r0,31,2,%5\n"
264"1: ldw 0(%%sr1,%5),%0\n"
265"2: ldw 4(%%sr1,%5),%1\n"
266"3: ldw 8(%%sr1,%5),%%r20\n"
267" subi 32,%%r19,%%r19\n"
268" mtsar %%r19\n"
269" vshd %0,%1,%0\n"
270" vshd %1,%%r20,%1\n"
271" copy %%r0, %2\n"
272"4: \n"
273" .section .fixup,\"ax\"\n"
274"5: ldi -2, %2\n"
275 FIXUP_BRANCH(4b)
276" .previous\n"
277" .section __ex_table,\"aw\"\n"
278#ifdef __LP64__
279" .dword 1b,5b\n"
280" .dword 2b,5b\n"
281" .dword 3b,5b\n"
282#else
283" .word 1b,5b\n"
284" .word 2b,5b\n"
285" .word 3b,5b\n"
286#endif
287" .previous\n"
288 : "=r" (valh), "=r" (vall), "=r" (ret)
289 : "0" (valh), "1" (vall), "r" (saddr), "r" (regs->isr)
290 : "r19", "r20" );
291 val=((__u64)valh<<32)|(__u64)vall;
292 }
293#endif
294
295 DPRINTF("val = 0x%llx\n", val);
296
297 if (flop)
298 regs->fr[toreg] = val;
299 else if (toreg)
300 regs->gr[toreg] = val;
301
302 return ret;
303}
304
305static int emulate_sth(struct pt_regs *regs, int frreg)
306{
307 unsigned long val = regs->gr[frreg];
308 int ret;
309
310 if (!frreg)
311 val = 0;
312
313 DPRINTF("store r%d (0x" RFMT ") to " RFMT ":" RFMT " for 2 bytes\n", frreg,
314 val, regs->isr, regs->ior);
315
316 __asm__ __volatile__ (
317" mtsp %3, %%sr1\n"
318" extrw,u %1, 23, 8, %%r19\n"
319"1: stb %1, 1(%%sr1, %2)\n"
320"2: stb %%r19, 0(%%sr1, %2)\n"
321" copy %%r0, %0\n"
322"3: \n"
323" .section .fixup,\"ax\"\n"
324"4: ldi -2, %0\n"
325 FIXUP_BRANCH(3b)
326" .previous\n"
327" .section __ex_table,\"aw\"\n"
328#ifdef __LP64__
329" .dword 1b,4b\n"
330" .dword 2b,4b\n"
331#else
332" .word 1b,4b\n"
333" .word 2b,4b\n"
334#endif
335" .previous\n"
336 : "=r" (ret)
337 : "r" (val), "r" (regs->ior), "r" (regs->isr)
338 : "r19" );
339
340 return ret;
341}
342
343static int emulate_stw(struct pt_regs *regs, int frreg, int flop)
344{
345 unsigned long val;
346 int ret;
347
348 if (flop)
349 val = ((__u32*)(regs->fr))[frreg];
350 else if (frreg)
351 val = regs->gr[frreg];
352 else
353 val = 0;
354
355 DPRINTF("store r%d (0x" RFMT ") to " RFMT ":" RFMT " for 4 bytes\n", frreg,
356 val, regs->isr, regs->ior);
357
358
359 __asm__ __volatile__ (
360" mtsp %3, %%sr1\n"
361" zdep %2, 28, 2, %%r19\n"
362" dep %%r0, 31, 2, %2\n"
363" mtsar %%r19\n"
364" depwi,z -2, %%sar, 32, %%r19\n"
365"1: ldw 0(%%sr1,%2),%%r20\n"
366"2: ldw 4(%%sr1,%2),%%r21\n"
367" vshd %%r0, %1, %%r22\n"
368" vshd %1, %%r0, %%r1\n"
369" and %%r20, %%r19, %%r20\n"
370" andcm %%r21, %%r19, %%r21\n"
371" or %%r22, %%r20, %%r20\n"
372" or %%r1, %%r21, %%r21\n"
373" stw %%r20,0(%%sr1,%2)\n"
374" stw %%r21,4(%%sr1,%2)\n"
375" copy %%r0, %0\n"
376"3: \n"
377" .section .fixup,\"ax\"\n"
378"4: ldi -2, %0\n"
379 FIXUP_BRANCH(3b)
380" .previous\n"
381" .section __ex_table,\"aw\"\n"
382#ifdef __LP64__
383" .dword 1b,4b\n"
384" .dword 2b,4b\n"
385#else
386" .word 1b,4b\n"
387" .word 2b,4b\n"
388#endif
389" .previous\n"
390 : "=r" (ret)
391 : "r" (val), "r" (regs->ior), "r" (regs->isr)
392 : "r19", "r20", "r21", "r22", "r1" );
393
394 return 0;
395}
396static int emulate_std(struct pt_regs *regs, int frreg, int flop)
397{
398 __u64 val;
399 int ret;
400
401 if (flop)
402 val = regs->fr[frreg];
403 else if (frreg)
404 val = regs->gr[frreg];
405 else
406 val = 0;
407
408 DPRINTF("store r%d (0x%016llx) to " RFMT ":" RFMT " for 8 bytes\n", frreg,
409 val, regs->isr, regs->ior);
410
411#ifdef CONFIG_PA20
412#ifndef __LP64__
413 if (!flop)
414 return -1;
415#endif
416 __asm__ __volatile__ (
417" mtsp %3, %%sr1\n"
418" depd,z %2, 60, 3, %%r19\n"
419" depd %%r0, 63, 3, %2\n"
420" mtsar %%r19\n"
421" depdi,z -2, %%sar, 64, %%r19\n"
422"1: ldd 0(%%sr1,%2),%%r20\n"
423"2: ldd 8(%%sr1,%2),%%r21\n"
424" shrpd %%r0, %1, %%sar, %%r22\n"
425" shrpd %1, %%r0, %%sar, %%r1\n"
426" and %%r20, %%r19, %%r20\n"
427" andcm %%r21, %%r19, %%r21\n"
428" or %%r22, %%r20, %%r20\n"
429" or %%r1, %%r21, %%r21\n"
430"3: std %%r20,0(%%sr1,%2)\n"
431"4: std %%r21,8(%%sr1,%2)\n"
432" copy %%r0, %0\n"
433"5: \n"
434" .section .fixup,\"ax\"\n"
435"6: ldi -2, %0\n"
436 FIXUP_BRANCH(5b)
437" .previous\n"
438" .section __ex_table,\"aw\"\n"
439#ifdef __LP64__
440" .dword 1b,6b\n"
441" .dword 2b,6b\n"
442" .dword 3b,6b\n"
443" .dword 4b,6b\n"
444#else
445" .word 1b,6b\n"
446" .word 2b,6b\n"
447" .word 3b,6b\n"
448" .word 4b,6b\n"
449#endif
450" .previous\n"
451 : "=r" (ret)
452 : "r" (val), "r" (regs->ior), "r" (regs->isr)
453 : "r19", "r20", "r21", "r22", "r1" );
454#else
455 {
456 unsigned long valh=(val>>32),vall=(val&0xffffffffl);
457 __asm__ __volatile__ (
458" mtsp %4, %%sr1\n"
459" zdep %2, 29, 2, %%r19\n"
460" dep %%r0, 31, 2, %2\n"
461" mtsar %%r19\n"
462" zvdepi -2, 32, %%r19\n"
463"1: ldw 0(%%sr1,%3),%%r20\n"
464"2: ldw 8(%%sr1,%3),%%r21\n"
465" vshd %1, %2, %%r1\n"
466" vshd %%r0, %1, %1\n"
467" vshd %2, %%r0, %2\n"
468" and %%r20, %%r19, %%r20\n"
469" andcm %%r21, %%r19, %%r21\n"
470" or %1, %%r20, %1\n"
471" or %2, %%r21, %2\n"
472"3: stw %1,0(%%sr1,%1)\n"
473"4: stw %%r1,4(%%sr1,%3)\n"
474"5: stw %2,8(%%sr1,%3)\n"
475" copy %%r0, %0\n"
476"6: \n"
477" .section .fixup,\"ax\"\n"
478"7: ldi -2, %0\n"
479 FIXUP_BRANCH(6b)
480" .previous\n"
481" .section __ex_table,\"aw\"\n"
482#ifdef __LP64__
483" .dword 1b,7b\n"
484" .dword 2b,7b\n"
485" .dword 3b,7b\n"
486" .dword 4b,7b\n"
487" .dword 5b,7b\n"
488#else
489" .word 1b,7b\n"
490" .word 2b,7b\n"
491" .word 3b,7b\n"
492" .word 4b,7b\n"
493" .word 5b,7b\n"
494#endif
495" .previous\n"
496 : "=r" (ret)
497 : "r" (valh), "r" (vall), "r" (regs->ior), "r" (regs->isr)
498 : "r19", "r20", "r21", "r1" );
499 }
500#endif
501
502 return ret;
503}
504
505void handle_unaligned(struct pt_regs *regs)
506{
507 static unsigned long unaligned_count = 0;
508 static unsigned long last_time = 0;
509 unsigned long newbase = R1(regs->iir)?regs->gr[R1(regs->iir)]:0;
510 int modify = 0;
511 int ret = ERR_NOTHANDLED;
512 struct siginfo si;
513 register int flop=0; /* true if this is a flop */
514
515 /* log a message with pacing */
f053725b
KM		 516 if (user_mode(regs)) {
517 if (current->thread.flags & PARISC_UAC_SIGBUS) {
518 goto force_sigbus;
519 }
520
521 if (unaligned_count > 5 && jiffies - last_time > 5*HZ) {
1da177e4
LT		 522 unaligned_count = 0;
523 last_time = jiffies;
524 }
f053725b
KM		 525
526 if (!(current->thread.flags & PARISC_UAC_NOPRINT)
527 && ++unaligned_count < 5) {
1da177e4
LT		 528 char buf[256];
529 sprintf(buf, "%s(%d): unaligned access to 0x" RFMT " at ip=0x" RFMT "\n",
530 current->comm, current->pid, regs->ior, regs->iaoq[0]);
531 printk(KERN_WARNING "%s", buf);
532#ifdef DEBUG_UNALIGNED
533 show_regs(regs);
534#endif
535 }
f053725b 536
1da177e4
LT		 537 if (!unaligned_enabled)
538 goto force_sigbus;
539 }
540
541 /* handle modification - OK, it's ugly, see the instruction manual */
542 switch (MAJOR_OP(regs->iir))
543 {
544 case 0x03:
545 case 0x09:
546 case 0x0b:
547 if (regs->iir&0x20)
548 {
549 modify = 1;
550 if (regs->iir&0x1000) /* short loads */
551 if (regs->iir&0x200)
552 newbase += IM5_3(regs->iir);
553 else
554 newbase += IM5_2(regs->iir);
555 else if (regs->iir&0x2000) /* scaled indexed */
556 {
557 int shift=0;
558 switch (regs->iir & OPCODE1_MASK)
559 {
560 case OPCODE_LDH_I:
561 shift= 1; break;
562 case OPCODE_LDW_I:
563 shift= 2; break;
564 case OPCODE_LDD_I:
565 case OPCODE_LDDA_I:
566 shift= 3; break;
567 }
568 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0)<<shift;
569 } else /* simple indexed */
570 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0);
571 }
572 break;
573 case 0x13:
574 case 0x1b:
575 modify = 1;
576 newbase += IM14(regs->iir);
577 break;
578 case 0x14:
579 case 0x1c:
580 if (regs->iir&8)
581 {
582 modify = 1;
583 newbase += IM14(regs->iir&~0xe);
584 }
585 break;
586 case 0x16:
587 case 0x1e:
588 modify = 1;
589 newbase += IM14(regs->iir&6);
590 break;
591 case 0x17:
592 case 0x1f:
593 if (regs->iir&4)
594 {
595 modify = 1;
596 newbase += IM14(regs->iir&~4);
597 }
598 break;
599 }
600
601 /* TODO: make this cleaner... */
602 switch (regs->iir & OPCODE1_MASK)
603 {
604 case OPCODE_LDH_I:
605 case OPCODE_LDH_S:
606 ret = emulate_ldh(regs, R3(regs->iir));
607 break;
608
609 case OPCODE_LDW_I:
610 case OPCODE_LDWA_I:
611 case OPCODE_LDW_S:
612 case OPCODE_LDWA_S:
613 ret = emulate_ldw(regs, R3(regs->iir),0);
614 break;
615
616 case OPCODE_STH:
617 ret = emulate_sth(regs, R2(regs->iir));
618 break;
619
620 case OPCODE_STW:
621 case OPCODE_STWA:
622 ret = emulate_stw(regs, R2(regs->iir),0);
623 break;
624
625#ifdef CONFIG_PA20
626 case OPCODE_LDD_I:
627 case OPCODE_LDDA_I:
628 case OPCODE_LDD_S:
629 case OPCODE_LDDA_S:
630 ret = emulate_ldd(regs, R3(regs->iir),0);
631 break;
632
633 case OPCODE_STD:
634 case OPCODE_STDA:
635 ret = emulate_std(regs, R2(regs->iir),0);
636 break;
637#endif
638
639 case OPCODE_FLDWX:
640 case OPCODE_FLDWS:
641 case OPCODE_FLDWXR:
642 case OPCODE_FLDWSR:
643 flop=1;
644 ret = emulate_ldw(regs,FR3(regs->iir),1);
645 break;
646
647 case OPCODE_FLDDX:
648 case OPCODE_FLDDS:
649 flop=1;
650 ret = emulate_ldd(regs,R3(regs->iir),1);
651 break;
652
653 case OPCODE_FSTWX:
654 case OPCODE_FSTWS:
655 case OPCODE_FSTWXR:
656 case OPCODE_FSTWSR:
657 flop=1;
658 ret = emulate_stw(regs,FR3(regs->iir),1);
659 break;
660
661 case OPCODE_FSTDX:
662 case OPCODE_FSTDS:
663 flop=1;
664 ret = emulate_std(regs,R3(regs->iir),1);
665 break;
666
667 case OPCODE_LDCD_I:
668 case OPCODE_LDCW_I:
669 case OPCODE_LDCD_S:
670 case OPCODE_LDCW_S:
671 ret = ERR_NOTHANDLED; /* "undefined", but lets kill them. */
672 break;
673 }
674#ifdef CONFIG_PA20
675 switch (regs->iir & OPCODE2_MASK)
676 {
677 case OPCODE_FLDD_L:
678 flop=1;
679 ret = emulate_ldd(regs,R2(regs->iir),1);
680 break;
681 case OPCODE_FSTD_L:
682 flop=1;
683 ret = emulate_std(regs, R2(regs->iir),1);
684 break;
685
686#ifdef CONFIG_PA20
687 case OPCODE_LDD_L:
688 ret = emulate_ldd(regs, R2(regs->iir),0);
689 break;
690 case OPCODE_STD_L:
691 ret = emulate_std(regs, R2(regs->iir),0);
692 break;
693#endif
694 }
695#endif
696 switch (regs->iir & OPCODE3_MASK)
697 {
698 case OPCODE_FLDW_L:
699 flop=1;
700 ret = emulate_ldw(regs, R2(regs->iir),0);
701 break;
702 case OPCODE_LDW_M:
703 ret = emulate_ldw(regs, R2(regs->iir),1);
704 break;
705
706 case OPCODE_FSTW_L:
707 flop=1;
708 ret = emulate_stw(regs, R2(regs->iir),1);
709 break;
710 case OPCODE_STW_M:
711 ret = emulate_stw(regs, R2(regs->iir),0);
712 break;
713 }
714 switch (regs->iir & OPCODE4_MASK)
715 {
716 case OPCODE_LDH_L:
717 ret = emulate_ldh(regs, R2(regs->iir));
718 break;
719 case OPCODE_LDW_L:
720 case OPCODE_LDWM:
721 ret = emulate_ldw(regs, R2(regs->iir),0);
722 break;
723 case OPCODE_STH_L:
724 ret = emulate_sth(regs, R2(regs->iir));
725 break;
726 case OPCODE_STW_L:
727 case OPCODE_STWM:
728 ret = emulate_stw(regs, R2(regs->iir),0);
729 break;
730 }
731
732 if (modify && R1(regs->iir))
733 regs->gr[R1(regs->iir)] = newbase;
734
735
736 if (ret == ERR_NOTHANDLED)
737 printk(KERN_CRIT "Not-handled unaligned insn 0x%08lx\n", regs->iir);
738
739 DPRINTF("ret = %d\n", ret);
740
741 if (ret)
742 {
743 printk(KERN_CRIT "Unaligned handler failed, ret = %d\n", ret);
744 die_if_kernel("Unaligned data reference", regs, 28);
745
746 if (ret == ERR_PAGEFAULT)
747 {
748 si.si_signo = SIGSEGV;
749 si.si_errno = 0;
750 si.si_code = SEGV_MAPERR;
751 si.si_addr = (void __user *)regs->ior;
752 force_sig_info(SIGSEGV, &si, current);
753 }
754 else
755 {
756force_sigbus:
757 /* couldn't handle it ... */
758 si.si_signo = SIGBUS;
759 si.si_errno = 0;
760 si.si_code = BUS_ADRALN;
761 si.si_addr = (void __user *)regs->ior;
762 force_sig_info(SIGBUS, &si, current);
763 }
764
765 return;
766 }
767
768 /* else we handled it, let life go on. */
769 regs->gr[0]|=PSW_N;
770}
771
772/*
773 * NB: check_unaligned() is only used for PCXS processors right
774 * now, so we only check for PA1.1 encodings at this point.
775 */
776
777int
778check_unaligned(struct pt_regs *regs)
779{
780 unsigned long align_mask;
781
782 /* Get alignment mask */
783
784 align_mask = 0UL;
785 switch (regs->iir & OPCODE1_MASK) {
786
787 case OPCODE_LDH_I:
788 case OPCODE_LDH_S:
789 case OPCODE_STH:
790 align_mask = 1UL;
791 break;
792
793 case OPCODE_LDW_I:
794 case OPCODE_LDWA_I:
795 case OPCODE_LDW_S:
796 case OPCODE_LDWA_S:
797 case OPCODE_STW:
798 case OPCODE_STWA:
799 align_mask = 3UL;
800 break;
801
802 default:
803 switch (regs->iir & OPCODE4_MASK) {
804 case OPCODE_LDH_L:
805 case OPCODE_STH_L:
806 align_mask = 1UL;
807 break;
808 case OPCODE_LDW_L:
809 case OPCODE_LDWM:
810 case OPCODE_STW_L:
811 case OPCODE_STWM:
812 align_mask = 3UL;
813 break;
814 }
815 break;
816 }
817
818 return (int)(regs->ior & align_mask);
819}
820
Linux kernel - Deliverables
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