[deliverable/linux.git] / arch / powerpc / boot / dts / c2k.dts

/* Device Tree Source for GEFanuc C2K
 *
 * Author: Remi Machet <rmachet@slac.stanford.edu>
 *
 * Originated from prpmc2800.dts
 *
 * 2008 (c) Stanford University
 * 2007 (c) MontaVista, Software, Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation.
 */

/dts-v1/;

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	model = "C2K";
	compatible = "GEFanuc,C2K";
	coherency-off;

	aliases {
		pci0 = &PCI0;
		pci1 = &PCI1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "PowerPC,7447";
			reg = <0>;
			clock-frequency = <996000000>;	/* 996 MHz */
			bus-frequency = <166666667>;	/* 166.6666 MHz */
			timebase-frequency = <41666667>;	/* 166.6666/4 MHz */
			i-cache-line-size = <32>;
			d-cache-line-size = <32>;
			i-cache-size = <32768>;
			d-cache-size = <32768>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x40000000>;	/* 1GB */
	};

	system-controller@d8000000 { /* Marvell Discovery */
		#address-cells = <1>;
		#size-cells = <1>;
		model = "mv64460";
		compatible = "marvell,mv64360";
		clock-frequency = <166666667>;		/* 166.66... MHz */
		reg = <0xd8000000 0x00010000>;
		virtual-reg = <0xd8000000>;
		ranges = <0xd4000000 0xd4000000 0x01000000	/* PCI 0 I/O Space */
			  0x80000000 0x80000000 0x08000000	/* PCI 0 MEM Space */
			  0xd0000000 0xd0000000 0x01000000	/* PCI 1 I/O Space */
			  0xa0000000 0xa0000000 0x08000000	/* PCI 1 MEM Space */
			  0xd8100000 0xd8100000 0x00010000	/* FPGA */
			  0xd8110000 0xd8110000 0x00010000	/* FPGA USARTs */
			  0xf8000000 0xf8000000 0x08000000	/* User FLASH */
			  0x00000000 0xd8000000 0x00010000	/* Bridge's regs */
			  0xd8140000 0xd8140000 0x00040000>;	/* Integrated SRAM */

		mdio@2000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "marvell,mv64360-mdio";
			reg = <0x2000 4>;
			PHY0: ethernet-phy@0 {
				interrupts = <76>;	/* GPP 12 */
				interrupt-parent = <&PIC>;
				reg = <0>;
			};
			PHY1: ethernet-phy@1 {
				interrupts = <76>;	/* GPP 12 */
				interrupt-parent = <&PIC>;
				reg = <1>;
			};
			PHY2: ethernet-phy@2 {
				interrupts = <76>;	/* GPP 12 */
				interrupt-parent = <&PIC>;
				reg = <2>;
			};
		};

		ethernet-group@2000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "marvell,mv64360-eth-group";
			reg = <0x2000 0x2000>;
			ethernet@0 {
				device_type = "network";
				compatible = "marvell,mv64360-eth";
				reg = <0>;
				interrupts = <32>;
				interrupt-parent = <&PIC>;
				phy = <&PHY0>;
				local-mac-address = [ 00 00 00 00 00 00 ];
			};
			ethernet@1 {
				device_type = "network";
				compatible = "marvell,mv64360-eth";
				reg = <1>;
				interrupts = <33>;
				interrupt-parent = <&PIC>;
				phy = <&PHY1>;
				local-mac-address = [ 00 00 00 00 00 00 ];
			};
			ethernet@2 {
				device_type = "network";
				compatible = "marvell,mv64360-eth";
				reg = <2>;
				interrupts = <34>;
				interrupt-parent = <&PIC>;
				phy = <&PHY2>;
				local-mac-address = [ 00 00 00 00 00 00 ];
			};
		};

		SDMA0: sdma@4000 {
			compatible = "marvell,mv64360-sdma";
			reg = <0x4000 0xc18>;
			virtual-reg = <0xd8004000>;
			interrupt-base = <0>;
			interrupts = <36>;
			interrupt-parent = <&PIC>;
		};

		SDMA1: sdma@6000 {
			compatible = "marvell,mv64360-sdma";
			reg = <0x6000 0xc18>;
			virtual-reg = <0xd8006000>;
			interrupt-base = <0>;
			interrupts = <38>;
			interrupt-parent = <&PIC>;
		};

		BRG0: brg@b200 {
			compatible = "marvell,mv64360-brg";
			reg = <0xb200 0x8>;
			clock-src = <8>;
			clock-frequency = <133333333>;
			current-speed = <115200>;
		};

		BRG1: brg@b208 {
			compatible = "marvell,mv64360-brg";
			reg = <0xb208 0x8>;
			clock-src = <8>;
			clock-frequency = <133333333>;
			current-speed = <115200>;
		};

		CUNIT: cunit@f200 {
			reg = <0xf200 0x200>;
		};

		MPSCROUTING: mpscrouting@b400 {
			reg = <0xb400 0xc>;
		};

		MPSCINTR: mpscintr@b800 {
			reg = <0xb800 0x100>;
			virtual-reg = <0xd800b800>;
		};

		MPSC0: mpsc@8000 {
			device_type = "serial";
			compatible = "marvell,mv64360-mpsc";
			reg = <0x8000 0x38>;
			virtual-reg = <0xd8008000>;
			sdma = <&SDMA0>;
			brg = <&BRG0>;
			cunit = <&CUNIT>;
			mpscrouting = <&MPSCROUTING>;
			mpscintr = <&MPSCINTR>;
			cell-index = <0>;
			interrupts = <40>;
			interrupt-parent = <&PIC>;
		};

		MPSC1: mpsc@9000 {
			device_type = "serial";
			compatible = "marvell,mv64360-mpsc";
			reg = <0x9000 0x38>;
			virtual-reg = <0xd8009000>;
			sdma = <&SDMA1>;
			brg = <&BRG1>;
			cunit = <&CUNIT>;
			mpscrouting = <&MPSCROUTING>;
			mpscintr = <&MPSCINTR>;
			cell-index = <1>;
			interrupts = <42>;
			interrupt-parent = <&PIC>;
		};

		wdt@b410 {			/* watchdog timer */
			compatible = "marvell,mv64360-wdt";
			reg = <0xb410 0x8>;
		};

		i2c@c000 {
			compatible = "marvell,mv64360-i2c";
			reg = <0xc000 0x20>;
			virtual-reg = <0xd800c000>;
			interrupts = <37>;
			interrupt-parent = <&PIC>;
		};

		PIC: pic {
			#interrupt-cells = <1>;
			#address-cells = <0>;
			compatible = "marvell,mv64360-pic";
			reg = <0x0000 0x88>;
			interrupt-controller;
		};

		mpp@f000 {
			compatible = "marvell,mv64360-mpp";
			reg = <0xf000 0x10>;
		};

		gpp@f100 {
			compatible = "marvell,mv64360-gpp";
			reg = <0xf100 0x20>;
		};

		PCI0: pci@80000000 {
			#address-cells = <3>;
			#size-cells = <2>;
			#interrupt-cells = <1>;
			device_type = "pci";
			compatible = "marvell,mv64360-pci";
			reg = <0x0cf8 0x8>;
			ranges = <0x01000000 0x0 0x00000000 0xd4000000 0x0 0x01000000
				  0x02000000 0x0 0x80000000 0x80000000 0x0 0x08000000>;
			bus-range = <0 255>;
			clock-frequency = <66000000>;
			interrupt-pci-iack = <0x0c34>;
			interrupt-parent = <&PIC>;
			interrupt-map-mask = <0x0000 0x0 0x0 0x7>;
			interrupt-map = <
				/* Only one interrupt line for PMC0 slot (INTA) */
				0x0000 0 0 1 &PIC 88
			>;
		};


		PCI1: pci@a0000000 {
			#address-cells = <3>;
			#size-cells = <2>;
			#interrupt-cells = <1>;
			device_type = "pci";
			compatible = "marvell,mv64360-pci";
			reg = <0x0c78 0x8>;
			ranges = <0x01000000 0x0 0x00000000 0xd0000000 0x0 0x01000000
				  0x02000000 0x0 0x80000000 0xa0000000 0x0 0x08000000>;
			bus-range = <0 255>;
			clock-frequency = <66000000>;
			interrupt-pci-iack = <0x0cb4>;
			interrupt-parent = <&PIC>;
			interrupt-map-mask = <0xf800 0x00 0x00 0x7>;
			interrupt-map = <
				/* IDSEL 0x01: PMC1 ? */
				0x0800 0 0 1 &PIC 88
				/* IDSEL 0x02: cPCI bridge */
				0x1000 0 0 1 &PIC 88
				/* IDSEL 0x03: USB controller */
				0x1800 0 0 1 &PIC 91
				/* IDSEL 0x04: SATA controller */
				0x2000 0 0 1 &PIC 95
			>;
		};

		cpu-error@0070 {
			compatible = "marvell,mv64360-cpu-error";
			reg = <0x0070 0x10 0x0128 0x28>;
			interrupts = <3>;
			interrupt-parent = <&PIC>;
		};

		sram-ctrl@0380 {
			compatible = "marvell,mv64360-sram-ctrl";
			reg = <0x0380 0x80>;
			interrupts = <13>;
			interrupt-parent = <&PIC>;
		};

		pci-error@1d40 {
			compatible = "marvell,mv64360-pci-error";
			reg = <0x1d40 0x40 0x0c28 0x4>;
			interrupts = <12>;
			interrupt-parent = <&PIC>;
		};

		pci-error@1dc0 {
			compatible = "marvell,mv64360-pci-error";
			reg = <0x1dc0 0x40 0x0ca8 0x4>;
			interrupts = <16>;
			interrupt-parent = <&PIC>;
		};

		mem-ctrl@1400 {
			compatible = "marvell,mv64360-mem-ctrl";
			reg = <0x1400 0x60>;
			interrupts = <17>;
			interrupt-parent = <&PIC>;
		};
		/* Devices attached to the device controller */
		devicebus@045c {
			#address-cells = <2>;
			#size-cells = <1>;
			compatible = "marvell,mv64306-devctrl";
			reg = <0x45C 0x88>;
			interrupts = <1>;
			interrupt-parent = <&PIC>;
			ranges = 	<0 0 0xd8100000 0x10000
					 2 0 0xd8110000 0x10000
					 4 0 0xf8000000 0x8000000>;
			fpga@0,0 {
				compatible = "sbs,fpga-c2k";
				reg = <0 0 0x10000>;
			};
			fpga_usart@2,0 {
				compatible = "sbs,fpga_usart-c2k";
				reg = <2 0 0x10000>;
			};
			nor_flash@4,0 {
				compatible = "cfi-flash";
				reg = <4 0 0x8000000>; /* 128MB */
				bank-width = <4>;
				device-width = <1>;
				#address-cells = <1>;
				#size-cells = <1>;
				partition@0 {
					label = "boot";
					reg = <0x00000000 0x00080000>;
				};
				partition@40000 {
					label = "kernel";
					reg = <0x00080000 0x00400000>;
				};
				partition@440000 {
					label = "initrd";
					reg = <0x00480000 0x00B80000>;
				};
				partition@1000000 {
					label = "rootfs";
					reg = <0x01000000 0x06800000>;
				};
				partition@7800000 {
					label = "recovery";
					reg = <0x07800000 0x00800000>;
					read-only;
				};
			};
		};
	};
	chosen {
		linux,stdout-path = &MPSC0;
	};
};
Commit	Line	Data
61586476 RM	1	/* Device Tree Source for GEFanuc C2K
	2	*
	3	* Author: Remi Machet <rmachet@slac.stanford.edu>
	4	*
	5	* Originated from prpmc2800.dts
	6	*
	7	* 2008 (c) Stanford University
	8	* 2007 (c) MontaVista, Software, Inc.
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License version 2 as published
	12	* by the Free Software Foundation.
	13	*/
	14
	15	/dts-v1/;
	16
	17	/ {
	18	#address-cells = <1>;
	19	#size-cells = <1>;
	20	model = "C2K";
	21	compatible = "GEFanuc,C2K";
	22	coherency-off;
	23
	24	aliases {
	25	pci0 = &PCI0;
	26	pci1 = &PCI1;
	27	};
	28
	29	cpus {
	30	#address-cells = <1>;
	31	#size-cells = <0>;
	32
	33	cpu@0 {
	34	device_type = "cpu";
	35	compatible = "PowerPC,7447";
	36	reg = <0>;
	37	clock-frequency = <996000000>; /* 996 MHz */
	38	bus-frequency = <166666667>; /* 166.6666 MHz */
	39	timebase-frequency = <41666667>; /* 166.6666/4 MHz */
	40	i-cache-line-size = <32>;
	41	d-cache-line-size = <32>;
	42	i-cache-size = <32768>;
	43	d-cache-size = <32768>;
	44	};
	45	};
	46
	47	memory {
	48	device_type = "memory";
	49	reg = <0x00000000 0x40000000>; /* 1GB */
	50	};
	51
	52	system-controller@d8000000 { /* Marvell Discovery */
	53	#address-cells = <1>;
	54	#size-cells = <1>;
	55	model = "mv64460";
	56	compatible = "marvell,mv64360";
	57	clock-frequency = <166666667>; /* 166.66... MHz */
	58	reg = <0xd8000000 0x00010000>;
	59	virtual-reg = <0xd8000000>;
	60	ranges = <0xd4000000 0xd4000000 0x01000000 /* PCI 0 I/O Space */
	61	0x80000000 0x80000000 0x08000000 /* PCI 0 MEM Space */
	62	0xd0000000 0xd0000000 0x01000000 /* PCI 1 I/O Space */
	63	0xa0000000 0xa0000000 0x08000000 /* PCI 1 MEM Space */
	64	0xd8100000 0xd8100000 0x00010000 /* FPGA */
65	0xd8110000 0xd8110000 0x00010000 /* FPGA USARTs */
66	0xf8000000 0xf8000000 0x08000000 /* User FLASH */
67	0x00000000 0xd8000000 0x00010000 /* Bridge's regs */
68	0xd8140000 0xd8140000 0x00040000>; /* Integrated SRAM */
69
70	mdio@2000 {
71	#address-cells = <1>;
72	#size-cells = <0>;
73	compatible = "marvell,mv64360-mdio";
74	reg = <0x2000 4>;
75	PHY0: ethernet-phy@0 {
61586476 RM	76	interrupts = <76>; /* GPP 12 */
	77	interrupt-parent = <&PIC>;
	78	reg = <0>;
	79	};
	80	PHY1: ethernet-phy@1 {
61586476 RM	81	interrupts = <76>; /* GPP 12 */
	82	interrupt-parent = <&PIC>;
	83	reg = <1>;
	84	};
	85	PHY2: ethernet-phy@2 {
61586476 RM	86	interrupts = <76>; /* GPP 12 */
	87	interrupt-parent = <&PIC>;
	88	reg = <2>;
	89	};
	90	};
	91
	92	ethernet-group@2000 {
	93	#address-cells = <1>;
	94	#size-cells = <0>;
	95	compatible = "marvell,mv64360-eth-group";
	96	reg = <0x2000 0x2000>;
	97	ethernet@0 {
	98	device_type = "network";
	99	compatible = "marvell,mv64360-eth";
	100	reg = <0>;
	101	interrupts = <32>;
	102	interrupt-parent = <&PIC>;
	103	phy = <&PHY0>;
	104	local-mac-address = [ 00 00 00 00 00 00 ];
	105	};
	106	ethernet@1 {
	107	device_type = "network";
	108	compatible = "marvell,mv64360-eth";
	109	reg = <1>;
	110	interrupts = <33>;
	111	interrupt-parent = <&PIC>;
	112	phy = <&PHY1>;
	113	local-mac-address = [ 00 00 00 00 00 00 ];
	114	};
	115	ethernet@2 {
	116	device_type = "network";
	117	compatible = "marvell,mv64360-eth";
	118	reg = <2>;
	119	interrupts = <34>;
	120	interrupt-parent = <&PIC>;
	121	phy = <&PHY2>;
	122	local-mac-address = [ 00 00 00 00 00 00 ];
	123	};
	124	};
	125
	126	SDMA0: sdma@4000 {
	127	compatible = "marvell,mv64360-sdma";
	128	reg = <0x4000 0xc18>;
	129	virtual-reg = <0xd8004000>;
	130	interrupt-base = <0>;
	131	interrupts = <36>;
	132	interrupt-parent = <&PIC>;
	133	};
	134
	135	SDMA1: sdma@6000 {
	136	compatible = "marvell,mv64360-sdma";
	137	reg = <0x6000 0xc18>;
	138	virtual-reg = <0xd8006000>;
	139	interrupt-base = <0>;
	140	interrupts = <38>;
	141	interrupt-parent = <&PIC>;
	142	};
	143
	144	BRG0: brg@b200 {
	145	compatible = "marvell,mv64360-brg";
	146	reg = <0xb200 0x8>;
	147	clock-src = <8>;
	148	clock-frequency = <133333333>;
	149	current-speed = <115200>;
150	};
151
152	BRG1: brg@b208 {
153	compatible = "marvell,mv64360-brg";
154	reg = <0xb208 0x8>;
155	clock-src = <8>;
156	clock-frequency = <133333333>;
157	current-speed = <115200>;
158	};
159
160	CUNIT: cunit@f200 {
161	reg = <0xf200 0x200>;
162	};
163
164	MPSCROUTING: mpscrouting@b400 {
165	reg = <0xb400 0xc>;
166	};
167
168	MPSCINTR: mpscintr@b800 {
169	reg = <0xb800 0x100>;
170	virtual-reg = <0xd800b800>;
171	};
172
173	MPSC0: mpsc@8000 {
174	device_type = "serial";
175	compatible = "marvell,mv64360-mpsc";
176	reg = <0x8000 0x38>;
177	virtual-reg = <0xd8008000>;
178	sdma = <&SDMA0>;
179	brg = <&BRG0>;
180	cunit = <&CUNIT>;
181	mpscrouting = <&MPSCROUTING>;
182	mpscintr = <&MPSCINTR>;
183	cell-index = <0>;
184	interrupts = <40>;
185	interrupt-parent = <&PIC>;
186	};
187
188	MPSC1: mpsc@9000 {
189	device_type = "serial";
190	compatible = "marvell,mv64360-mpsc";
191	reg = <0x9000 0x38>;
192	virtual-reg = <0xd8009000>;
193	sdma = <&SDMA1>;
194	brg = <&BRG1>;
195	cunit = <&CUNIT>;
196	mpscrouting = <&MPSCROUTING>;
197	mpscintr = <&MPSCINTR>;
198	cell-index = <1>;
199	interrupts = <42>;
200	interrupt-parent = <&PIC>;
201	};
202
203	wdt@b410 { /* watchdog timer */
204	compatible = "marvell,mv64360-wdt";
205	reg = <0xb410 0x8>;
206	};
207
208	i2c@c000 {
209	compatible = "marvell,mv64360-i2c";
210	reg = <0xc000 0x20>;
211	virtual-reg = <0xd800c000>;
212	interrupts = <37>;
213	interrupt-parent = <&PIC>;
214	};
215
216	PIC: pic {
217	#interrupt-cells = <1>;
218	#address-cells = <0>;
219	compatible = "marvell,mv64360-pic";
220	reg = <0x0000 0x88>;
221	interrupt-controller;
222	};
223
224	mpp@f000 {
225	compatible = "marvell,mv64360-mpp";
226	reg = <0xf000 0x10>;
227	};
228
229	gpp@f100 {
230	compatible = "marvell,mv64360-gpp";
231	reg = <0xf100 0x20>;
232	};
233
234	PCI0: pci@80000000 {
235	#address-cells = <3>;
236	#size-cells = <2>;
237	#interrupt-cells = <1>;
238	device_type = "pci";
239	compatible = "marvell,mv64360-pci";
240	reg = <0x0cf8 0x8>;
241	ranges = <0x01000000 0x0 0x00000000 0xd4000000 0x0 0x01000000
242	0x02000000 0x0 0x80000000 0x80000000 0x0 0x08000000>;
243	bus-range = <0 255>;
244	clock-frequency = <66000000>;
245	interrupt-pci-iack = <0x0c34>;
246	interrupt-parent = <&PIC>;
247	interrupt-map-mask = <0x0000 0x0 0x0 0x7>;
248	interrupt-map = <
249	/* Only one interrupt line for PMC0 slot (INTA) */
250	0x0000 0 0 1 &PIC 88
251	>;
252	};
253
254
255	PCI1: pci@a0000000 {
256	#address-cells = <3>;
257	#size-cells = <2>;
258	#interrupt-cells = <1>;
259	device_type = "pci";
260	compatible = "marvell,mv64360-pci";
261	reg = <0x0c78 0x8>;
262	ranges = <0x01000000 0x0 0x00000000 0xd0000000 0x0 0x01000000
263	0x02000000 0x0 0x80000000 0xa0000000 0x0 0x08000000>;
264	bus-range = <0 255>;
265	clock-frequency = <66000000>;
266	interrupt-pci-iack = <0x0cb4>;
267	interrupt-parent = <&PIC>;
268	interrupt-map-mask = <0xf800 0x00 0x00 0x7>;
269	interrupt-map = <
270	/* IDSEL 0x01: PMC1 ? */
271	0x0800 0 0 1 &PIC 88
272	/* IDSEL 0x02: cPCI bridge */
273	0x1000 0 0 1 &PIC 88
274	/* IDSEL 0x03: USB controller */
275	0x1800 0 0 1 &PIC 91
276	/* IDSEL 0x04: SATA controller */
277	0x2000 0 0 1 &PIC 95
278	>;
279	};
280
281	cpu-error@0070 {
282	compatible = "marvell,mv64360-cpu-error";
283	reg = <0x0070 0x10 0x0128 0x28>;
284	interrupts = <3>;
285	interrupt-parent = <&PIC>;
286	};
287
288	sram-ctrl@0380 {
289	compatible = "marvell,mv64360-sram-ctrl";
290	reg = <0x0380 0x80>;
291	interrupts = <13>;
292	interrupt-parent = <&PIC>;
293	};
294
295	pci-error@1d40 {
296	compatible = "marvell,mv64360-pci-error";
297	reg = <0x1d40 0x40 0x0c28 0x4>;
298	interrupts = <12>;
299	interrupt-parent = <&PIC>;
300	};
301
302	pci-error@1dc0 {
303	compatible = "marvell,mv64360-pci-error";
304	reg = <0x1dc0 0x40 0x0ca8 0x4>;
305	interrupts = <16>;
306	interrupt-parent = <&PIC>;
307	};
308
309	mem-ctrl@1400 {
310	compatible = "marvell,mv64360-mem-ctrl";
311	reg = <0x1400 0x60>;
312	interrupts = <17>;
313	interrupt-parent = <&PIC>;
314	};
315	/* Devices attached to the device controller */
316	devicebus@045c {
317	#address-cells = <2>;
318	#size-cells = <1>;
319	compatible = "marvell,mv64306-devctrl";
320	reg = <0x45C 0x88>;
321	interrupts = <1>;
322	interrupt-parent = <&PIC>;
323	ranges = <0 0 0xd8100000 0x10000
324	2 0 0xd8110000 0x10000
325	4 0 0xf8000000 0x8000000>;
326	fpga@0,0 {
327	compatible = "sbs,fpga-c2k";
328	reg = <0 0 0x10000>;
329	};
330	fpga_usart@2,0 {
331	compatible = "sbs,fpga_usart-c2k";
332	reg = <2 0 0x10000>;
333	};
334	nor_flash@4,0 {
335	compatible = "cfi-flash";
336	reg = <4 0 0x8000000>; /* 128MB */
337	bank-width = <4>;
338	device-width = <1>;
339	#address-cells = <1>;
340	#size-cells = <1>;
341	partition@0 {
342	label = "boot";
343	reg = <0x00000000 0x00080000>;
344	};
345	partition@40000 {
346	label = "kernel";
347	reg = <0x00080000 0x00400000>;
348	};
349	partition@440000 {
350	label = "initrd";
351	reg = <0x00480000 0x00B80000>;
352	};
353	partition@1000000 {
354	label = "rootfs";
355	reg = <0x01000000 0x06800000>;
356	};
357	partition@7800000 {
358	label = "recovery";
359	reg = <0x07800000 0x00800000>;
360	read-only;
361	};
362	};
363	};
364	};
365	chosen {
366	linux,stdout-path = &MPSC0;
367	};
368	};