[deliverable/linux.git] / arch / powerpc / boot / dts / canyonlands.dts

/*
 * Device Tree Source for AMCC Canyonlands (460EX)
 *
 * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without
 * any warranty of any kind, whether express or implied.
 */

/dts-v1/;

/ {
	#address-cells = <2>;
	#size-cells = <1>;
	model = "amcc,canyonlands";
	compatible = "amcc,canyonlands";
	dcr-parent = <&{/cpus/cpu@0}>;

	aliases {
		ethernet0 = &EMAC0;
		ethernet1 = &EMAC1;
		serial0 = &UART0;
		serial1 = &UART1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			model = "PowerPC,460EX";
			reg = <0x00000000>;
			clock-frequency = <0>; /* Filled in by U-Boot */
			timebase-frequency = <0>; /* Filled in by U-Boot */
			i-cache-line-size = <32>;
			d-cache-line-size = <32>;
			i-cache-size = <32768>;
			d-cache-size = <32768>;
			dcr-controller;
			dcr-access-method = "native";
			next-level-cache = <&L2C0>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
	};

	UIC0: interrupt-controller0 {
		compatible = "ibm,uic-460ex","ibm,uic";
		interrupt-controller;
		cell-index = <0>;
		dcr-reg = <0x0c0 0x009>;
		#address-cells = <0>;
		#size-cells = <0>;
		#interrupt-cells = <2>;
	};

	UIC1: interrupt-controller1 {
		compatible = "ibm,uic-460ex","ibm,uic";
		interrupt-controller;
		cell-index = <1>;
		dcr-reg = <0x0d0 0x009>;
		#address-cells = <0>;
		#size-cells = <0>;
		#interrupt-cells = <2>;
		interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
		interrupt-parent = <&UIC0>;
	};

	UIC2: interrupt-controller2 {
		compatible = "ibm,uic-460ex","ibm,uic";
		interrupt-controller;
		cell-index = <2>;
		dcr-reg = <0x0e0 0x009>;
		#address-cells = <0>;
		#size-cells = <0>;
		#interrupt-cells = <2>;
		interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
		interrupt-parent = <&UIC0>;
	};

	UIC3: interrupt-controller3 {
		compatible = "ibm,uic-460ex","ibm,uic";
		interrupt-controller;
		cell-index = <3>;
		dcr-reg = <0x0f0 0x009>;
		#address-cells = <0>;
		#size-cells = <0>;
		#interrupt-cells = <2>;
		interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
		interrupt-parent = <&UIC0>;
	};

	SDR0: sdr {
		compatible = "ibm,sdr-460ex";
		dcr-reg = <0x00e 0x002>;
	};

	CPR0: cpr {
		compatible = "ibm,cpr-460ex";
		dcr-reg = <0x00c 0x002>;
	};

	L2C0: l2c {
		compatible = "ibm,l2-cache-460ex", "ibm,l2-cache";
		dcr-reg = <0x020 0x008		/* Internal SRAM DCR's */
			   0x030 0x008>;	/* L2 cache DCR's */
		cache-line-size = <32>;		/* 32 bytes */
		cache-size = <262144>;		/* L2, 256K */
		interrupt-parent = <&UIC1>;
		interrupts = <11 1>;
	};

	plb {
		compatible = "ibm,plb-460ex", "ibm,plb4";
		#address-cells = <2>;
		#size-cells = <1>;
		ranges;
		clock-frequency = <0>; /* Filled in by U-Boot */

		SDRAM0: sdram {
			compatible = "ibm,sdram-460ex", "ibm,sdram-405gp";
			dcr-reg = <0x010 0x002>;
		};

		MAL0: mcmal {
			compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
			dcr-reg = <0x180 0x062>;
			num-tx-chans = <2>;
			num-rx-chans = <16>;
			#address-cells = <0>;
			#size-cells = <0>;
			interrupt-parent = <&UIC2>;
			interrupts = <	/*TXEOB*/ 0x6 0x4
					/*RXEOB*/ 0x7 0x4
					/*SERR*/  0x3 0x4
					/*TXDE*/  0x4 0x4
					/*RXDE*/  0x5 0x4>;
		};

                USB0: ehci@bffd0400 {
                        compatible = "ibm,usb-ehci-460ex", "usb-ehci";
                        interrupt-parent = <&UIC2>;
                        interrupts = <0x1d 4>;
                        reg = <4 0xbffd0400 0x90 4 0xbffd0490 0x70>;
                };

                USB1: usb@bffd0000 {
                        compatible = "ohci-le";
                        reg = <4 0xbffd0000 0x60>;
                        interrupt-parent = <&UIC2>;
                        interrupts = <0x1e 4>;
                };

		POB0: opb {
			compatible = "ibm,opb-460ex", "ibm,opb";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
			clock-frequency = <0>; /* Filled in by U-Boot */

			EBC0: ebc {
				compatible = "ibm,ebc-460ex", "ibm,ebc";
				dcr-reg = <0x012 0x002>;
				#address-cells = <2>;
				#size-cells = <1>;
				clock-frequency = <0>; /* Filled in by U-Boot */
				/* ranges property is supplied by U-Boot */
				interrupts = <0x6 0x4>;
				interrupt-parent = <&UIC1>;

				nor_flash@0,0 {
					compatible = "amd,s29gl512n", "cfi-flash";
					bank-width = <2>;
					reg = <0x00000000 0x00000000 0x04000000>;
					#address-cells = <1>;
					#size-cells = <1>;
					partition@0 {
						label = "kernel";
						reg = <0x00000000 0x001e0000>;
					};
					partition@1e0000 {
						label = "dtb";
						reg = <0x001e0000 0x00020000>;
					};
					partition@200000 {
						label = "ramdisk";
						reg = <0x00200000 0x01400000>;
					};
					partition@1600000 {
						label = "jffs2";
						reg = <0x01600000 0x00400000>;
					};
					partition@1a00000 {
						label = "user";
						reg = <0x01a00000 0x02560000>;
					};
					partition@3f60000 {
						label = "env";
						reg = <0x03f60000 0x00040000>;
					};
					partition@3fa0000 {
						label = "u-boot";
						reg = <0x03fa0000 0x00060000>;
					};
				};
			};

			UART0: serial@ef600300 {
				device_type = "serial";
				compatible = "ns16550";
				reg = <0xef600300 0x00000008>;
				virtual-reg = <0xef600300>;
				clock-frequency = <0>; /* Filled in by U-Boot */
				current-speed = <0>; /* Filled in by U-Boot */
				interrupt-parent = <&UIC1>;
				interrupts = <0x1 0x4>;
			};

			UART1: serial@ef600400 {
				device_type = "serial";
				compatible = "ns16550";
				reg = <0xef600400 0x00000008>;
				virtual-reg = <0xef600400>;
				clock-frequency = <0>; /* Filled in by U-Boot */
				current-speed = <0>; /* Filled in by U-Boot */
				interrupt-parent = <&UIC0>;
				interrupts = <0x1 0x4>;
			};

			UART2: serial@ef600500 {
				device_type = "serial";
				compatible = "ns16550";
				reg = <0xef600500 0x00000008>;
				virtual-reg = <0xef600500>;
				clock-frequency = <0>; /* Filled in by U-Boot */
				current-speed = <0>; /* Filled in by U-Boot */
				interrupt-parent = <&UIC1>;
				interrupts = <0x1d 0x4>;
			};

			UART3: serial@ef600600 {
				device_type = "serial";
				compatible = "ns16550";
				reg = <0xef600600 0x00000008>;
				virtual-reg = <0xef600600>;
				clock-frequency = <0>; /* Filled in by U-Boot */
				current-speed = <0>; /* Filled in by U-Boot */
				interrupt-parent = <&UIC1>;
				interrupts = <0x1e 0x4>;
			};

			IIC0: i2c@ef600700 {
				compatible = "ibm,iic-460ex", "ibm,iic";
				reg = <0xef600700 0x00000014>;
				interrupt-parent = <&UIC0>;
				interrupts = <0x2 0x4>;
				#address-cells = <1>;
				#size-cells = <0>;
                                rtc@68 {
                                        compatible = "stm,m41t80";
                                        reg = <0x68>;
					interrupt-parent = <&UIC2>;
					interrupts = <0x19 0x8>;
                                };
                                sttm@48 {
                                        compatible = "ad,ad7414";
                                        reg = <0x48>;
					interrupt-parent = <&UIC1>;
					interrupts = <0x14 0x8>;
                                };
			};

			IIC1: i2c@ef600800 {
				compatible = "ibm,iic-460ex", "ibm,iic";
				reg = <0xef600800 0x00000014>;
				interrupt-parent = <&UIC0>;
				interrupts = <0x3 0x4>;
			};

			ZMII0: emac-zmii@ef600d00 {
				compatible = "ibm,zmii-460ex", "ibm,zmii";
				reg = <0xef600d00 0x0000000c>;
			};

			RGMII0: emac-rgmii@ef601500 {
				compatible = "ibm,rgmii-460ex", "ibm,rgmii";
				reg = <0xef601500 0x00000008>;
				has-mdio;
			};

			TAH0: emac-tah@ef601350 {
				compatible = "ibm,tah-460ex", "ibm,tah";
				reg = <0xef601350 0x00000030>;
			};

			TAH1: emac-tah@ef601450 {
				compatible = "ibm,tah-460ex", "ibm,tah";
				reg = <0xef601450 0x00000030>;
			};

			EMAC0: ethernet@ef600e00 {
				device_type = "network";
				compatible = "ibm,emac-460ex", "ibm,emac4sync";
				interrupt-parent = <&EMAC0>;
				interrupts = <0x0 0x1>;
				#interrupt-cells = <1>;
				#address-cells = <0>;
				#size-cells = <0>;
				interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
						 /*Wake*/   0x1 &UIC2 0x14 0x4>;
				reg = <0xef600e00 0x000000c4>;
				local-mac-address = [000000000000]; /* Filled in by U-Boot */
				mal-device = <&MAL0>;
				mal-tx-channel = <0>;
				mal-rx-channel = <0>;
				cell-index = <0>;
				max-frame-size = <9000>;
				rx-fifo-size = <4096>;
				tx-fifo-size = <2048>;
				phy-mode = "rgmii";
				phy-map = <0x00000000>;
				rgmii-device = <&RGMII0>;
				rgmii-channel = <0>;
				tah-device = <&TAH0>;
				tah-channel = <0>;
				has-inverted-stacr-oc;
				has-new-stacr-staopc;
			};

			EMAC1: ethernet@ef600f00 {
				device_type = "network";
				compatible = "ibm,emac-460ex", "ibm,emac4sync";
				interrupt-parent = <&EMAC1>;
				interrupts = <0x0 0x1>;
				#interrupt-cells = <1>;
				#address-cells = <0>;
				#size-cells = <0>;
				interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
						 /*Wake*/   0x1 &UIC2 0x15 0x4>;
				reg = <0xef600f00 0x000000c4>;
				local-mac-address = [000000000000]; /* Filled in by U-Boot */
				mal-device = <&MAL0>;
				mal-tx-channel = <1>;
				mal-rx-channel = <8>;
				cell-index = <1>;
				max-frame-size = <9000>;
				rx-fifo-size = <4096>;
				tx-fifo-size = <2048>;
				phy-mode = "rgmii";
				phy-map = <0x00000000>;
				rgmii-device = <&RGMII0>;
				rgmii-channel = <1>;
				tah-device = <&TAH1>;
				tah-channel = <1>;
				has-inverted-stacr-oc;
				has-new-stacr-staopc;
				mdio-device = <&EMAC0>;
			};
		};

		PCIX0: pci@c0ec00000 {
			device_type = "pci";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix";
			primary;
			large-inbound-windows;
			enable-msi-hole;
			reg = <0x0000000c 0x0ec00000   0x00000008	/* Config space access */
			       0x00000000 0x00000000 0x00000000		/* no IACK cycles */
			       0x0000000c 0x0ed00000   0x00000004   /* Special cycles */
			       0x0000000c 0x0ec80000 0x00000100	/* Internal registers */
			       0x0000000c 0x0ec80100  0x000000fc>;	/* Internal messaging registers */

			/* Outbound ranges, one memory and one IO,
			 * later cannot be changed
			 */
			ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
				  0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000
				  0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;

			/* Inbound 2GB range starting at 0 */
			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;

			/* This drives busses 0 to 0x3f */
			bus-range = <0x0 0x3f>;

			/* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
			interrupt-map-mask = <0x0 0x0 0x0 0x0>;
			interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
		};

		PCIE0: pciex@d00000000 {
			device_type = "pci";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
			primary;
			port = <0x0>; /* port number */
			reg = <0x0000000d 0x00000000 0x20000000	/* Config space access */
			       0x0000000c 0x08010000 0x00001000>;	/* Registers */
			dcr-reg = <0x100 0x020>;
			sdr-base = <0x300>;

			/* Outbound ranges, one memory and one IO,
			 * later cannot be changed
			 */
			ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
				  0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
				  0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;

			/* Inbound 2GB range starting at 0 */
			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;

			/* This drives busses 40 to 0x7f */
			bus-range = <0x40 0x7f>;

			/* Legacy interrupts (note the weird polarity, the bridge seems
			 * to invert PCIe legacy interrupts).
			 * We are de-swizzling here because the numbers are actually for
			 * port of the root complex virtual P2P bridge. But I want
			 * to avoid putting a node for it in the tree, so the numbers
			 * below are basically de-swizzled numbers.
			 * The real slot is on idsel 0, so the swizzling is 1:1
			 */
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <
				0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
				0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
				0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
				0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
		};

		PCIE1: pciex@d20000000 {
			device_type = "pci";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
			primary;
			port = <0x1>; /* port number */
			reg = <0x0000000d 0x20000000 0x20000000	/* Config space access */
			       0x0000000c 0x08011000 0x00001000>;	/* Registers */
			dcr-reg = <0x120 0x020>;
			sdr-base = <0x340>;

			/* Outbound ranges, one memory and one IO,
			 * later cannot be changed
			 */
			ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
				  0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000
				  0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;

			/* Inbound 2GB range starting at 0 */
			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;

			/* This drives busses 80 to 0xbf */
			bus-range = <0x80 0xbf>;

			/* Legacy interrupts (note the weird polarity, the bridge seems
			 * to invert PCIe legacy interrupts).
			 * We are de-swizzling here because the numbers are actually for
			 * port of the root complex virtual P2P bridge. But I want
			 * to avoid putting a node for it in the tree, so the numbers
			 * below are basically de-swizzled numbers.
			 * The real slot is on idsel 0, so the swizzling is 1:1
			 */
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <
				0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */
				0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */
				0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
				0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;
		};
	};
};
Commit	Line	Data
8bc4a51d SR	1	/*
	2	* Device Tree Source for AMCC Canyonlands (460EX)
	3	*
	4	* Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without
	8	* any warranty of any kind, whether express or implied.
	9	*/
	10
71f34979 DG	11	/dts-v1/;
71f34979 DG	12
8bc4a51d SR	13	/ {
	14	#address-cells = <2>;
	15	#size-cells = <1>;
	16	model = "amcc,canyonlands";
	17	compatible = "amcc,canyonlands";
71f34979	18	dcr-parent = <&{/cpus/cpu@0}>;
8bc4a51d SR	19
	20	aliases {
	21	ethernet0 = &EMAC0;
	22	ethernet1 = &EMAC1;
	23	serial0 = &UART0;
	24	serial1 = &UART1;
	25	};
	26
	27	cpus {
	28	#address-cells = <1>;
	29	#size-cells = <0>;
	30
	31	cpu@0 {
	32	device_type = "cpu";
	33	model = "PowerPC,460EX";
71f34979	34	reg = <0x00000000>;
8bc4a51d SR	35	clock-frequency = <0>; /* Filled in by U-Boot */
8bc4a51d SR	36	timebase-frequency = <0>; /* Filled in by U-Boot */
71f34979 DG	37	i-cache-line-size = <32>;
	38	d-cache-line-size = <32>;
	39	i-cache-size = <32768>;
	40	d-cache-size = <32768>;
8bc4a51d SR	41	dcr-controller;
8bc4a51d SR	42	dcr-access-method = "native";
cd85400a	43	next-level-cache = <&L2C0>;
8bc4a51d SR	44	};
	45	};
	46
	47	memory {
	48	device_type = "memory";
71f34979	49	reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
8bc4a51d SR	50	};
	51
	52	UIC0: interrupt-controller0 {
	53	compatible = "ibm,uic-460ex","ibm,uic";
	54	interrupt-controller;
	55	cell-index = <0>;
71f34979	56	dcr-reg = <0x0c0 0x009>;
8bc4a51d SR	57	#address-cells = <0>;
	58	#size-cells = <0>;
	59	#interrupt-cells = <2>;
	60	};
	61
	62	UIC1: interrupt-controller1 {
	63	compatible = "ibm,uic-460ex","ibm,uic";
	64	interrupt-controller;
	65	cell-index = <1>;
71f34979	66	dcr-reg = <0x0d0 0x009>;
8bc4a51d SR	67	#address-cells = <0>;
	68	#size-cells = <0>;
	69	#interrupt-cells = <2>;
71f34979	70	interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
8bc4a51d SR	71	interrupt-parent = <&UIC0>;
	72	};
	73
	74	UIC2: interrupt-controller2 {
	75	compatible = "ibm,uic-460ex","ibm,uic";
	76	interrupt-controller;
	77	cell-index = <2>;
71f34979	78	dcr-reg = <0x0e0 0x009>;
8bc4a51d SR	79	#address-cells = <0>;
	80	#size-cells = <0>;
	81	#interrupt-cells = <2>;
71f34979	82	interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
8bc4a51d SR	83	interrupt-parent = <&UIC0>;
	84	};
	85
	86	UIC3: interrupt-controller3 {
	87	compatible = "ibm,uic-460ex","ibm,uic";
	88	interrupt-controller;
	89	cell-index = <3>;
71f34979	90	dcr-reg = <0x0f0 0x009>;
8bc4a51d SR	91	#address-cells = <0>;
	92	#size-cells = <0>;
	93	#interrupt-cells = <2>;
71f34979	94	interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
8bc4a51d SR	95	interrupt-parent = <&UIC0>;
	96	};
	97
	98	SDR0: sdr {
	99	compatible = "ibm,sdr-460ex";
71f34979	100	dcr-reg = <0x00e 0x002>;
8bc4a51d SR	101	};
	102
	103	CPR0: cpr {
	104	compatible = "ibm,cpr-460ex";
71f34979	105	dcr-reg = <0x00c 0x002>;
8bc4a51d SR	106	};
8bc4a51d SR	107
cd85400a SR	108	L2C0: l2c {
	109	compatible = "ibm,l2-cache-460ex", "ibm,l2-cache";
	110	dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
	111	0x030 0x008>; /* L2 cache DCR's */
	112	cache-line-size = <32>; /* 32 bytes */
	113	cache-size = <262144>; /* L2, 256K */
	114	interrupt-parent = <&UIC1>;
	115	interrupts = <11 1>;
	116	};
	117
8bc4a51d SR	118	plb {
	119	compatible = "ibm,plb-460ex", "ibm,plb4";
	120	#address-cells = <2>;
	121	#size-cells = <1>;
	122	ranges;
	123	clock-frequency = <0>; /* Filled in by U-Boot */
	124
	125	SDRAM0: sdram {
	126	compatible = "ibm,sdram-460ex", "ibm,sdram-405gp";
71f34979	127	dcr-reg = <0x010 0x002>;
8bc4a51d SR	128	};
	129
	130	MAL0: mcmal {
	131	compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
71f34979	132	dcr-reg = <0x180 0x062>;
8bc4a51d	133	num-tx-chans = <2>;
71f34979	134	num-rx-chans = <16>;
8bc4a51d SR	135	#address-cells = <0>;
	136	#size-cells = <0>;
	137	interrupt-parent = <&UIC2>;
71f34979 DG	138	interrupts = < /TXEOB/ 0x6 0x4
	139	/RXEOB/ 0x7 0x4
	140	/SERR/ 0x3 0x4
	141	/TXDE/ 0x4 0x4
	142	/RXDE/ 0x5 0x4>;
8bc4a51d SR	143	};
8bc4a51d SR	144
018f76ec BH	145	USB0: ehci@bffd0400 {
	146	compatible = "ibm,usb-ehci-460ex", "usb-ehci";
	147	interrupt-parent = <&UIC2>;
	148	interrupts = <0x1d 4>;
	149	reg = <4 0xbffd0400 0x90 4 0xbffd0490 0x70>;
	150	};
	151
	152	USB1: usb@bffd0000 {
	153	compatible = "ohci-le";
	154	reg = <4 0xbffd0000 0x60>;
	155	interrupt-parent = <&UIC2>;
	156	interrupts = <0x1e 4>;
	157	};
	158
8bc4a51d SR	159	POB0: opb {
	160	compatible = "ibm,opb-460ex", "ibm,opb";
	161	#address-cells = <1>;
	162	#size-cells = <1>;
71f34979	163	ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
8bc4a51d SR	164	clock-frequency = <0>; /* Filled in by U-Boot */
	165
	166	EBC0: ebc {
	167	compatible = "ibm,ebc-460ex", "ibm,ebc";
71f34979	168	dcr-reg = <0x012 0x002>;
8bc4a51d SR	169	#address-cells = <2>;
	170	#size-cells = <1>;
	171	clock-frequency = <0>; /* Filled in by U-Boot */
5020231b	172	/* ranges property is supplied by U-Boot */
71f34979	173	interrupts = <0x6 0x4>;
8bc4a51d	174	interrupt-parent = <&UIC1>;
5020231b SR	175
	176	nor_flash@0,0 {
	177	compatible = "amd,s29gl512n", "cfi-flash";
	178	bank-width = <2>;
71f34979	179	reg = <0x00000000 0x00000000 0x04000000>;
5020231b SR	180	#address-cells = <1>;
	181	#size-cells = <1>;
	182	partition@0 {
	183	label = "kernel";
71f34979	184	reg = <0x00000000 0x001e0000>;
5020231b SR	185	};
	186	partition@1e0000 {
	187	label = "dtb";
71f34979	188	reg = <0x001e0000 0x00020000>;
5020231b SR	189	};
	190	partition@200000 {
	191	label = "ramdisk";
71f34979	192	reg = <0x00200000 0x01400000>;
5020231b SR	193	};
	194	partition@1600000 {
	195	label = "jffs2";
71f34979	196	reg = <0x01600000 0x00400000>;
5020231b SR	197	};
	198	partition@1a00000 {
	199	label = "user";
71f34979	200	reg = <0x01a00000 0x02560000>;
5020231b SR	201	};
	202	partition@3f60000 {
	203	label = "env";
71f34979	204	reg = <0x03f60000 0x00040000>;
5020231b SR	205	};
	206	partition@3fa0000 {
	207	label = "u-boot";
71f34979	208	reg = <0x03fa0000 0x00060000>;
5020231b SR	209	};
5020231b SR	210	};
8bc4a51d SR	211	};
	212
	213	UART0: serial@ef600300 {
	214	device_type = "serial";
	215	compatible = "ns16550";
71f34979 DG	216	reg = <0xef600300 0x00000008>;
71f34979 DG	217	virtual-reg = <0xef600300>;
8bc4a51d SR	218	clock-frequency = <0>; /* Filled in by U-Boot */
	219	current-speed = <0>; /* Filled in by U-Boot */
	220	interrupt-parent = <&UIC1>;
71f34979	221	interrupts = <0x1 0x4>;
8bc4a51d SR	222	};
	223
	224	UART1: serial@ef600400 {
	225	device_type = "serial";
	226	compatible = "ns16550";
71f34979 DG	227	reg = <0xef600400 0x00000008>;
71f34979 DG	228	virtual-reg = <0xef600400>;
8bc4a51d SR	229	clock-frequency = <0>; /* Filled in by U-Boot */
	230	current-speed = <0>; /* Filled in by U-Boot */
	231	interrupt-parent = <&UIC0>;
71f34979	232	interrupts = <0x1 0x4>;
8bc4a51d SR	233	};
	234
	235	UART2: serial@ef600500 {
	236	device_type = "serial";
	237	compatible = "ns16550";
71f34979 DG	238	reg = <0xef600500 0x00000008>;
71f34979 DG	239	virtual-reg = <0xef600500>;
8bc4a51d SR	240	clock-frequency = <0>; /* Filled in by U-Boot */
	241	current-speed = <0>; /* Filled in by U-Boot */
	242	interrupt-parent = <&UIC1>;
71f34979	243	interrupts = <0x1d 0x4>;
8bc4a51d SR	244	};
	245
	246	UART3: serial@ef600600 {
	247	device_type = "serial";
	248	compatible = "ns16550";
71f34979 DG	249	reg = <0xef600600 0x00000008>;
71f34979 DG	250	virtual-reg = <0xef600600>;
8bc4a51d SR	251	clock-frequency = <0>; /* Filled in by U-Boot */
	252	current-speed = <0>; /* Filled in by U-Boot */
	253	interrupt-parent = <&UIC1>;
71f34979	254	interrupts = <0x1e 0x4>;
8bc4a51d SR	255	};
	256
	257	IIC0: i2c@ef600700 {
	258	compatible = "ibm,iic-460ex", "ibm,iic";
71f34979	259	reg = <0xef600700 0x00000014>;
8bc4a51d	260	interrupt-parent = <&UIC0>;
71f34979	261	interrupts = <0x2 0x4>;
018f76ec BH	262	#address-cells = <1>;
	263	#size-cells = <0>;
	264	rtc@68 {
	265	compatible = "stm,m41t80";
	266	reg = <0x68>;
	267	interrupt-parent = <&UIC2>;
	268	interrupts = <0x19 0x8>;
	269	};
	270	sttm@48 {
	271	compatible = "ad,ad7414";
	272	reg = <0x48>;
	273	interrupt-parent = <&UIC1>;
	274	interrupts = <0x14 0x8>;
	275	};
8bc4a51d SR	276	};
	277
	278	IIC1: i2c@ef600800 {
	279	compatible = "ibm,iic-460ex", "ibm,iic";
71f34979	280	reg = <0xef600800 0x00000014>;
8bc4a51d	281	interrupt-parent = <&UIC0>;
71f34979	282	interrupts = <0x3 0x4>;
8bc4a51d SR	283	};
	284
	285	ZMII0: emac-zmii@ef600d00 {
	286	compatible = "ibm,zmii-460ex", "ibm,zmii";
71f34979	287	reg = <0xef600d00 0x0000000c>;
8bc4a51d SR	288	};
	289
	290	RGMII0: emac-rgmii@ef601500 {
	291	compatible = "ibm,rgmii-460ex", "ibm,rgmii";
71f34979	292	reg = <0xef601500 0x00000008>;
8bc4a51d SR	293	has-mdio;
	294	};
	295
a6190a84 SR	296	TAH0: emac-tah@ef601350 {
a6190a84 SR	297	compatible = "ibm,tah-460ex", "ibm,tah";
71f34979	298	reg = <0xef601350 0x00000030>;
a6190a84 SR	299	};
	300
	301	TAH1: emac-tah@ef601450 {
	302	compatible = "ibm,tah-460ex", "ibm,tah";
71f34979	303	reg = <0xef601450 0x00000030>;
a6190a84 SR	304	};
a6190a84 SR	305
8bc4a51d SR	306	EMAC0: ethernet@ef600e00 {
8bc4a51d SR	307	device_type = "network";
05781ccd	308	compatible = "ibm,emac-460ex", "ibm,emac4sync";
8bc4a51d	309	interrupt-parent = <&EMAC0>;
71f34979	310	interrupts = <0x0 0x1>;
8bc4a51d SR	311	#interrupt-cells = <1>;
	312	#address-cells = <0>;
	313	#size-cells = <0>;
71f34979 DG	314	interrupt-map = </Status/ 0x0 &UIC2 0x10 0x4
71f34979 DG	315	/Wake/ 0x1 &UIC2 0x14 0x4>;
05781ccd	316	reg = <0xef600e00 0x000000c4>;
8bc4a51d SR	317	local-mac-address = [000000000000]; /* Filled in by U-Boot */
	318	mal-device = <&MAL0>;
	319	mal-tx-channel = <0>;
	320	mal-rx-channel = <0>;
	321	cell-index = <0>;
71f34979 DG	322	max-frame-size = <9000>;
	323	rx-fifo-size = <4096>;
	324	tx-fifo-size = <2048>;
8bc4a51d	325	phy-mode = "rgmii";
71f34979	326	phy-map = <0x00000000>;
8bc4a51d SR	327	rgmii-device = <&RGMII0>;
8bc4a51d SR	328	rgmii-channel = <0>;
a6190a84 SR	329	tah-device = <&TAH0>;
a6190a84 SR	330	tah-channel = <0>;
8bc4a51d SR	331	has-inverted-stacr-oc;
	332	has-new-stacr-staopc;
	333	};
	334
	335	EMAC1: ethernet@ef600f00 {
	336	device_type = "network";
05781ccd	337	compatible = "ibm,emac-460ex", "ibm,emac4sync";
8bc4a51d	338	interrupt-parent = <&EMAC1>;
71f34979	339	interrupts = <0x0 0x1>;
8bc4a51d SR	340	#interrupt-cells = <1>;
	341	#address-cells = <0>;
	342	#size-cells = <0>;
71f34979 DG	343	interrupt-map = </Status/ 0x0 &UIC2 0x11 0x4
71f34979 DG	344	/Wake/ 0x1 &UIC2 0x15 0x4>;
05781ccd	345	reg = <0xef600f00 0x000000c4>;
8bc4a51d SR	346	local-mac-address = [000000000000]; /* Filled in by U-Boot */
	347	mal-device = <&MAL0>;
	348	mal-tx-channel = <1>;
	349	mal-rx-channel = <8>;
	350	cell-index = <1>;
71f34979 DG	351	max-frame-size = <9000>;
	352	rx-fifo-size = <4096>;
	353	tx-fifo-size = <2048>;
8bc4a51d	354	phy-mode = "rgmii";
71f34979	355	phy-map = <0x00000000>;
8bc4a51d SR	356	rgmii-device = <&RGMII0>;
8bc4a51d SR	357	rgmii-channel = <1>;
a6190a84 SR	358	tah-device = <&TAH1>;
a6190a84 SR	359	tah-channel = <1>;
8bc4a51d SR	360	has-inverted-stacr-oc;
8bc4a51d SR	361	has-new-stacr-staopc;
a6190a84	362	mdio-device = <&EMAC0>;
8bc4a51d SR	363	};
	364	};
	365
	366	PCIX0: pci@c0ec00000 {
	367	device_type = "pci";
	368	#interrupt-cells = <1>;
	369	#size-cells = <2>;
	370	#address-cells = <3>;
	371	compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix";
	372	primary;
	373	large-inbound-windows;
	374	enable-msi-hole;
71f34979 DG	375	reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
	376	0x00000000 0x00000000 0x00000000 /* no IACK cycles */
	377	0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
	378	0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
	379	0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
8bc4a51d SR	380
	381	/* Outbound ranges, one memory and one IO,
	382	* later cannot be changed
	383	*/
71f34979	384	ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
84d727a1	385	0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000
71f34979	386	0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
8bc4a51d SR	387
8bc4a51d SR	388	/* Inbound 2GB range starting at 0 */
71f34979	389	dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
8bc4a51d SR	390
8bc4a51d SR	391	/* This drives busses 0 to 0x3f */
71f34979	392	bus-range = <0x0 0x3f>;
8bc4a51d SR	393
8bc4a51d SR	394	/* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
71f34979 DG	395	interrupt-map-mask = <0x0 0x0 0x0 0x0>;
71f34979 DG	396	interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
8bc4a51d SR	397	};
	398
	399	PCIE0: pciex@d00000000 {
	400	device_type = "pci";
	401	#interrupt-cells = <1>;
	402	#size-cells = <2>;
	403	#address-cells = <3>;
	404	compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
	405	primary;
71f34979 DG	406	port = <0x0>; /* port number */
	407	reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
	408	0x0000000c 0x08010000 0x00001000>; /* Registers */
	409	dcr-reg = <0x100 0x020>;
	410	sdr-base = <0x300>;
8bc4a51d SR	411
	412	/* Outbound ranges, one memory and one IO,
	413	* later cannot be changed
	414	*/
71f34979	415	ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
84d727a1	416	0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
71f34979	417	0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
8bc4a51d SR	418
8bc4a51d SR	419	/* Inbound 2GB range starting at 0 */
71f34979	420	dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
8bc4a51d SR	421
8bc4a51d SR	422	/* This drives busses 40 to 0x7f */
71f34979	423	bus-range = <0x40 0x7f>;
8bc4a51d SR	424
	425	/* Legacy interrupts (note the weird polarity, the bridge seems
	426	* to invert PCIe legacy interrupts).
	427	* We are de-swizzling here because the numbers are actually for
	428	* port of the root complex virtual P2P bridge. But I want
	429	* to avoid putting a node for it in the tree, so the numbers
	430	* below are basically de-swizzled numbers.
	431	* The real slot is on idsel 0, so the swizzling is 1:1
	432	*/
71f34979	433	interrupt-map-mask = <0x0 0x0 0x0 0x7>;
8bc4a51d	434	interrupt-map = <
71f34979 DG	435	0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
	436	0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
	437	0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
	438	0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
8bc4a51d SR	439	};
	440
	441	PCIE1: pciex@d20000000 {
	442	device_type = "pci";
	443	#interrupt-cells = <1>;
	444	#size-cells = <2>;
	445	#address-cells = <3>;
	446	compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
	447	primary;
71f34979 DG	448	port = <0x1>; /* port number */
	449	reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
	450	0x0000000c 0x08011000 0x00001000>; /* Registers */
	451	dcr-reg = <0x120 0x020>;
	452	sdr-base = <0x340>;
8bc4a51d SR	453
	454	/* Outbound ranges, one memory and one IO,
	455	* later cannot be changed
	456	*/
71f34979	457	ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
84d727a1	458	0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000
71f34979	459	0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
8bc4a51d SR	460
8bc4a51d SR	461	/* Inbound 2GB range starting at 0 */
71f34979	462	dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
8bc4a51d SR	463
8bc4a51d SR	464	/* This drives busses 80 to 0xbf */
71f34979	465	bus-range = <0x80 0xbf>;
8bc4a51d SR	466
	467	/* Legacy interrupts (note the weird polarity, the bridge seems
	468	* to invert PCIe legacy interrupts).
	469	* We are de-swizzling here because the numbers are actually for
	470	* port of the root complex virtual P2P bridge. But I want
	471	* to avoid putting a node for it in the tree, so the numbers
	472	* below are basically de-swizzled numbers.
	473	* The real slot is on idsel 0, so the swizzling is 1:1
	474	*/
71f34979	475	interrupt-map-mask = <0x0 0x0 0x0 0x7>;
8bc4a51d	476	interrupt-map = <
71f34979 DG	477	0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */
	478	0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */
	479	0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
	480	0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;
8bc4a51d SR	481	};
	482	};
	483	};