Commit | Line | Data |
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8bc4a51d SR |
1 | /* |
2 | * Device Tree Source for AMCC Canyonlands (460EX) | |
3 | * | |
4 | * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de> | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public | |
7 | * License version 2. This program is licensed "as is" without | |
8 | * any warranty of any kind, whether express or implied. | |
9 | */ | |
10 | ||
71f34979 DG |
11 | /dts-v1/; |
12 | ||
8bc4a51d SR |
13 | / { |
14 | #address-cells = <2>; | |
15 | #size-cells = <1>; | |
16 | model = "amcc,canyonlands"; | |
17 | compatible = "amcc,canyonlands"; | |
71f34979 | 18 | dcr-parent = <&{/cpus/cpu@0}>; |
8bc4a51d SR |
19 | |
20 | aliases { | |
21 | ethernet0 = &EMAC0; | |
22 | ethernet1 = &EMAC1; | |
23 | serial0 = &UART0; | |
24 | serial1 = &UART1; | |
25 | }; | |
26 | ||
27 | cpus { | |
28 | #address-cells = <1>; | |
29 | #size-cells = <0>; | |
30 | ||
31 | cpu@0 { | |
32 | device_type = "cpu"; | |
33 | model = "PowerPC,460EX"; | |
71f34979 | 34 | reg = <0x00000000>; |
8bc4a51d SR |
35 | clock-frequency = <0>; /* Filled in by U-Boot */ |
36 | timebase-frequency = <0>; /* Filled in by U-Boot */ | |
71f34979 DG |
37 | i-cache-line-size = <32>; |
38 | d-cache-line-size = <32>; | |
39 | i-cache-size = <32768>; | |
40 | d-cache-size = <32768>; | |
8bc4a51d SR |
41 | dcr-controller; |
42 | dcr-access-method = "native"; | |
43 | }; | |
44 | }; | |
45 | ||
46 | memory { | |
47 | device_type = "memory"; | |
71f34979 | 48 | reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */ |
8bc4a51d SR |
49 | }; |
50 | ||
51 | UIC0: interrupt-controller0 { | |
52 | compatible = "ibm,uic-460ex","ibm,uic"; | |
53 | interrupt-controller; | |
54 | cell-index = <0>; | |
71f34979 | 55 | dcr-reg = <0x0c0 0x009>; |
8bc4a51d SR |
56 | #address-cells = <0>; |
57 | #size-cells = <0>; | |
58 | #interrupt-cells = <2>; | |
59 | }; | |
60 | ||
61 | UIC1: interrupt-controller1 { | |
62 | compatible = "ibm,uic-460ex","ibm,uic"; | |
63 | interrupt-controller; | |
64 | cell-index = <1>; | |
71f34979 | 65 | dcr-reg = <0x0d0 0x009>; |
8bc4a51d SR |
66 | #address-cells = <0>; |
67 | #size-cells = <0>; | |
68 | #interrupt-cells = <2>; | |
71f34979 | 69 | interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ |
8bc4a51d SR |
70 | interrupt-parent = <&UIC0>; |
71 | }; | |
72 | ||
73 | UIC2: interrupt-controller2 { | |
74 | compatible = "ibm,uic-460ex","ibm,uic"; | |
75 | interrupt-controller; | |
76 | cell-index = <2>; | |
71f34979 | 77 | dcr-reg = <0x0e0 0x009>; |
8bc4a51d SR |
78 | #address-cells = <0>; |
79 | #size-cells = <0>; | |
80 | #interrupt-cells = <2>; | |
71f34979 | 81 | interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ |
8bc4a51d SR |
82 | interrupt-parent = <&UIC0>; |
83 | }; | |
84 | ||
85 | UIC3: interrupt-controller3 { | |
86 | compatible = "ibm,uic-460ex","ibm,uic"; | |
87 | interrupt-controller; | |
88 | cell-index = <3>; | |
71f34979 | 89 | dcr-reg = <0x0f0 0x009>; |
8bc4a51d SR |
90 | #address-cells = <0>; |
91 | #size-cells = <0>; | |
92 | #interrupt-cells = <2>; | |
71f34979 | 93 | interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ |
8bc4a51d SR |
94 | interrupt-parent = <&UIC0>; |
95 | }; | |
96 | ||
97 | SDR0: sdr { | |
98 | compatible = "ibm,sdr-460ex"; | |
71f34979 | 99 | dcr-reg = <0x00e 0x002>; |
8bc4a51d SR |
100 | }; |
101 | ||
102 | CPR0: cpr { | |
103 | compatible = "ibm,cpr-460ex"; | |
71f34979 | 104 | dcr-reg = <0x00c 0x002>; |
8bc4a51d SR |
105 | }; |
106 | ||
107 | plb { | |
108 | compatible = "ibm,plb-460ex", "ibm,plb4"; | |
109 | #address-cells = <2>; | |
110 | #size-cells = <1>; | |
111 | ranges; | |
112 | clock-frequency = <0>; /* Filled in by U-Boot */ | |
113 | ||
114 | SDRAM0: sdram { | |
115 | compatible = "ibm,sdram-460ex", "ibm,sdram-405gp"; | |
71f34979 | 116 | dcr-reg = <0x010 0x002>; |
8bc4a51d SR |
117 | }; |
118 | ||
119 | MAL0: mcmal { | |
120 | compatible = "ibm,mcmal-460ex", "ibm,mcmal2"; | |
71f34979 | 121 | dcr-reg = <0x180 0x062>; |
8bc4a51d | 122 | num-tx-chans = <2>; |
71f34979 | 123 | num-rx-chans = <16>; |
8bc4a51d SR |
124 | #address-cells = <0>; |
125 | #size-cells = <0>; | |
126 | interrupt-parent = <&UIC2>; | |
71f34979 DG |
127 | interrupts = < /*TXEOB*/ 0x6 0x4 |
128 | /*RXEOB*/ 0x7 0x4 | |
129 | /*SERR*/ 0x3 0x4 | |
130 | /*TXDE*/ 0x4 0x4 | |
131 | /*RXDE*/ 0x5 0x4>; | |
8bc4a51d SR |
132 | }; |
133 | ||
134 | POB0: opb { | |
135 | compatible = "ibm,opb-460ex", "ibm,opb"; | |
136 | #address-cells = <1>; | |
137 | #size-cells = <1>; | |
71f34979 | 138 | ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>; |
8bc4a51d SR |
139 | clock-frequency = <0>; /* Filled in by U-Boot */ |
140 | ||
141 | EBC0: ebc { | |
142 | compatible = "ibm,ebc-460ex", "ibm,ebc"; | |
71f34979 | 143 | dcr-reg = <0x012 0x002>; |
8bc4a51d SR |
144 | #address-cells = <2>; |
145 | #size-cells = <1>; | |
146 | clock-frequency = <0>; /* Filled in by U-Boot */ | |
5020231b | 147 | /* ranges property is supplied by U-Boot */ |
71f34979 | 148 | interrupts = <0x6 0x4>; |
8bc4a51d | 149 | interrupt-parent = <&UIC1>; |
5020231b SR |
150 | |
151 | nor_flash@0,0 { | |
152 | compatible = "amd,s29gl512n", "cfi-flash"; | |
153 | bank-width = <2>; | |
71f34979 | 154 | reg = <0x00000000 0x00000000 0x04000000>; |
5020231b SR |
155 | #address-cells = <1>; |
156 | #size-cells = <1>; | |
157 | partition@0 { | |
158 | label = "kernel"; | |
71f34979 | 159 | reg = <0x00000000 0x001e0000>; |
5020231b SR |
160 | }; |
161 | partition@1e0000 { | |
162 | label = "dtb"; | |
71f34979 | 163 | reg = <0x001e0000 0x00020000>; |
5020231b SR |
164 | }; |
165 | partition@200000 { | |
166 | label = "ramdisk"; | |
71f34979 | 167 | reg = <0x00200000 0x01400000>; |
5020231b SR |
168 | }; |
169 | partition@1600000 { | |
170 | label = "jffs2"; | |
71f34979 | 171 | reg = <0x01600000 0x00400000>; |
5020231b SR |
172 | }; |
173 | partition@1a00000 { | |
174 | label = "user"; | |
71f34979 | 175 | reg = <0x01a00000 0x02560000>; |
5020231b SR |
176 | }; |
177 | partition@3f60000 { | |
178 | label = "env"; | |
71f34979 | 179 | reg = <0x03f60000 0x00040000>; |
5020231b SR |
180 | }; |
181 | partition@3fa0000 { | |
182 | label = "u-boot"; | |
71f34979 | 183 | reg = <0x03fa0000 0x00060000>; |
5020231b SR |
184 | }; |
185 | }; | |
8bc4a51d SR |
186 | }; |
187 | ||
188 | UART0: serial@ef600300 { | |
189 | device_type = "serial"; | |
190 | compatible = "ns16550"; | |
71f34979 DG |
191 | reg = <0xef600300 0x00000008>; |
192 | virtual-reg = <0xef600300>; | |
8bc4a51d SR |
193 | clock-frequency = <0>; /* Filled in by U-Boot */ |
194 | current-speed = <0>; /* Filled in by U-Boot */ | |
195 | interrupt-parent = <&UIC1>; | |
71f34979 | 196 | interrupts = <0x1 0x4>; |
8bc4a51d SR |
197 | }; |
198 | ||
199 | UART1: serial@ef600400 { | |
200 | device_type = "serial"; | |
201 | compatible = "ns16550"; | |
71f34979 DG |
202 | reg = <0xef600400 0x00000008>; |
203 | virtual-reg = <0xef600400>; | |
8bc4a51d SR |
204 | clock-frequency = <0>; /* Filled in by U-Boot */ |
205 | current-speed = <0>; /* Filled in by U-Boot */ | |
206 | interrupt-parent = <&UIC0>; | |
71f34979 | 207 | interrupts = <0x1 0x4>; |
8bc4a51d SR |
208 | }; |
209 | ||
210 | UART2: serial@ef600500 { | |
211 | device_type = "serial"; | |
212 | compatible = "ns16550"; | |
71f34979 DG |
213 | reg = <0xef600500 0x00000008>; |
214 | virtual-reg = <0xef600500>; | |
8bc4a51d SR |
215 | clock-frequency = <0>; /* Filled in by U-Boot */ |
216 | current-speed = <0>; /* Filled in by U-Boot */ | |
217 | interrupt-parent = <&UIC1>; | |
71f34979 | 218 | interrupts = <0x1d 0x4>; |
8bc4a51d SR |
219 | }; |
220 | ||
221 | UART3: serial@ef600600 { | |
222 | device_type = "serial"; | |
223 | compatible = "ns16550"; | |
71f34979 DG |
224 | reg = <0xef600600 0x00000008>; |
225 | virtual-reg = <0xef600600>; | |
8bc4a51d SR |
226 | clock-frequency = <0>; /* Filled in by U-Boot */ |
227 | current-speed = <0>; /* Filled in by U-Boot */ | |
228 | interrupt-parent = <&UIC1>; | |
71f34979 | 229 | interrupts = <0x1e 0x4>; |
8bc4a51d SR |
230 | }; |
231 | ||
232 | IIC0: i2c@ef600700 { | |
233 | compatible = "ibm,iic-460ex", "ibm,iic"; | |
71f34979 | 234 | reg = <0xef600700 0x00000014>; |
8bc4a51d | 235 | interrupt-parent = <&UIC0>; |
71f34979 | 236 | interrupts = <0x2 0x4>; |
8bc4a51d SR |
237 | }; |
238 | ||
239 | IIC1: i2c@ef600800 { | |
240 | compatible = "ibm,iic-460ex", "ibm,iic"; | |
71f34979 | 241 | reg = <0xef600800 0x00000014>; |
8bc4a51d | 242 | interrupt-parent = <&UIC0>; |
71f34979 | 243 | interrupts = <0x3 0x4>; |
8bc4a51d SR |
244 | }; |
245 | ||
246 | ZMII0: emac-zmii@ef600d00 { | |
247 | compatible = "ibm,zmii-460ex", "ibm,zmii"; | |
71f34979 | 248 | reg = <0xef600d00 0x0000000c>; |
8bc4a51d SR |
249 | }; |
250 | ||
251 | RGMII0: emac-rgmii@ef601500 { | |
252 | compatible = "ibm,rgmii-460ex", "ibm,rgmii"; | |
71f34979 | 253 | reg = <0xef601500 0x00000008>; |
8bc4a51d SR |
254 | has-mdio; |
255 | }; | |
256 | ||
a6190a84 SR |
257 | TAH0: emac-tah@ef601350 { |
258 | compatible = "ibm,tah-460ex", "ibm,tah"; | |
71f34979 | 259 | reg = <0xef601350 0x00000030>; |
a6190a84 SR |
260 | }; |
261 | ||
262 | TAH1: emac-tah@ef601450 { | |
263 | compatible = "ibm,tah-460ex", "ibm,tah"; | |
71f34979 | 264 | reg = <0xef601450 0x00000030>; |
a6190a84 SR |
265 | }; |
266 | ||
8bc4a51d SR |
267 | EMAC0: ethernet@ef600e00 { |
268 | device_type = "network"; | |
05781ccd | 269 | compatible = "ibm,emac-460ex", "ibm,emac4sync"; |
8bc4a51d | 270 | interrupt-parent = <&EMAC0>; |
71f34979 | 271 | interrupts = <0x0 0x1>; |
8bc4a51d SR |
272 | #interrupt-cells = <1>; |
273 | #address-cells = <0>; | |
274 | #size-cells = <0>; | |
71f34979 DG |
275 | interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4 |
276 | /*Wake*/ 0x1 &UIC2 0x14 0x4>; | |
05781ccd | 277 | reg = <0xef600e00 0x000000c4>; |
8bc4a51d SR |
278 | local-mac-address = [000000000000]; /* Filled in by U-Boot */ |
279 | mal-device = <&MAL0>; | |
280 | mal-tx-channel = <0>; | |
281 | mal-rx-channel = <0>; | |
282 | cell-index = <0>; | |
71f34979 DG |
283 | max-frame-size = <9000>; |
284 | rx-fifo-size = <4096>; | |
285 | tx-fifo-size = <2048>; | |
8bc4a51d | 286 | phy-mode = "rgmii"; |
71f34979 | 287 | phy-map = <0x00000000>; |
8bc4a51d SR |
288 | rgmii-device = <&RGMII0>; |
289 | rgmii-channel = <0>; | |
a6190a84 SR |
290 | tah-device = <&TAH0>; |
291 | tah-channel = <0>; | |
8bc4a51d SR |
292 | has-inverted-stacr-oc; |
293 | has-new-stacr-staopc; | |
294 | }; | |
295 | ||
296 | EMAC1: ethernet@ef600f00 { | |
297 | device_type = "network"; | |
05781ccd | 298 | compatible = "ibm,emac-460ex", "ibm,emac4sync"; |
8bc4a51d | 299 | interrupt-parent = <&EMAC1>; |
71f34979 | 300 | interrupts = <0x0 0x1>; |
8bc4a51d SR |
301 | #interrupt-cells = <1>; |
302 | #address-cells = <0>; | |
303 | #size-cells = <0>; | |
71f34979 DG |
304 | interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4 |
305 | /*Wake*/ 0x1 &UIC2 0x15 0x4>; | |
05781ccd | 306 | reg = <0xef600f00 0x000000c4>; |
8bc4a51d SR |
307 | local-mac-address = [000000000000]; /* Filled in by U-Boot */ |
308 | mal-device = <&MAL0>; | |
309 | mal-tx-channel = <1>; | |
310 | mal-rx-channel = <8>; | |
311 | cell-index = <1>; | |
71f34979 DG |
312 | max-frame-size = <9000>; |
313 | rx-fifo-size = <4096>; | |
314 | tx-fifo-size = <2048>; | |
8bc4a51d | 315 | phy-mode = "rgmii"; |
71f34979 | 316 | phy-map = <0x00000000>; |
8bc4a51d SR |
317 | rgmii-device = <&RGMII0>; |
318 | rgmii-channel = <1>; | |
a6190a84 SR |
319 | tah-device = <&TAH1>; |
320 | tah-channel = <1>; | |
8bc4a51d SR |
321 | has-inverted-stacr-oc; |
322 | has-new-stacr-staopc; | |
a6190a84 | 323 | mdio-device = <&EMAC0>; |
8bc4a51d SR |
324 | }; |
325 | }; | |
326 | ||
327 | PCIX0: pci@c0ec00000 { | |
328 | device_type = "pci"; | |
329 | #interrupt-cells = <1>; | |
330 | #size-cells = <2>; | |
331 | #address-cells = <3>; | |
332 | compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix"; | |
333 | primary; | |
334 | large-inbound-windows; | |
335 | enable-msi-hole; | |
71f34979 DG |
336 | reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */ |
337 | 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ | |
338 | 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */ | |
339 | 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */ | |
340 | 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */ | |
8bc4a51d SR |
341 | |
342 | /* Outbound ranges, one memory and one IO, | |
343 | * later cannot be changed | |
344 | */ | |
71f34979 DG |
345 | ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000 |
346 | 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>; | |
8bc4a51d SR |
347 | |
348 | /* Inbound 2GB range starting at 0 */ | |
71f34979 | 349 | dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; |
8bc4a51d SR |
350 | |
351 | /* This drives busses 0 to 0x3f */ | |
71f34979 | 352 | bus-range = <0x0 0x3f>; |
8bc4a51d SR |
353 | |
354 | /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */ | |
71f34979 DG |
355 | interrupt-map-mask = <0x0 0x0 0x0 0x0>; |
356 | interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >; | |
8bc4a51d SR |
357 | }; |
358 | ||
359 | PCIE0: pciex@d00000000 { | |
360 | device_type = "pci"; | |
361 | #interrupt-cells = <1>; | |
362 | #size-cells = <2>; | |
363 | #address-cells = <3>; | |
364 | compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; | |
365 | primary; | |
71f34979 DG |
366 | port = <0x0>; /* port number */ |
367 | reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */ | |
368 | 0x0000000c 0x08010000 0x00001000>; /* Registers */ | |
369 | dcr-reg = <0x100 0x020>; | |
370 | sdr-base = <0x300>; | |
8bc4a51d SR |
371 | |
372 | /* Outbound ranges, one memory and one IO, | |
373 | * later cannot be changed | |
374 | */ | |
71f34979 DG |
375 | ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 |
376 | 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; | |
8bc4a51d SR |
377 | |
378 | /* Inbound 2GB range starting at 0 */ | |
71f34979 | 379 | dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; |
8bc4a51d SR |
380 | |
381 | /* This drives busses 40 to 0x7f */ | |
71f34979 | 382 | bus-range = <0x40 0x7f>; |
8bc4a51d SR |
383 | |
384 | /* Legacy interrupts (note the weird polarity, the bridge seems | |
385 | * to invert PCIe legacy interrupts). | |
386 | * We are de-swizzling here because the numbers are actually for | |
387 | * port of the root complex virtual P2P bridge. But I want | |
388 | * to avoid putting a node for it in the tree, so the numbers | |
389 | * below are basically de-swizzled numbers. | |
390 | * The real slot is on idsel 0, so the swizzling is 1:1 | |
391 | */ | |
71f34979 | 392 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; |
8bc4a51d | 393 | interrupt-map = < |
71f34979 DG |
394 | 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */ |
395 | 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */ | |
396 | 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */ | |
397 | 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>; | |
8bc4a51d SR |
398 | }; |
399 | ||
400 | PCIE1: pciex@d20000000 { | |
401 | device_type = "pci"; | |
402 | #interrupt-cells = <1>; | |
403 | #size-cells = <2>; | |
404 | #address-cells = <3>; | |
405 | compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; | |
406 | primary; | |
71f34979 DG |
407 | port = <0x1>; /* port number */ |
408 | reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */ | |
409 | 0x0000000c 0x08011000 0x00001000>; /* Registers */ | |
410 | dcr-reg = <0x120 0x020>; | |
411 | sdr-base = <0x340>; | |
8bc4a51d SR |
412 | |
413 | /* Outbound ranges, one memory and one IO, | |
414 | * later cannot be changed | |
415 | */ | |
71f34979 DG |
416 | ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 |
417 | 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; | |
8bc4a51d SR |
418 | |
419 | /* Inbound 2GB range starting at 0 */ | |
71f34979 | 420 | dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; |
8bc4a51d SR |
421 | |
422 | /* This drives busses 80 to 0xbf */ | |
71f34979 | 423 | bus-range = <0x80 0xbf>; |
8bc4a51d SR |
424 | |
425 | /* Legacy interrupts (note the weird polarity, the bridge seems | |
426 | * to invert PCIe legacy interrupts). | |
427 | * We are de-swizzling here because the numbers are actually for | |
428 | * port of the root complex virtual P2P bridge. But I want | |
429 | * to avoid putting a node for it in the tree, so the numbers | |
430 | * below are basically de-swizzled numbers. | |
431 | * The real slot is on idsel 0, so the swizzling is 1:1 | |
432 | */ | |
71f34979 | 433 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; |
8bc4a51d | 434 | interrupt-map = < |
71f34979 DG |
435 | 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */ |
436 | 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */ | |
437 | 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */ | |
438 | 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>; | |
8bc4a51d SR |
439 | }; |
440 | }; | |
441 | }; |