[deliverable/linux.git] / arch / powerpc / boot / dts / gef_ppc9a.dts

/*
 * GE Fanuc PPC9A Device Tree Source
 *
 * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 * Based on: SBS CM6 Device Tree Source
 * Copyright 2007 SBS Technologies GmbH & Co. KG
 * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
 * Copyright 2006 Freescale Semiconductor Inc.
 */

/*
 * Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
 */

/dts-v1/;

/ {
	model = "GEF_PPC9A";
	compatible = "gef,ppc9a";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8641@0 {
			device_type = "cpu";
			reg = <0>;
			d-cache-line-size = <32>;	// 32 bytes
			i-cache-line-size = <32>;	// 32 bytes
			d-cache-size = <32768>;		// L1, 32K
			i-cache-size = <32768>;		// L1, 32K
			timebase-frequency = <0>;	// From uboot
			bus-frequency = <0>;		// From uboot
			clock-frequency = <0>;		// From uboot
		};
		PowerPC,8641@1 {
			device_type = "cpu";
			reg = <1>;
			d-cache-line-size = <32>;	// 32 bytes
			i-cache-line-size = <32>;	// 32 bytes
			d-cache-size = <32768>;		// L1, 32K
			i-cache-size = <32768>;		// L1, 32K
			timebase-frequency = <0>;	// From uboot
			bus-frequency = <0>;		// From uboot
			clock-frequency = <0>;		// From uboot
		};
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x40000000>;	// set by uboot
	};

	localbus@fef05000 {
		#address-cells = <2>;
		#size-cells = <1>;
		compatible = "fsl,mpc8641-localbus", "simple-bus";
		reg = <0xfef05000 0x1000>;
		interrupts = <19 2>;
		interrupt-parent = <&mpic>;

		ranges = <0 0 0xff000000 0x01000000	// 16MB Boot flash
			  1 0 0xe8000000 0x08000000	// Paged Flash 0
			  2 0 0xe0000000 0x08000000	// Paged Flash 1
			  3 0 0xfc100000 0x00020000	// NVRAM
			  4 0 0xfc000000 0x00008000	// FPGA
			  5 0 0xfc008000 0x00008000	// AFIX FPGA
			  6 0 0xfd000000 0x00800000	// IO FPGA (8-bit)
			  7 0 0xfd800000 0x00800000>;	// IO FPGA (32-bit)

		/* flash@0,0 is a mirror of part of the memory in flash@1,0
		flash@0,0 {
			compatible = "gef,ppc9a-firmware-mirror", "cfi-flash";
			reg = <0x0 0x0 0x1000000>;
			bank-width = <4>;
			device-width = <2>;
			#address-cells = <1>;
			#size-cells = <1>;
			partition@0 {
				label = "firmware";
				reg = <0x0 0x1000000>;
				read-only;
			};
		};
		*/

		flash@1,0 {
			compatible = "gef,ppc9a-paged-flash", "cfi-flash";
			reg = <0x1 0x0 0x8000000>;
			bank-width = <4>;
			device-width = <2>;
			#address-cells = <1>;
			#size-cells = <1>;
			partition@0 {
				label = "user";
				reg = <0x0 0x7800000>;
			};
			partition@7800000 {
				label = "firmware";
				reg = <0x7800000 0x800000>;
				read-only;
			};
		};

		fpga@4,0 {
			compatible = "gef,ppc9a-fpga-regs";
			reg = <0x4 0x0 0x40>;
		};

		wdt@4,2000 {
			compatible = "gef,ppc9a-fpga-wdt", "gef,fpga-wdt-1.00",
				"gef,fpga-wdt";
			reg = <0x4 0x2000 0x8>;
			interrupts = <0x1a 0x4>;
			interrupt-parent = <&gef_pic>;
		};
		/* Second watchdog available, driver currently supports one.
		wdt@4,2010 {
			compatible = "gef,ppc9a-fpga-wdt", "gef,fpga-wdt-1.00",
				"gef,fpga-wdt";
			reg = <0x4 0x2010 0x8>;
			interrupts = <0x1b 0x4>;
			interrupt-parent = <&gef_pic>;
		};
		*/
		gef_pic: pic@4,4000 {
			#interrupt-cells = <1>;
			interrupt-controller;
			compatible = "gef,ppc9a-fpga-pic", "gef,fpga-pic-1.00";
			reg = <0x4 0x4000 0x20>;
			interrupts = <0x8
				      0x9>;
			interrupt-parent = <&mpic>;

		};
		gef_gpio: gpio@7,14000 {
			#gpio-cells = <2>;
			compatible = "gef,ppc9a-gpio", "gef,sbc610-gpio";
			reg = <0x7 0x14000 0x24>;
			gpio-controller;
		};
	};

	soc@fef00000 {
		#address-cells = <1>;
		#size-cells = <1>;
		#interrupt-cells = <2>;
		compatible = "fsl,mpc8641-soc", "simple-bus";
		ranges = <0x0 0xfef00000 0x00100000>;
		reg = <0xfef00000 0x100000>;	// CCSRBAR 1M
		bus-frequency = <33333333>;

		i2c1: i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <0x2b 0x2>;
			interrupt-parent = <&mpic>;
			dfsrr;

			hwmon@48 {
				compatible = "national,lm92";
				reg = <0x48>;
			};

			hwmon@4c {
				compatible = "adi,adt7461";
				reg = <0x4c>;
			};

			rtc@51 {
				compatible = "epson,rx8581";
				reg = <0x00000051>;
			};

			eti@6b {
				compatible = "dallas,ds1682";
				reg = <0x6b>;
			};
		};

		i2c2: i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <0x2b 0x2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		dma@21300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
			reg = <0x21300 0x4>;
			ranges = <0x0 0x21100 0x200>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,mpc8641-dma-channel",
					   "fsl,eloplus-dma-channel";
				reg = <0x0 0x80>;
				cell-index = <0>;
				interrupt-parent = <&mpic>;
				interrupts = <20 2>;
			};
			dma-channel@80 {
				compatible = "fsl,mpc8641-dma-channel",
					   "fsl,eloplus-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupt-parent = <&mpic>;
				interrupts = <21 2>;
			};
			dma-channel@100 {
				compatible = "fsl,mpc8641-dma-channel",
					   "fsl,eloplus-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupt-parent = <&mpic>;
				interrupts = <22 2>;
			};
			dma-channel@180 {
				compatible = "fsl,mpc8641-dma-channel",
					   "fsl,eloplus-dma-channel";
				reg = <0x180 0x80>;
				cell-index = <3>;
				interrupt-parent = <&mpic>;
				interrupts = <23 2>;
			};
		};

		enet0: ethernet@24000 {
			#address-cells = <1>;
			#size-cells = <1>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x24000 0x1000>;
			ranges = <0x0 0x24000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy0>;
			phy-connection-type = "gmii";

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-mdio";
				reg = <0x520 0x20>;

				phy0: ethernet-phy@0 {
					interrupt-parent = <&gef_pic>;
					interrupts = <0x9 0x4>;
					reg = <1>;
				};
				phy2: ethernet-phy@2 {
					interrupt-parent = <&gef_pic>;
					interrupts = <0x8 0x4>;
					reg = <3>;
				};
			};
		};

		enet1: ethernet@26000 {
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x26000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <0x1f 0x2 0x20 0x2 0x21 0x2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy2>;
			phy-connection-type = "gmii";
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4500 0x100>;
			clock-frequency = <0>;
			interrupts = <0x2a 0x2>;
			interrupt-parent = <&mpic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4600 0x100>;
			clock-frequency = <0>;
			interrupts = <0x1c 0x2>;
			interrupt-parent = <&mpic>;
		};

		mpic: pic@40000 {
			clock-frequency = <0>;
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x40000 0x40000>;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
		};

		global-utilities@e0000 {
			compatible = "fsl,mpc8641-guts";
			reg = <0xe0000 0x1000>;
			fsl,has-rstcr;
		};
	};

	pci0: pcie@fef08000 {
		compatible = "fsl,mpc8641-pcie";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xfef08000 0x1000>;
		bus-range = <0x0 0xff>;
		ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
			  0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <0x18 0x2>;
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <
			0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
			0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
			0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
			0x0000 0x0 0x0 0x4 &mpic 0x3 0x1
		>;

		pcie@0 {
			reg = <0 0 0 0 0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x02000000 0x0 0x80000000
				  0x02000000 0x0 0x80000000
				  0x0 0x40000000

				  0x01000000 0x0 0x00000000
				  0x01000000 0x0 0x00000000
				  0x0 0x00400000>;
		};
	};
};
Commit	Line	Data
740d36ae MW	1	/*
	2	* GE Fanuc PPC9A Device Tree Source
	3	*
	4	* Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*
	11	* Based on: SBS CM6 Device Tree Source
	12	* Copyright 2007 SBS Technologies GmbH & Co. KG
	13	* And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
	14	* Copyright 2006 Freescale Semiconductor Inc.
	15	*/
	16
	17	/*
	18	* Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
	19	*/
	20
	21	/dts-v1/;
	22
	23	/ {
	24	model = "GEF_PPC9A";
	25	compatible = "gef,ppc9a";
	26	#address-cells = <1>;
	27	#size-cells = <1>;
	28
	29	aliases {
	30	ethernet0 = &enet0;
	31	ethernet1 = &enet1;
	32	serial0 = &serial0;
	33	serial1 = &serial1;
	34	pci0 = &pci0;
	35	};
	36
	37	cpus {
	38	#address-cells = <1>;
	39	#size-cells = <0>;
	40
	41	PowerPC,8641@0 {
	42	device_type = "cpu";
	43	reg = <0>;
	44	d-cache-line-size = <32>; // 32 bytes
	45	i-cache-line-size = <32>; // 32 bytes
	46	d-cache-size = <32768>; // L1, 32K
	47	i-cache-size = <32768>; // L1, 32K
	48	timebase-frequency = <0>; // From uboot
	49	bus-frequency = <0>; // From uboot
	50	clock-frequency = <0>; // From uboot
	51	};
	52	PowerPC,8641@1 {
	53	device_type = "cpu";
	54	reg = <1>;
	55	d-cache-line-size = <32>; // 32 bytes
	56	i-cache-line-size = <32>; // 32 bytes
	57	d-cache-size = <32768>; // L1, 32K
	58	i-cache-size = <32768>; // L1, 32K
	59	timebase-frequency = <0>; // From uboot
	60	bus-frequency = <0>; // From uboot
	61	clock-frequency = <0>; // From uboot
	62	};
	63	};
	64
65	memory {
66	device_type = "memory";
67	reg = <0x0 0x40000000>; // set by uboot
68	};
69
70	localbus@fef05000 {
71	#address-cells = <2>;
72	#size-cells = <1>;
73	compatible = "fsl,mpc8641-localbus", "simple-bus";
74	reg = <0xfef05000 0x1000>;
75	interrupts = <19 2>;
76	interrupt-parent = <&mpic>;
77
78	ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
79	1 0 0xe8000000 0x08000000 // Paged Flash 0
80	2 0 0xe0000000 0x08000000 // Paged Flash 1
81	3 0 0xfc100000 0x00020000 // NVRAM
82	4 0 0xfc000000 0x00008000 // FPGA
83	5 0 0xfc008000 0x00008000 // AFIX FPGA
84	6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
85	7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
86
87	/* flash@0,0 is a mirror of part of the memory in flash@1,0
88	flash@0,0 {
89	compatible = "gef,ppc9a-firmware-mirror", "cfi-flash";
90	reg = <0x0 0x0 0x1000000>;
91	bank-width = <4>;
92	device-width = <2>;
93	#address-cells = <1>;
94	#size-cells = <1>;
95	partition@0 {
96	label = "firmware";
97	reg = <0x0 0x1000000>;
98	read-only;
99	};
100	};
101	*/
102
103	flash@1,0 {
104	compatible = "gef,ppc9a-paged-flash", "cfi-flash";
105	reg = <0x1 0x0 0x8000000>;
106	bank-width = <4>;
107	device-width = <2>;
108	#address-cells = <1>;
109	#size-cells = <1>;
110	partition@0 {
111	label = "user";
112	reg = <0x0 0x7800000>;
113	};
114	partition@7800000 {
115	label = "firmware";
116	reg = <0x7800000 0x800000>;
117	read-only;
118	};
119	};
120
121	fpga@4,0 {
122	compatible = "gef,ppc9a-fpga-regs";
123	reg = <0x4 0x0 0x40>;
124	};
125
126	wdt@4,2000 {
127	compatible = "gef,ppc9a-fpga-wdt", "gef,fpga-wdt-1.00",
128	"gef,fpga-wdt";
129	reg = <0x4 0x2000 0x8>;
130	interrupts = <0x1a 0x4>;
131	interrupt-parent = <&gef_pic>;
132	};
133	/* Second watchdog available, driver currently supports one.
134	wdt@4,2010 {
135	compatible = "gef,ppc9a-fpga-wdt", "gef,fpga-wdt-1.00",
136	"gef,fpga-wdt";
137	reg = <0x4 0x2010 0x8>;
138	interrupts = <0x1b 0x4>;
139	interrupt-parent = <&gef_pic>;
140	};
141	*/
142	gef_pic: pic@4,4000 {
143	#interrupt-cells = <1>;
144	interrupt-controller;
145	compatible = "gef,ppc9a-fpga-pic", "gef,fpga-pic-1.00";
146	reg = <0x4 0x4000 0x20>;
147	interrupts = <0x8
148	0x9>;
149	interrupt-parent = <&mpic>;
150
151	};
152	gef_gpio: gpio@7,14000 {
153	#gpio-cells = <2>;
154	compatible = "gef,ppc9a-gpio", "gef,sbc610-gpio";
155	reg = <0x7 0x14000 0x24>;
156	gpio-controller;
157	};
158	};
159
160	soc@fef00000 {
161	#address-cells = <1>;
162	#size-cells = <1>;
163	#interrupt-cells = <2>;
164	compatible = "fsl,mpc8641-soc", "simple-bus";
165	ranges = <0x0 0xfef00000 0x00100000>;
166	reg = <0xfef00000 0x100000>; // CCSRBAR 1M
167	bus-frequency = <33333333>;
168
169	i2c1: i2c@3000 {
170	#address-cells = <1>;
171	#size-cells = <0>;
172	compatible = "fsl-i2c";
173	reg = <0x3000 0x100>;
174	interrupts = <0x2b 0x2>;
175	interrupt-parent = <&mpic>;
176	dfsrr;
177
178	hwmon@48 {
179	compatible = "national,lm92";
180	reg = <0x48>;
181	};
182
183	hwmon@4c {
184	compatible = "adi,adt7461";
185	reg = <0x4c>;
186	};
187
188	rtc@51 {
189	compatible = "epson,rx8581";
190	reg = <0x00000051>;
191	};
192
193	eti@6b {
194	compatible = "dallas,ds1682";
195	reg = <0x6b>;
196	};
197	};
198
199	i2c2: i2c@3100 {
200	#address-cells = <1>;
201	#size-cells = <0>;
202	compatible = "fsl-i2c";
203	reg = <0x3100 0x100>;
204	interrupts = <0x2b 0x2>;
205	interrupt-parent = <&mpic>;
206	dfsrr;
207	};
208
209	dma@21300 {
210	#address-cells = <1>;
211	#size-cells = <1>;
212	compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
213	reg = <0x21300 0x4>;
214	ranges = <0x0 0x21100 0x200>;
215	cell-index = <0>;
216	dma-channel@0 {
217	compatible = "fsl,mpc8641-dma-channel",
218	"fsl,eloplus-dma-channel";
219	reg = <0x0 0x80>;
220	cell-index = <0>;
221	interrupt-parent = <&mpic>;
222	interrupts = <20 2>;
223	};
224	dma-channel@80 {
225	compatible = "fsl,mpc8641-dma-channel",
226	"fsl,eloplus-dma-channel";
227	reg = <0x80 0x80>;
228	cell-index = <1>;
229	interrupt-parent = <&mpic>;
230	interrupts = <21 2>;
231	};
232	dma-channel@100 {
233	compatible = "fsl,mpc8641-dma-channel",
234	"fsl,eloplus-dma-channel";
235	reg = <0x100 0x80>;
236	cell-index = <2>;
237	interrupt-parent = <&mpic>;
238	interrupts = <22 2>;
239	};
240	dma-channel@180 {
241	compatible = "fsl,mpc8641-dma-channel",
242	"fsl,eloplus-dma-channel";
243	reg = <0x180 0x80>;
244	cell-index = <3>;
245	interrupt-parent = <&mpic>;
246	interrupts = <23 2>;
247	};
248	};
249
740d36ae	250	enet0: ethernet@24000 {
d8bc55fb AV	251	#address-cells = <1>;
d8bc55fb AV	252	#size-cells = <1>;
740d36ae MW	253	device_type = "network";
	254	model = "eTSEC";
	255	compatible = "gianfar";
	256	reg = <0x24000 0x1000>;
d8bc55fb	257	ranges = <0x0 0x24000 0x1000>;
740d36ae MW	258	local-mac-address = [ 00 00 00 00 00 00 ];
	259	interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
	260	interrupt-parent = <&mpic>;
	261	phy-handle = <&phy0>;
	262	phy-connection-type = "gmii";
d8bc55fb AV	263
	264	mdio@520 {
	265	#address-cells = <1>;
	266	#size-cells = <0>;
	267	compatible = "fsl,gianfar-mdio";
	268	reg = <0x520 0x20>;
	269
	270	phy0: ethernet-phy@0 {
	271	interrupt-parent = <&gef_pic>;
	272	interrupts = <0x9 0x4>;
	273	reg = <1>;
	274	};
	275	phy2: ethernet-phy@2 {
	276	interrupt-parent = <&gef_pic>;
	277	interrupts = <0x8 0x4>;
	278	reg = <3>;
	279	};
	280	};
740d36ae MW	281	};
	282
	283	enet1: ethernet@26000 {
	284	device_type = "network";
	285	model = "eTSEC";
	286	compatible = "gianfar";
	287	reg = <0x26000 0x1000>;
	288	local-mac-address = [ 00 00 00 00 00 00 ];
	289	interrupts = <0x1f 0x2 0x20 0x2 0x21 0x2>;
	290	interrupt-parent = <&mpic>;
	291	phy-handle = <&phy2>;
	292	phy-connection-type = "gmii";
	293	};
	294
	295	serial0: serial@4500 {
	296	cell-index = <0>;
	297	device_type = "serial";
	298	compatible = "ns16550";
	299	reg = <0x4500 0x100>;
	300	clock-frequency = <0>;
	301	interrupts = <0x2a 0x2>;
	302	interrupt-parent = <&mpic>;
	303	};
	304
	305	serial1: serial@4600 {
	306	cell-index = <1>;
	307	device_type = "serial";
	308	compatible = "ns16550";
	309	reg = <0x4600 0x100>;
	310	clock-frequency = <0>;
	311	interrupts = <0x1c 0x2>;
	312	interrupt-parent = <&mpic>;
	313	};
	314
	315	mpic: pic@40000 {
	316	clock-frequency = <0>;
	317	interrupt-controller;
	318	#address-cells = <0>;
	319	#interrupt-cells = <2>;
	320	reg = <0x40000 0x40000>;
	321	compatible = "chrp,open-pic";
	322	device_type = "open-pic";
	323	};
	324
	325	global-utilities@e0000 {
	326	compatible = "fsl,mpc8641-guts";
	327	reg = <0xe0000 0x1000>;
	328	fsl,has-rstcr;
	329	};
	330	};
	331
	332	pci0: pcie@fef08000 {
	333	compatible = "fsl,mpc8641-pcie";
	334	device_type = "pci";
	335	#interrupt-cells = <1>;
	336	#size-cells = <2>;
	337	#address-cells = <3>;
	338	reg = <0xfef08000 0x1000>;
	339	bus-range = <0x0 0xff>;
	340	ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
	341	0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
	342	clock-frequency = <33333333>;
	343	interrupt-parent = <&mpic>;
	344	interrupts = <0x18 0x2>;
345	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
346	interrupt-map = <
347	0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
348	0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
349	0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
350	0x0000 0x0 0x0 0x4 &mpic 0x3 0x1
351	>;
352
353	pcie@0 {
354	reg = <0 0 0 0 0>;
355	#size-cells = <2>;
356	#address-cells = <3>;
357	device_type = "pci";
358	ranges = <0x02000000 0x0 0x80000000
359	0x02000000 0x0 0x80000000
360	0x0 0x40000000
361
362	0x01000000 0x0 0x00000000
363	0x01000000 0x0 0x00000000
364	0x0 0x00400000>;
365	};
366	};
367	};