[deliverable/linux.git] / arch / powerpc / boot / dts / katmai.dts

/*
 * Device Tree Source for AMCC Katmai eval board
 *
 * Copyright (c) 2006, 2007 IBM Corp.
 * Benjamin Herrenschmidt <benh@kernel.crashing.org>
 *
 * Copyright (c) 2006, 2007 IBM Corp.
 * Josh Boyer <jwboyer@linux.vnet.ibm.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without
 * any warranty of any kind, whether express or implied.
 */

/dts-v1/;

/ {
	#address-cells = <2>;
	#size-cells = <1>;
	model = "amcc,katmai";
	compatible = "amcc,katmai";
	dcr-parent = <&{/cpus/cpu@0}>;

	aliases {
		ethernet0 = &EMAC0;
		serial0 = &UART0;
		serial1 = &UART1;
		serial2 = &UART2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			model = "PowerPC,440SPe";
			reg = <0x00000000>;
			clock-frequency = <0>; /* Filled in by zImage */
			timebase-frequency = <0>; /* Filled in by zImage */
			i-cache-line-size = <32>;
			d-cache-line-size = <32>;
			i-cache-size = <32768>;
			d-cache-size = <32768>;
			dcr-controller;
			dcr-access-method = "native";
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */
	};

	UIC0: interrupt-controller0 {
		compatible = "ibm,uic-440spe","ibm,uic";
		interrupt-controller;
		cell-index = <0>;
		dcr-reg = <0x0c0 0x009>;
		#address-cells = <0>;
		#size-cells = <0>;
		#interrupt-cells = <2>;
	};

	UIC1: interrupt-controller1 {
		compatible = "ibm,uic-440spe","ibm,uic";
		interrupt-controller;
		cell-index = <1>;
		dcr-reg = <0x0d0 0x009>;
		#address-cells = <0>;
		#size-cells = <0>;
		#interrupt-cells = <2>;
		interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
		interrupt-parent = <&UIC0>;
	};

	UIC2: interrupt-controller2 {
		compatible = "ibm,uic-440spe","ibm,uic";
		interrupt-controller;
		cell-index = <2>;
		dcr-reg = <0x0e0 0x009>;
		#address-cells = <0>;
		#size-cells = <0>;
		#interrupt-cells = <2>;
		interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
		interrupt-parent = <&UIC0>;
	};

	UIC3: interrupt-controller3 {
		compatible = "ibm,uic-440spe","ibm,uic";
		interrupt-controller;
		cell-index = <3>;
		dcr-reg = <0x0f0 0x009>;
		#address-cells = <0>;
		#size-cells = <0>;
		#interrupt-cells = <2>;
		interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
		interrupt-parent = <&UIC0>;
	};

	SDR0: sdr {
		compatible = "ibm,sdr-440spe";
		dcr-reg = <0x00e 0x002>;
	};

	CPR0: cpr {
		compatible = "ibm,cpr-440spe";
		dcr-reg = <0x00c 0x002>;
	};

	plb {
		compatible = "ibm,plb-440spe", "ibm,plb-440gp", "ibm,plb4";
		#address-cells = <2>;
		#size-cells = <1>;
		ranges;
		clock-frequency = <0>; /* Filled in by zImage */

		SDRAM0: sdram {
			compatible = "ibm,sdram-440spe", "ibm,sdram-405gp";
			dcr-reg = <0x010 0x002>;
		};

		MAL0: mcmal {
			compatible = "ibm,mcmal-440spe", "ibm,mcmal2";
			dcr-reg = <0x180 0x062>;
			num-tx-chans = <2>;
			num-rx-chans = <1>;
			interrupt-parent = <&MAL0>;
			interrupts = <0x0 0x1 0x2 0x3 0x4>;
			#interrupt-cells = <1>;
			#address-cells = <0>;
			#size-cells = <0>;
			interrupt-map = </*TXEOB*/ 0x0 &UIC1 0x6 0x4
					 /*RXEOB*/ 0x1 &UIC1 0x7 0x4
					 /*SERR*/  0x2 &UIC1 0x1 0x4
					 /*TXDE*/  0x3 &UIC1 0x2 0x4
					 /*RXDE*/  0x4 &UIC1 0x3 0x4>;
		};

		POB0: opb {
			compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x00000000 0x00000004 0xe0000000 0x20000000>;
			clock-frequency = <0>; /* Filled in by zImage */

			EBC0: ebc {
				compatible = "ibm,ebc-440spe", "ibm,ebc-440gp", "ibm,ebc";
				dcr-reg = <0x012 0x002>;
				#address-cells = <2>;
				#size-cells = <1>;
				clock-frequency = <0>; /* Filled in by zImage */
				interrupts = <0x5 0x1>;
				interrupt-parent = <&UIC1>;
			};

			UART0: serial@10000200 {
				device_type = "serial";
				compatible = "ns16550";
				reg = <0x10000200 0x00000008>;
				virtual-reg = <0xa0000200>;
				clock-frequency = <0>; /* Filled in by zImage */
				current-speed = <115200>;
				interrupt-parent = <&UIC0>;
				interrupts = <0x0 0x4>;
			};

			UART1: serial@10000300 {
				device_type = "serial";
				compatible = "ns16550";
				reg = <0x10000300 0x00000008>;
				virtual-reg = <0xa0000300>;
				clock-frequency = <0>;
				current-speed = <0>;
				interrupt-parent = <&UIC0>;
				interrupts = <0x1 0x4>;
			};


			UART2: serial@10000600 {
				device_type = "serial";
				compatible = "ns16550";
				reg = <0x10000600 0x00000008>;
				virtual-reg = <0xa0000600>;
				clock-frequency = <0>;
				current-speed = <0>;
				interrupt-parent = <&UIC1>;
				interrupts = <0x5 0x4>;
			};

			IIC0: i2c@10000400 {
				compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
				reg = <0x10000400 0x00000014>;
				interrupt-parent = <&UIC0>;
				interrupts = <0x2 0x4>;
			};

			IIC1: i2c@10000500 {
				compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
				reg = <0x10000500 0x00000014>;
				interrupt-parent = <&UIC0>;
				interrupts = <0x3 0x4>;
			};

			EMAC0: ethernet@10000800 {
				linux,network-index = <0x0>;
				device_type = "network";
				compatible = "ibm,emac-440spe", "ibm,emac4";
				interrupt-parent = <&UIC1>;
				interrupts = <0x1c 0x4 0x1d 0x4>;
				reg = <0x10000800 0x00000074>;
				local-mac-address = [000000000000];
				mal-device = <&MAL0>;
				mal-tx-channel = <0>;
				mal-rx-channel = <0>;
				cell-index = <0>;
				max-frame-size = <9000>;
				rx-fifo-size = <4096>;
				tx-fifo-size = <2048>;
				phy-mode = "gmii";
				phy-map = <0x00000000>;
				has-inverted-stacr-oc;
				has-new-stacr-staopc;
			};
		};

		PCIX0: pci@c0ec00000 {
			device_type = "pci";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			compatible = "ibm,plb-pcix-440spe", "ibm,plb-pcix";
			primary;
			large-inbound-windows;
			enable-msi-hole;
			reg = <0x0000000c 0x0ec00000   0x00000008	/* Config space access */
			       0x00000000 0x00000000 0x00000000		/* no IACK cycles */
			       0x0000000c 0x0ed00000   0x00000004   /* Special cycles */
			       0x0000000c 0x0ec80000 0x00000100	/* Internal registers */
			       0x0000000c 0x0ec80100  0x000000fc>;	/* Internal messaging registers */

			/* Outbound ranges, one memory and one IO,
			 * later cannot be changed
			 */
			ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
				  0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;

			/* Inbound 2GB range starting at 0 */
			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;

			/* This drives busses 0 to 0xf */
			bus-range = <0x0 0xf>;

			/*
			 * On Katmai, the following PCI-X interrupts signals
			 * have to be enabled via jumpers (only INTA is
			 * enabled per default):
			 *
			 * INTB: J3: 1-2
			 * INTC: J2: 1-2
			 * INTD: J1: 1-2
			 */
			interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
			interrupt-map = <
				/* IDSEL 1 */
				0x800 0x0 0x0 0x1 &UIC1 0x14 0x8
				0x800 0x0 0x0 0x2 &UIC1 0x13 0x8
				0x800 0x0 0x0 0x3 &UIC1 0x12 0x8
				0x800 0x0 0x0 0x4 &UIC1 0x11 0x8
			>;
		};

		PCIE0: pciex@d00000000 {
			device_type = "pci";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
			primary;
			port = <0x0>; /* port number */
			reg = <0x0000000d 0x00000000 0x20000000	/* Config space access */
			       0x0000000c 0x10000000 0x00001000>;	/* Registers */
			dcr-reg = <0x100 0x020>;
			sdr-base = <0x300>;

			/* Outbound ranges, one memory and one IO,
			 * later cannot be changed
			 */
			ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
				  0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;

			/* Inbound 2GB range starting at 0 */
			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;

			/* This drives busses 10 to 0x1f */
			bus-range = <0x10 0x1f>;

			/* Legacy interrupts (note the weird polarity, the bridge seems
			 * to invert PCIe legacy interrupts).
			 * We are de-swizzling here because the numbers are actually for
			 * port of the root complex virtual P2P bridge. But I want
			 * to avoid putting a node for it in the tree, so the numbers
			 * below are basically de-swizzled numbers.
			 * The real slot is on idsel 0, so the swizzling is 1:1
			 */
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <
				0x0 0x0 0x0 0x1 &UIC3 0x0 0x4 /* swizzled int A */
				0x0 0x0 0x0 0x2 &UIC3 0x1 0x4 /* swizzled int B */
				0x0 0x0 0x0 0x3 &UIC3 0x2 0x4 /* swizzled int C */
				0x0 0x0 0x0 0x4 &UIC3 0x3 0x4 /* swizzled int D */>;
		};

		PCIE1: pciex@d20000000 {
			device_type = "pci";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
			primary;
			port = <0x1>; /* port number */
			reg = <0x0000000d 0x20000000 0x20000000	/* Config space access */
			       0x0000000c 0x10001000 0x00001000>;	/* Registers */
			dcr-reg = <0x120 0x020>;
			sdr-base = <0x340>;

			/* Outbound ranges, one memory and one IO,
			 * later cannot be changed
			 */
			ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
				  0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;

			/* Inbound 2GB range starting at 0 */
			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;

			/* This drives busses 10 to 0x1f */
			bus-range = <0x20 0x2f>;

			/* Legacy interrupts (note the weird polarity, the bridge seems
			 * to invert PCIe legacy interrupts).
			 * We are de-swizzling here because the numbers are actually for
			 * port of the root complex virtual P2P bridge. But I want
			 * to avoid putting a node for it in the tree, so the numbers
			 * below are basically de-swizzled numbers.
			 * The real slot is on idsel 0, so the swizzling is 1:1
			 */
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <
				0x0 0x0 0x0 0x1 &UIC3 0x4 0x4 /* swizzled int A */
				0x0 0x0 0x0 0x2 &UIC3 0x5 0x4 /* swizzled int B */
				0x0 0x0 0x0 0x3 &UIC3 0x6 0x4 /* swizzled int C */
				0x0 0x0 0x0 0x4 &UIC3 0x7 0x4 /* swizzled int D */>;
		};

		PCIE2: pciex@d40000000 {
			device_type = "pci";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
			primary;
			port = <0x2>; /* port number */
			reg = <0x0000000d 0x40000000 0x20000000	/* Config space access */
			       0x0000000c 0x10002000 0x00001000>;	/* Registers */
			dcr-reg = <0x140 0x020>;
			sdr-base = <0x370>;

			/* Outbound ranges, one memory and one IO,
			 * later cannot be changed
			 */
			ranges = <0x02000000 0x00000000 0x80000000 0x0000000f 0x00000000 0x00000000 0x80000000
				  0x01000000 0x00000000 0x00000000 0x0000000f 0x80020000 0x00000000 0x00010000>;

			/* Inbound 2GB range starting at 0 */
			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;

			/* This drives busses 10 to 0x1f */
			bus-range = <0x30 0x3f>;

			/* Legacy interrupts (note the weird polarity, the bridge seems
			 * to invert PCIe legacy interrupts).
			 * We are de-swizzling here because the numbers are actually for
			 * port of the root complex virtual P2P bridge. But I want
			 * to avoid putting a node for it in the tree, so the numbers
			 * below are basically de-swizzled numbers.
			 * The real slot is on idsel 0, so the swizzling is 1:1
			 */
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <
				0x0 0x0 0x0 0x1 &UIC3 0x8 0x4 /* swizzled int A */
				0x0 0x0 0x0 0x2 &UIC3 0x9 0x4 /* swizzled int B */
				0x0 0x0 0x0 0x3 &UIC3 0xa 0x4 /* swizzled int C */
				0x0 0x0 0x0 0x4 &UIC3 0xb 0x4 /* swizzled int D */>;
		};
	};

	chosen {
		linux,stdout-path = "/plb/opb/serial@10000200";
	};
};
Commit	Line	Data
3de9c9cd BH	1	/*
	2	* Device Tree Source for AMCC Katmai eval board
	3	*
	4	* Copyright (c) 2006, 2007 IBM Corp.
	5	* Benjamin Herrenschmidt <benh@kernel.crashing.org>
	6	*
	7	* Copyright (c) 2006, 2007 IBM Corp.
	8	* Josh Boyer <jwboyer@linux.vnet.ibm.com>
	9	*
	10	* This file is licensed under the terms of the GNU General Public
	11	* License version 2. This program is licensed "as is" without
	12	* any warranty of any kind, whether express or implied.
	13	*/
	14
71f34979 DG	15	/dts-v1/;
71f34979 DG	16
3de9c9cd BH	17	/ {
	18	#address-cells = <2>;
	19	#size-cells = <1>;
	20	model = "amcc,katmai";
	21	compatible = "amcc,katmai";
71f34979	22	dcr-parent = <&{/cpus/cpu@0}>;
3de9c9cd	23
8aaed98c SR	24	aliases {
	25	ethernet0 = &EMAC0;
	26	serial0 = &UART0;
	27	serial1 = &UART1;
	28	serial2 = &UART2;
	29	};
	30
3de9c9cd BH	31	cpus {
	32	#address-cells = <1>;
	33	#size-cells = <0>;
	34
72fda114	35	cpu@0 {
3de9c9cd	36	device_type = "cpu";
72fda114	37	model = "PowerPC,440SPe";
71f34979	38	reg = <0x00000000>;
3de9c9cd BH	39	clock-frequency = <0>; /* Filled in by zImage */
3de9c9cd BH	40	timebase-frequency = <0>; /* Filled in by zImage */
71f34979 DG	41	i-cache-line-size = <32>;
	42	d-cache-line-size = <32>;
	43	i-cache-size = <32768>;
	44	d-cache-size = <32768>;
3de9c9cd BH	45	dcr-controller;
	46	dcr-access-method = "native";
	47	};
	48	};
	49
	50	memory {
	51	device_type = "memory";
71f34979	52	reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */
3de9c9cd BH	53	};
	54
	55	UIC0: interrupt-controller0 {
	56	compatible = "ibm,uic-440spe","ibm,uic";
	57	interrupt-controller;
	58	cell-index = <0>;
71f34979	59	dcr-reg = <0x0c0 0x009>;
3de9c9cd BH	60	#address-cells = <0>;
	61	#size-cells = <0>;
	62	#interrupt-cells = <2>;
	63	};
	64
	65	UIC1: interrupt-controller1 {
	66	compatible = "ibm,uic-440spe","ibm,uic";
	67	interrupt-controller;
	68	cell-index = <1>;
71f34979	69	dcr-reg = <0x0d0 0x009>;
3de9c9cd BH	70	#address-cells = <0>;
	71	#size-cells = <0>;
	72	#interrupt-cells = <2>;
71f34979	73	interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
3de9c9cd BH	74	interrupt-parent = <&UIC0>;
	75	};
	76
	77	UIC2: interrupt-controller2 {
	78	compatible = "ibm,uic-440spe","ibm,uic";
	79	interrupt-controller;
	80	cell-index = <2>;
71f34979	81	dcr-reg = <0x0e0 0x009>;
3de9c9cd BH	82	#address-cells = <0>;
	83	#size-cells = <0>;
	84	#interrupt-cells = <2>;
71f34979	85	interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
3de9c9cd BH	86	interrupt-parent = <&UIC0>;
	87	};
	88
	89	UIC3: interrupt-controller3 {
	90	compatible = "ibm,uic-440spe","ibm,uic";
	91	interrupt-controller;
	92	cell-index = <3>;
71f34979	93	dcr-reg = <0x0f0 0x009>;
3de9c9cd BH	94	#address-cells = <0>;
	95	#size-cells = <0>;
	96	#interrupt-cells = <2>;
71f34979	97	interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
3de9c9cd BH	98	interrupt-parent = <&UIC0>;
	99	};
	100
	101	SDR0: sdr {
	102	compatible = "ibm,sdr-440spe";
71f34979	103	dcr-reg = <0x00e 0x002>;
3de9c9cd BH	104	};
	105
	106	CPR0: cpr {
	107	compatible = "ibm,cpr-440spe";
71f34979	108	dcr-reg = <0x00c 0x002>;
3de9c9cd BH	109	};
	110
	111	plb {
	112	compatible = "ibm,plb-440spe", "ibm,plb-440gp", "ibm,plb4";
	113	#address-cells = <2>;
	114	#size-cells = <1>;
	115	ranges;
	116	clock-frequency = <0>; /* Filled in by zImage */
	117
	118	SDRAM0: sdram {
	119	compatible = "ibm,sdram-440spe", "ibm,sdram-405gp";
71f34979	120	dcr-reg = <0x010 0x002>;
3de9c9cd BH	121	};
	122
	123	MAL0: mcmal {
	124	compatible = "ibm,mcmal-440spe", "ibm,mcmal2";
71f34979	125	dcr-reg = <0x180 0x062>;
3de9c9cd BH	126	num-tx-chans = <2>;
	127	num-rx-chans = <1>;
	128	interrupt-parent = <&MAL0>;
71f34979	129	interrupts = <0x0 0x1 0x2 0x3 0x4>;
3de9c9cd BH	130	#interrupt-cells = <1>;
	131	#address-cells = <0>;
	132	#size-cells = <0>;
71f34979 DG	133	interrupt-map = </TXEOB/ 0x0 &UIC1 0x6 0x4
	134	/RXEOB/ 0x1 &UIC1 0x7 0x4
	135	/SERR/ 0x2 &UIC1 0x1 0x4
	136	/TXDE/ 0x3 &UIC1 0x2 0x4
	137	/RXDE/ 0x4 &UIC1 0x3 0x4>;
3de9c9cd BH	138	};
	139
	140	POB0: opb {
3db3ba03	141	compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb";
3de9c9cd BH	142	#address-cells = <1>;
3de9c9cd BH	143	#size-cells = <1>;
71f34979	144	ranges = <0x00000000 0x00000004 0xe0000000 0x20000000>;
3db3ba03	145	clock-frequency = <0>; /* Filled in by zImage */
3de9c9cd BH	146
	147	EBC0: ebc {
	148	compatible = "ibm,ebc-440spe", "ibm,ebc-440gp", "ibm,ebc";
71f34979	149	dcr-reg = <0x012 0x002>;
3de9c9cd BH	150	#address-cells = <2>;
	151	#size-cells = <1>;
	152	clock-frequency = <0>; /* Filled in by zImage */
71f34979	153	interrupts = <0x5 0x1>;
3de9c9cd BH	154	interrupt-parent = <&UIC1>;
	155	};
	156
	157	UART0: serial@10000200 {
3db3ba03 SR	158	device_type = "serial";
3db3ba03 SR	159	compatible = "ns16550";
71f34979 DG	160	reg = <0x10000200 0x00000008>;
71f34979 DG	161	virtual-reg = <0xa0000200>;
3db3ba03	162	clock-frequency = <0>; /* Filled in by zImage */
71f34979	163	current-speed = <115200>;
3db3ba03	164	interrupt-parent = <&UIC0>;
71f34979	165	interrupts = <0x0 0x4>;
3db3ba03	166	};
3de9c9cd BH	167
3de9c9cd BH	168	UART1: serial@10000300 {
3db3ba03 SR	169	device_type = "serial";
3db3ba03 SR	170	compatible = "ns16550";
71f34979 DG	171	reg = <0x10000300 0x00000008>;
71f34979 DG	172	virtual-reg = <0xa0000300>;
3db3ba03 SR	173	clock-frequency = <0>;
	174	current-speed = <0>;
	175	interrupt-parent = <&UIC0>;
71f34979	176	interrupts = <0x1 0x4>;
3db3ba03	177	};
3de9c9cd BH	178
	179
	180	UART2: serial@10000600 {
3db3ba03 SR	181	device_type = "serial";
3db3ba03 SR	182	compatible = "ns16550";
71f34979 DG	183	reg = <0x10000600 0x00000008>;
71f34979 DG	184	virtual-reg = <0xa0000600>;
3db3ba03 SR	185	clock-frequency = <0>;
	186	current-speed = <0>;
	187	interrupt-parent = <&UIC1>;
71f34979	188	interrupts = <0x5 0x4>;
3db3ba03	189	};
3de9c9cd BH	190
3de9c9cd BH	191	IIC0: i2c@10000400 {
3de9c9cd	192	compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
71f34979	193	reg = <0x10000400 0x00000014>;
3de9c9cd	194	interrupt-parent = <&UIC0>;
71f34979	195	interrupts = <0x2 0x4>;
3de9c9cd BH	196	};
	197
	198	IIC1: i2c@10000500 {
3de9c9cd	199	compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
71f34979	200	reg = <0x10000500 0x00000014>;
3de9c9cd	201	interrupt-parent = <&UIC0>;
71f34979	202	interrupts = <0x3 0x4>;
3de9c9cd BH	203	};
	204
	205	EMAC0: ethernet@10000800 {
71f34979	206	linux,network-index = <0x0>;
3de9c9cd BH	207	device_type = "network";
	208	compatible = "ibm,emac-440spe", "ibm,emac4";
	209	interrupt-parent = <&UIC1>;
71f34979	210	interrupts = <0x1c 0x4 0x1d 0x4>;
05781ccd	211	reg = <0x10000800 0x00000074>;
3de9c9cd BH	212	local-mac-address = [000000000000];
	213	mal-device = <&MAL0>;
	214	mal-tx-channel = <0>;
	215	mal-rx-channel = <0>;
	216	cell-index = <0>;
71f34979 DG	217	max-frame-size = <9000>;
	218	rx-fifo-size = <4096>;
	219	tx-fifo-size = <2048>;
3de9c9cd	220	phy-mode = "gmii";
71f34979	221	phy-map = <0x00000000>;
3de9c9cd BH	222	has-inverted-stacr-oc;
	223	has-new-stacr-staopc;
	224	};
	225	};
	226
	227	PCIX0: pci@c0ec00000 {
	228	device_type = "pci";
	229	#interrupt-cells = <1>;
	230	#size-cells = <2>;
	231	#address-cells = <3>;
	232	compatible = "ibm,plb-pcix-440spe", "ibm,plb-pcix";
	233	primary;
	234	large-inbound-windows;
	235	enable-msi-hole;
71f34979 DG	236	reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
	237	0x00000000 0x00000000 0x00000000 /* no IACK cycles */
	238	0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
	239	0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
	240	0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
3de9c9cd BH	241
	242	/* Outbound ranges, one memory and one IO,
	243	* later cannot be changed
	244	*/
71f34979 DG	245	ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
71f34979 DG	246	0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
3de9c9cd BH	247
3de9c9cd BH	248	/* Inbound 2GB range starting at 0 */
71f34979	249	dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
3de9c9cd BH	250
3de9c9cd BH	251	/* This drives busses 0 to 0xf */
71f34979	252	bus-range = <0x0 0xf>;
3de9c9cd BH	253
	254	/*
	255	* On Katmai, the following PCI-X interrupts signals
	256	* have to be enabled via jumpers (only INTA is
	257	* enabled per default):
	258	*
	259	* INTB: J3: 1-2
	260	* INTC: J2: 1-2
	261	* INTD: J1: 1-2
	262	*/
71f34979	263	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
3de9c9cd BH	264	interrupt-map = <
3de9c9cd BH	265	/* IDSEL 1 */
71f34979 DG	266	0x800 0x0 0x0 0x1 &UIC1 0x14 0x8
	267	0x800 0x0 0x0 0x2 &UIC1 0x13 0x8
	268	0x800 0x0 0x0 0x3 &UIC1 0x12 0x8
	269	0x800 0x0 0x0 0x4 &UIC1 0x11 0x8
3de9c9cd BH	270	>;
	271	};
	272
	273	PCIE0: pciex@d00000000 {
	274	device_type = "pci";
	275	#interrupt-cells = <1>;
	276	#size-cells = <2>;
	277	#address-cells = <3>;
accf5ef2	278	compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
3de9c9cd	279	primary;
71f34979 DG	280	port = <0x0>; /* port number */
	281	reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
	282	0x0000000c 0x10000000 0x00001000>; /* Registers */
	283	dcr-reg = <0x100 0x020>;
	284	sdr-base = <0x300>;
3de9c9cd BH	285
	286	/* Outbound ranges, one memory and one IO,
	287	* later cannot be changed
	288	*/
71f34979 DG	289	ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
71f34979 DG	290	0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
3de9c9cd BH	291
3de9c9cd BH	292	/* Inbound 2GB range starting at 0 */
71f34979	293	dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
3de9c9cd BH	294
3de9c9cd BH	295	/* This drives busses 10 to 0x1f */
71f34979	296	bus-range = <0x10 0x1f>;
3de9c9cd BH	297
	298	/* Legacy interrupts (note the weird polarity, the bridge seems
	299	* to invert PCIe legacy interrupts).
	300	* We are de-swizzling here because the numbers are actually for
	301	* port of the root complex virtual P2P bridge. But I want
	302	* to avoid putting a node for it in the tree, so the numbers
	303	* below are basically de-swizzled numbers.
	304	* The real slot is on idsel 0, so the swizzling is 1:1
	305	*/
71f34979	306	interrupt-map-mask = <0x0 0x0 0x0 0x7>;
3de9c9cd	307	interrupt-map = <
71f34979 DG	308	0x0 0x0 0x0 0x1 &UIC3 0x0 0x4 /* swizzled int A */
	309	0x0 0x0 0x0 0x2 &UIC3 0x1 0x4 /* swizzled int B */
	310	0x0 0x0 0x0 0x3 &UIC3 0x2 0x4 /* swizzled int C */
	311	0x0 0x0 0x0 0x4 &UIC3 0x3 0x4 /* swizzled int D */>;
3de9c9cd BH	312	};
	313
	314	PCIE1: pciex@d20000000 {
	315	device_type = "pci";
	316	#interrupt-cells = <1>;
	317	#size-cells = <2>;
	318	#address-cells = <3>;
accf5ef2	319	compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
3de9c9cd	320	primary;
71f34979 DG	321	port = <0x1>; /* port number */
	322	reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
	323	0x0000000c 0x10001000 0x00001000>; /* Registers */
	324	dcr-reg = <0x120 0x020>;
	325	sdr-base = <0x340>;
3de9c9cd BH	326
	327	/* Outbound ranges, one memory and one IO,
	328	* later cannot be changed
	329	*/
71f34979 DG	330	ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
71f34979 DG	331	0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
3de9c9cd BH	332
3de9c9cd BH	333	/* Inbound 2GB range starting at 0 */
71f34979	334	dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
3de9c9cd BH	335
3de9c9cd BH	336	/* This drives busses 10 to 0x1f */
71f34979	337	bus-range = <0x20 0x2f>;
3de9c9cd BH	338
	339	/* Legacy interrupts (note the weird polarity, the bridge seems
	340	* to invert PCIe legacy interrupts).
	341	* We are de-swizzling here because the numbers are actually for
	342	* port of the root complex virtual P2P bridge. But I want
	343	* to avoid putting a node for it in the tree, so the numbers
	344	* below are basically de-swizzled numbers.
	345	* The real slot is on idsel 0, so the swizzling is 1:1
	346	*/
71f34979	347	interrupt-map-mask = <0x0 0x0 0x0 0x7>;
3de9c9cd	348	interrupt-map = <
71f34979 DG	349	0x0 0x0 0x0 0x1 &UIC3 0x4 0x4 /* swizzled int A */
	350	0x0 0x0 0x0 0x2 &UIC3 0x5 0x4 /* swizzled int B */
	351	0x0 0x0 0x0 0x3 &UIC3 0x6 0x4 /* swizzled int C */
	352	0x0 0x0 0x0 0x4 &UIC3 0x7 0x4 /* swizzled int D */>;
3de9c9cd BH	353	};
	354
	355	PCIE2: pciex@d40000000 {
	356	device_type = "pci";
	357	#interrupt-cells = <1>;
	358	#size-cells = <2>;
	359	#address-cells = <3>;
accf5ef2	360	compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
3de9c9cd	361	primary;
71f34979 DG	362	port = <0x2>; /* port number */
	363	reg = <0x0000000d 0x40000000 0x20000000 /* Config space access */
	364	0x0000000c 0x10002000 0x00001000>; /* Registers */
	365	dcr-reg = <0x140 0x020>;
	366	sdr-base = <0x370>;
3de9c9cd BH	367
	368	/* Outbound ranges, one memory and one IO,
	369	* later cannot be changed
	370	*/
71f34979 DG	371	ranges = <0x02000000 0x00000000 0x80000000 0x0000000f 0x00000000 0x00000000 0x80000000
71f34979 DG	372	0x01000000 0x00000000 0x00000000 0x0000000f 0x80020000 0x00000000 0x00010000>;
3de9c9cd BH	373
3de9c9cd BH	374	/* Inbound 2GB range starting at 0 */
71f34979	375	dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
3de9c9cd BH	376
3de9c9cd BH	377	/* This drives busses 10 to 0x1f */
71f34979	378	bus-range = <0x30 0x3f>;
3de9c9cd BH	379
	380	/* Legacy interrupts (note the weird polarity, the bridge seems
	381	* to invert PCIe legacy interrupts).
	382	* We are de-swizzling here because the numbers are actually for
	383	* port of the root complex virtual P2P bridge. But I want
	384	* to avoid putting a node for it in the tree, so the numbers
	385	* below are basically de-swizzled numbers.
	386	* The real slot is on idsel 0, so the swizzling is 1:1
	387	*/
71f34979	388	interrupt-map-mask = <0x0 0x0 0x0 0x7>;
3de9c9cd	389	interrupt-map = <
71f34979 DG	390	0x0 0x0 0x0 0x1 &UIC3 0x8 0x4 /* swizzled int A */
	391	0x0 0x0 0x0 0x2 &UIC3 0x9 0x4 /* swizzled int B */
	392	0x0 0x0 0x0 0x3 &UIC3 0xa 0x4 /* swizzled int C */
	393	0x0 0x0 0x0 0x4 &UIC3 0xb 0x4 /* swizzled int D */>;
3de9c9cd BH	394	};
	395	};
	396
	397	chosen {
	398	linux,stdout-path = "/plb/opb/serial@10000200";
	399	};
	400	};