[deliverable/linux.git] / arch / powerpc / boot / dts / mpc5125twr.dts

/*
 * STx/Freescale ADS5125 MPC5125 silicon
 *
 * Copyright (C) 2009 Freescale Semiconductor Inc. All rights reserved.
 *
 * Reworked by Matteo Facchinetti (engineering@sirius-es.it)
 * Copyright (C) 2013 Sirius Electronic Systems
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <dt-bindings/clock/mpc512x-clock.h>

/dts-v1/;

/ {
	model = "mpc5125twr"; // In BSP "mpc5125ads"
	compatible = "fsl,mpc5125ads", "fsl,mpc5125";
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&ipic>;

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		ethernet0 = &eth0;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,5125@0 {
			device_type = "cpu";
			reg = <0>;
			d-cache-line-size = <0x20>;	// 32 bytes
			i-cache-line-size = <0x20>;	// 32 bytes
			d-cache-size = <0x8000>;	// L1, 32K
			i-cache-size = <0x8000>;	// L1, 32K
			timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
			bus-frequency = <198000000>;	// 198 MHz csb bus
			clock-frequency = <396000000>;	// 396 MHz ppc core
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x10000000>;	// 256MB at 0
	};

	sram@30000000 {
		compatible = "fsl,mpc5121-sram";
		reg = <0x30000000 0x08000>;		// 32K at 0x30000000
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <0>;

		osc: osc {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <33000000>;
		};
	};

	soc@80000000 {
		compatible = "fsl,mpc5121-immr";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x80000000 0x400000>;
		reg = <0x80000000 0x400000>;
		bus-frequency = <66000000>;	// 66 MHz ips bus

		// IPIC
		// interrupts cell = <intr #, sense>
		// sense values match linux IORESOURCE_IRQ_* defines:
		// sense == 8: Level, low assertion
		// sense == 2: Edge, high-to-low change
		//
		ipic: interrupt-controller@c00 {
			compatible = "fsl,mpc5121-ipic", "fsl,ipic";
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0xc00 0x100>;
		};

		rtc@a00 {	// Real time clock
			compatible = "fsl,mpc5121-rtc";
			reg = <0xa00 0x100>;
			interrupts = <79 0x8 80 0x8>;
		};

		reset@e00 {	// Reset module
			compatible = "fsl,mpc5125-reset";
			reg = <0xe00 0x100>;
		};

		clks: clock@f00 {	// Clock control
			compatible = "fsl,mpc5121-clock";
			reg = <0xf00 0x100>;
			#clock-cells = <1>;
			clocks = <&osc>;
			clock-names = "osc";
		};

		pmc@1000{  // Power Management Controller
			compatible = "fsl,mpc5121-pmc";
			reg = <0x1000 0x100>;
			interrupts = <83 0x2>;
		};

		gpio0: gpio@1100 {
			compatible = "fsl,mpc5125-gpio";
			reg = <0x1100 0x080>;
			interrupts = <78 0x8>;
		};

		gpio1: gpio@1180 {
			compatible = "fsl,mpc5125-gpio";
			reg = <0x1180 0x080>;
			interrupts = <86 0x8>;
		};

		can@1300 { // CAN rev.2
			compatible = "fsl,mpc5121-mscan";
			interrupts = <12 0x8>;
			reg = <0x1300 0x80>;
			clocks = <&clks MPC512x_CLK_BDLC>,
				 <&clks MPC512x_CLK_IPS>,
				 <&clks MPC512x_CLK_SYS>,
				 <&clks MPC512x_CLK_REF>,
				 <&clks MPC512x_CLK_MSCAN0_MCLK>;
			clock-names = "ipg", "ips", "sys", "ref", "mclk";
		};

		can@1380 {
			compatible = "fsl,mpc5121-mscan";
			interrupts = <13 0x8>;
			reg = <0x1380 0x80>;
			clocks = <&clks MPC512x_CLK_BDLC>,
				 <&clks MPC512x_CLK_IPS>,
				 <&clks MPC512x_CLK_SYS>,
				 <&clks MPC512x_CLK_REF>,
				 <&clks MPC512x_CLK_MSCAN1_MCLK>;
			clock-names = "ipg", "ips", "sys", "ref", "mclk";
		};

		sdhc@1500 {
			compatible = "fsl,mpc5121-sdhc";
			interrupts = <8 0x8>;
			reg = <0x1500 0x100>;
			clocks = <&clks MPC512x_CLK_IPS>,
				 <&clks MPC512x_CLK_SDHC>;
			clock-names = "ipg", "per";
		};

		i2c@1700 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,mpc5121-i2c", "fsl-i2c";
			reg = <0x1700 0x20>;
			interrupts = <0x9 0x8>;
			clocks = <&clks MPC512x_CLK_I2C>;
			clock-names = "ipg";
		};

		i2c@1720 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,mpc5121-i2c", "fsl-i2c";
			reg = <0x1720 0x20>;
			interrupts = <0xa 0x8>;
			clocks = <&clks MPC512x_CLK_I2C>;
			clock-names = "ipg";
		};

		i2c@1740 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,mpc5121-i2c", "fsl-i2c";
			reg = <0x1740 0x20>;
			interrupts = <0xb 0x8>;
			clocks = <&clks MPC512x_CLK_I2C>;
			clock-names = "ipg";
		};

		i2ccontrol@1760 {
			compatible = "fsl,mpc5121-i2c-ctrl";
			reg = <0x1760 0x8>;
		};

		diu@2100 {
			compatible = "fsl,mpc5121-diu";
			reg = <0x2100 0x100>;
			interrupts = <64 0x8>;
			clocks = <&clks MPC512x_CLK_DIU>;
			clock-names = "ipg";
		};

		mdio@2800 {
			compatible = "fsl,mpc5121-fec-mdio";
			reg = <0x2800 0x800>;
			#address-cells = <1>;
			#size-cells = <0>;
			phy0: ethernet-phy@0 {
				reg = <1>;
			};
		};

		eth0: ethernet@2800 {
			compatible = "fsl,mpc5125-fec";
			reg = <0x2800 0x800>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <4 0x8>;
			phy-handle = < &phy0 >;
			phy-connection-type = "rmii";
			clocks = <&clks MPC512x_CLK_FEC>;
			clock-names = "per";
		};

		// IO control
		ioctl@a000 {
			compatible = "fsl,mpc5125-ioctl";
			reg = <0xA000 0x1000>;
		};

		// disable USB1 port
		// TODO:
		// correct pinmux config and fix USB3320 ulpi dependency
		// before re-enabling it
		usb@3000 {
			compatible = "fsl,mpc5121-usb2-dr";
			reg = <0x3000 0x400>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <43 0x8>;
			dr_mode = "host";
			phy_type = "ulpi";
			clocks = <&clks MPC512x_CLK_USB1>;
			clock-names = "ipg";
			status = "disabled";
		};

		// 5125 PSCs are not 52xx or 5121 PSC compatible
		// PSC1 uart0 aka ttyPSC0
		serial@11100 {
			compatible = "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc";
			reg = <0x11100 0x100>;
			interrupts = <40 0x8>;
			fsl,rx-fifo-size = <16>;
			fsl,tx-fifo-size = <16>;
			clocks = <&clks MPC512x_CLK_PSC1>,
				 <&clks MPC512x_CLK_PSC1_MCLK>;
			clock-names = "ipg", "mclk";
		};

		// PSC9 uart1 aka ttyPSC1
		serial@11900 {
			compatible = "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc";
			reg = <0x11900 0x100>;
			interrupts = <40 0x8>;
			fsl,rx-fifo-size = <16>;
			fsl,tx-fifo-size = <16>;
			clocks = <&clks MPC512x_CLK_PSC9>,
				 <&clks MPC512x_CLK_PSC9_MCLK>;
			clock-names = "ipg", "mclk";
		};

		pscfifo@11f00 {
			compatible = "fsl,mpc5121-psc-fifo";
			reg = <0x11f00 0x100>;
			interrupts = <40 0x8>;
			clocks = <&clks MPC512x_CLK_PSC_FIFO>;
			clock-names = "ipg";
		};

		dma@14000 {
			compatible = "fsl,mpc5121-dma"; // BSP name: "mpc512x-dma2"
			reg = <0x14000 0x1800>;
			interrupts = <65 0x8>;
		};
	};
};
Commit	Line	Data
a9b6aae4 MF	1	/*
	2	* STx/Freescale ADS5125 MPC5125 silicon
	3	*
	4	* Copyright (C) 2009 Freescale Semiconductor Inc. All rights reserved.
	5	*
	6	* Reworked by Matteo Facchinetti (engineering@sirius-es.it)
	7	* Copyright (C) 2013 Sirius Electronic Systems
	8	*
	9	* This program is free software; you can redistribute it and/or modify it
	10	* under the terms of the GNU General Public License as published by the
	11	* Free Software Foundation; either version 2 of the License, or (at your
	12	* option) any later version.
	13	*/
	14
bc750594 GS	15	#include <dt-bindings/clock/mpc512x-clock.h>
bc750594 GS	16
a9b6aae4 MF	17	/dts-v1/;
	18
	19	/ {
	20	model = "mpc5125twr"; // In BSP "mpc5125ads"
	21	compatible = "fsl,mpc5125ads", "fsl,mpc5125";
	22	#address-cells = <1>;
	23	#size-cells = <1>;
	24	interrupt-parent = <&ipic>;
	25
	26	aliases {
	27	gpio0 = &gpio0;
	28	gpio1 = &gpio1;
	29	ethernet0 = &eth0;
	30	};
	31
	32	cpus {
	33	#address-cells = <1>;
	34	#size-cells = <0>;
	35
	36	PowerPC,5125@0 {
	37	device_type = "cpu";
	38	reg = <0>;
	39	d-cache-line-size = <0x20>; // 32 bytes
	40	i-cache-line-size = <0x20>; // 32 bytes
	41	d-cache-size = <0x8000>; // L1, 32K
	42	i-cache-size = <0x8000>; // L1, 32K
	43	timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
	44	bus-frequency = <198000000>; // 198 MHz csb bus
	45	clock-frequency = <396000000>; // 396 MHz ppc core
	46	};
	47	};
	48
	49	memory {
	50	device_type = "memory";
	51	reg = <0x00000000 0x10000000>; // 256MB at 0
	52	};
	53
	54	sram@30000000 {
	55	compatible = "fsl,mpc5121-sram";
	56	reg = <0x30000000 0x08000>; // 32K at 0x30000000
	57	};
	58
bc750594 GS	59	clocks {
	60	#address-cells = <1>;
	61	#size-cells = <0>;
	62
	63	osc: osc {
	64	compatible = "fixed-clock";
	65	#clock-cells = <0>;
	66	clock-frequency = <33000000>;
	67	};
	68	};
	69
a9b6aae4 MF	70	soc@80000000 {
	71	compatible = "fsl,mpc5121-immr";
	72	#address-cells = <1>;
	73	#size-cells = <1>;
a9b6aae4 MF	74	ranges = <0x0 0x80000000 0x400000>;
	75	reg = <0x80000000 0x400000>;
	76	bus-frequency = <66000000>; // 66 MHz ips bus
	77
	78	// IPIC
	79	// interrupts cell = <intr #, sense>
	80	// sense values match linux IORESOURCE_IRQ_* defines:
	81	// sense == 8: Level, low assertion
	82	// sense == 2: Edge, high-to-low change
	83	//
	84	ipic: interrupt-controller@c00 {
	85	compatible = "fsl,mpc5121-ipic", "fsl,ipic";
	86	interrupt-controller;
	87	#address-cells = <0>;
	88	#interrupt-cells = <2>;
	89	reg = <0xc00 0x100>;
	90	};
	91
	92	rtc@a00 { // Real time clock
	93	compatible = "fsl,mpc5121-rtc";
	94	reg = <0xa00 0x100>;
	95	interrupts = <79 0x8 80 0x8>;
	96	};
	97
	98	reset@e00 { // Reset module
	99	compatible = "fsl,mpc5125-reset";
	100	reg = <0xe00 0x100>;
	101	};
	102
bc750594	103	clks: clock@f00 { // Clock control
a9b6aae4 MF	104	compatible = "fsl,mpc5121-clock";
a9b6aae4 MF	105	reg = <0xf00 0x100>;
bc750594 GS	106	#clock-cells = <1>;
	107	clocks = <&osc>;
	108	clock-names = "osc";
a9b6aae4 MF	109	};
	110
	111	pmc@1000{ // Power Management Controller
	112	compatible = "fsl,mpc5121-pmc";
	113	reg = <0x1000 0x100>;
	114	interrupts = <83 0x2>;
	115	};
	116
	117	gpio0: gpio@1100 {
	118	compatible = "fsl,mpc5125-gpio";
	119	reg = <0x1100 0x080>;
	120	interrupts = <78 0x8>;
	121	};
	122
	123	gpio1: gpio@1180 {
	124	compatible = "fsl,mpc5125-gpio";
	125	reg = <0x1180 0x080>;
	126	interrupts = <86 0x8>;
	127	};
	128
	129	can@1300 { // CAN rev.2
	130	compatible = "fsl,mpc5121-mscan";
	131	interrupts = <12 0x8>;
	132	reg = <0x1300 0x80>;
bc750594 GS	133	clocks = <&clks MPC512x_CLK_BDLC>,
	134	<&clks MPC512x_CLK_IPS>,
	135	<&clks MPC512x_CLK_SYS>,
	136	<&clks MPC512x_CLK_REF>,
	137	<&clks MPC512x_CLK_MSCAN0_MCLK>;
	138	clock-names = "ipg", "ips", "sys", "ref", "mclk";
a9b6aae4 MF	139	};
	140
	141	can@1380 {
	142	compatible = "fsl,mpc5121-mscan";
	143	interrupts = <13 0x8>;
	144	reg = <0x1380 0x80>;
bc750594 GS	145	clocks = <&clks MPC512x_CLK_BDLC>,
	146	<&clks MPC512x_CLK_IPS>,
	147	<&clks MPC512x_CLK_SYS>,
	148	<&clks MPC512x_CLK_REF>,
	149	<&clks MPC512x_CLK_MSCAN1_MCLK>;
	150	clock-names = "ipg", "ips", "sys", "ref", "mclk";
a9b6aae4 MF	151	};
	152
	153	sdhc@1500 {
	154	compatible = "fsl,mpc5121-sdhc";
	155	interrupts = <8 0x8>;
	156	reg = <0x1500 0x100>;
bc750594 GS	157	clocks = <&clks MPC512x_CLK_IPS>,
	158	<&clks MPC512x_CLK_SDHC>;
	159	clock-names = "ipg", "per";
a9b6aae4 MF	160	};
	161
	162	i2c@1700 {
	163	#address-cells = <1>;
	164	#size-cells = <0>;
	165	compatible = "fsl,mpc5121-i2c", "fsl-i2c";
	166	reg = <0x1700 0x20>;
	167	interrupts = <0x9 0x8>;
bc750594 GS	168	clocks = <&clks MPC512x_CLK_I2C>;
bc750594 GS	169	clock-names = "ipg";
a9b6aae4 MF	170	};
	171
	172	i2c@1720 {
	173	#address-cells = <1>;
	174	#size-cells = <0>;
	175	compatible = "fsl,mpc5121-i2c", "fsl-i2c";
	176	reg = <0x1720 0x20>;
	177	interrupts = <0xa 0x8>;
bc750594 GS	178	clocks = <&clks MPC512x_CLK_I2C>;
bc750594 GS	179	clock-names = "ipg";
a9b6aae4 MF	180	};
	181
	182	i2c@1740 {
	183	#address-cells = <1>;
	184	#size-cells = <0>;
	185	compatible = "fsl,mpc5121-i2c", "fsl-i2c";
	186	reg = <0x1740 0x20>;
	187	interrupts = <0xb 0x8>;
bc750594 GS	188	clocks = <&clks MPC512x_CLK_I2C>;
bc750594 GS	189	clock-names = "ipg";
a9b6aae4 MF	190	};
	191
	192	i2ccontrol@1760 {
	193	compatible = "fsl,mpc5121-i2c-ctrl";
	194	reg = <0x1760 0x8>;
	195	};
	196
	197	diu@2100 {
	198	compatible = "fsl,mpc5121-diu";
	199	reg = <0x2100 0x100>;
	200	interrupts = <64 0x8>;
bc750594 GS	201	clocks = <&clks MPC512x_CLK_DIU>;
bc750594 GS	202	clock-names = "ipg";
a9b6aae4 MF	203	};
	204
	205	mdio@2800 {
	206	compatible = "fsl,mpc5121-fec-mdio";
	207	reg = <0x2800 0x800>;
	208	#address-cells = <1>;
	209	#size-cells = <0>;
	210	phy0: ethernet-phy@0 {
	211	reg = <1>;
	212	};
	213	};
	214
	215	eth0: ethernet@2800 {
	216	compatible = "fsl,mpc5125-fec";
	217	reg = <0x2800 0x800>;
	218	local-mac-address = [ 00 00 00 00 00 00 ];
	219	interrupts = <4 0x8>;
	220	phy-handle = < &phy0 >;
	221	phy-connection-type = "rmii";
bc750594 GS	222	clocks = <&clks MPC512x_CLK_FEC>;
bc750594 GS	223	clock-names = "per";
a9b6aae4 MF	224	};
	225
	226	// IO control
	227	ioctl@a000 {
	228	compatible = "fsl,mpc5125-ioctl";
	229	reg = <0xA000 0x1000>;
	230	};
	231
11daf32b MF	232	// disable USB1 port
	233	// TODO:
	234	// correct pinmux config and fix USB3320 ulpi dependency
	235	// before re-enabling it
a9b6aae4 MF	236	usb@3000 {
	237	compatible = "fsl,mpc5121-usb2-dr";
	238	reg = <0x3000 0x400>;
	239	#address-cells = <1>;
	240	#size-cells = <0>;
	241	interrupts = <43 0x8>;
	242	dr_mode = "host";
	243	phy_type = "ulpi";
bc750594 GS	244	clocks = <&clks MPC512x_CLK_USB1>;
bc750594 GS	245	clock-names = "ipg";
11daf32b	246	status = "disabled";
a9b6aae4 MF	247	};
	248
	249	// 5125 PSCs are not 52xx or 5121 PSC compatible
	250	// PSC1 uart0 aka ttyPSC0
	251	serial@11100 {
	252	compatible = "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc";
	253	reg = <0x11100 0x100>;
	254	interrupts = <40 0x8>;
	255	fsl,rx-fifo-size = <16>;
	256	fsl,tx-fifo-size = <16>;
bc750594 GS	257	clocks = <&clks MPC512x_CLK_PSC1>,
	258	<&clks MPC512x_CLK_PSC1_MCLK>;
	259	clock-names = "ipg", "mclk";
a9b6aae4 MF	260	};
	261
	262	// PSC9 uart1 aka ttyPSC1
	263	serial@11900 {
	264	compatible = "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc";
	265	reg = <0x11900 0x100>;
	266	interrupts = <40 0x8>;
	267	fsl,rx-fifo-size = <16>;
	268	fsl,tx-fifo-size = <16>;
bc750594 GS	269	clocks = <&clks MPC512x_CLK_PSC9>,
	270	<&clks MPC512x_CLK_PSC9_MCLK>;
	271	clock-names = "ipg", "mclk";
a9b6aae4 MF	272	};
	273
	274	pscfifo@11f00 {
	275	compatible = "fsl,mpc5121-psc-fifo";
	276	reg = <0x11f00 0x100>;
	277	interrupts = <40 0x8>;
bc750594 GS	278	clocks = <&clks MPC512x_CLK_PSC_FIFO>;
bc750594 GS	279	clock-names = "ipg";
a9b6aae4 MF	280	};
	281
	282	dma@14000 {
	283	compatible = "fsl,mpc5121-dma"; // BSP name: "mpc512x-dma2"
	284	reg = <0x14000 0x1800>;
	285	interrupts = <65 0x8>;
	286	};
	287	};
	288	};