[deliverable/linux.git] / arch / powerpc / boot / dts / mpc5200b.dtsi

/*
 * base MPC5200b Device Tree Source
 *
 * Copyright (C) 2010 SecretLab
 * Grant Likely <grant@secretlab.ca>
 * John Bonesio <bones@secretlab.ca>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/dts-v1/;

/ {
	model = "fsl,mpc5200b";
	compatible = "fsl,mpc5200b";
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&mpc5200_pic>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		powerpc: PowerPC,5200@0 {
			device_type = "cpu";
			reg = <0>;
			d-cache-line-size = <32>;
			i-cache-line-size = <32>;
			d-cache-size = <0x4000>;	// L1, 16K
			i-cache-size = <0x4000>;	// L1, 16K
			timebase-frequency = <0>;	// from bootloader
			bus-frequency = <0>;		// from bootloader
			clock-frequency = <0>;		// from bootloader
		};
	};

	memory: memory {
		device_type = "memory";
		reg = <0x00000000 0x04000000>;	// 64MB
	};

	soc: soc5200@f0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "fsl,mpc5200b-immr";
		ranges = <0 0xf0000000 0x0000c000>;
		reg = <0xf0000000 0x00000100>;
		bus-frequency = <0>;		// from bootloader
		system-frequency = <0>;		// from bootloader

		cdm@200 {
			compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
			reg = <0x200 0x38>;
		};

		mpc5200_pic: interrupt-controller@500 {
			// 5200 interrupts are encoded into two levels;
			interrupt-controller;
			#interrupt-cells = <3>;
			compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
			reg = <0x500 0x80>;
		};

		timer@600 {	// General Purpose Timer
			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
			reg = <0x600 0x10>;
			interrupts = <1 9 0>;
		};

		timer@610 {	// General Purpose Timer
			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
			reg = <0x610 0x10>;
			interrupts = <1 10 0>;
		};

		timer@620 {	// General Purpose Timer
			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
			reg = <0x620 0x10>;
			interrupts = <1 11 0>;
		};

		timer@630 {	// General Purpose Timer
			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
			reg = <0x630 0x10>;
			interrupts = <1 12 0>;
		};

		timer@640 {	// General Purpose Timer
			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
			reg = <0x640 0x10>;
			interrupts = <1 13 0>;
		};

		timer@650 {	// General Purpose Timer
			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
			reg = <0x650 0x10>;
			interrupts = <1 14 0>;
		};

		timer@660 {	// General Purpose Timer
			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
			reg = <0x660 0x10>;
			interrupts = <1 15 0>;
		};

		timer@670 {	// General Purpose Timer
			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
			reg = <0x670 0x10>;
			interrupts = <1 16 0>;
		};

		rtc@800 {	// Real time clock
			compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
			reg = <0x800 0x100>;
			interrupts = <1 5 0 1 6 0>;
		};

		can@900 {
			compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
			interrupts = <2 17 0>;
			reg = <0x900 0x80>;
		};

		can@980 {
			compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
			interrupts = <2 18 0>;
			reg = <0x980 0x80>;
		};

		gpio_simple: gpio@b00 {
			compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
			reg = <0xb00 0x40>;
			interrupts = <1 7 0>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		gpio_wkup: gpio@c00 {
			compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
			reg = <0xc00 0x40>;
			interrupts = <1 8 0 0 3 0>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		spi@f00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
			reg = <0xf00 0x20>;
			interrupts = <2 13 0 2 14 0>;
		};

		usb: usb@1000 {
			compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
			reg = <0x1000 0xff>;
			interrupts = <2 6 0>;
		};

		dma-controller@1200 {
			compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
			reg = <0x1200 0x80>;
			interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
			              3 4 0  3 5 0  3 6 0  3 7 0
			              3 8 0  3 9 0  3 10 0  3 11 0
			              3 12 0  3 13 0  3 14 0  3 15 0>;
		};

		xlb@1f00 {
			compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
			reg = <0x1f00 0x100>;
		};

		psc1: psc@2000 {		// PSC1
			compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
			reg = <0x2000 0x100>;
			interrupts = <2 1 0>;
		};

		psc2: psc@2200 {		// PSC2
			compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
			reg = <0x2200 0x100>;
			interrupts = <2 2 0>;
		};

		psc3: psc@2400 {		// PSC3
			compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
			reg = <0x2400 0x100>;
			interrupts = <2 3 0>;
		};

		psc4: psc@2600 {		// PSC4
			compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
			reg = <0x2600 0x100>;
			interrupts = <2 11 0>;
		};

		psc5: psc@2800 {		// PSC5
			compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
			reg = <0x2800 0x100>;
			interrupts = <2 12 0>;
		};

		psc6: psc@2c00 {		// PSC6
			compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
			reg = <0x2c00 0x100>;
			interrupts = <2 4 0>;
		};

		eth0: ethernet@3000 {
			compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
			reg = <0x3000 0x400>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <2 5 0>;
		};

		mdio@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
			reg = <0x3000 0x400>;	// fec range, since we need to setup fec interrupts
			interrupts = <2 5 0>;	// these are for "mii command finished", not link changes & co.
		};

		ata@3a00 {
			compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
			reg = <0x3a00 0x100>;
			interrupts = <2 7 0>;
		};

		i2c@3d00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
			reg = <0x3d00 0x40>;
			interrupts = <2 15 0>;
		};

		i2c@3d40 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
			reg = <0x3d40 0x40>;
			interrupts = <2 16 0>;
		};

		sram@8000 {
			compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
			reg = <0x8000 0x4000>;
		};
	};

	pci: pci@f0000d00 {
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		device_type = "pci";
		compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
		reg = <0xf0000d00 0x100>;
		// interrupt-map-mask = need to add
		// interrupt-map = need to add
		clock-frequency = <0>; // From boot loader
		interrupts = <2 8 0 2 9 0 2 10 0>;
		bus-range = <0 0>;
		// ranges = need to add
	};

	localbus: localbus {
		compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
		#address-cells = <2>;
		#size-cells = <1>;
		ranges = <0 0 0xfc000000 0x2000000>;
	};
};
Commit	Line	Data
c8bf6b52 JB	1	/*
	2	* base MPC5200b Device Tree Source
	3	*
	4	* Copyright (C) 2010 SecretLab
	5	* Grant Likely <grant@secretlab.ca>
	6	* John Bonesio <bones@secretlab.ca>
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*/
	13
	14	/dts-v1/;
	15
	16	/ {
	17	model = "fsl,mpc5200b";
	18	compatible = "fsl,mpc5200b";
	19	#address-cells = <1>;
	20	#size-cells = <1>;
	21	interrupt-parent = <&mpc5200_pic>;
	22
	23	cpus {
	24	#address-cells = <1>;
	25	#size-cells = <0>;
	26
	27	powerpc: PowerPC,5200@0 {
	28	device_type = "cpu";
	29	reg = <0>;
	30	d-cache-line-size = <32>;
	31	i-cache-line-size = <32>;
	32	d-cache-size = <0x4000>; // L1, 16K
	33	i-cache-size = <0x4000>; // L1, 16K
	34	timebase-frequency = <0>; // from bootloader
	35	bus-frequency = <0>; // from bootloader
	36	clock-frequency = <0>; // from bootloader
	37	};
	38	};
	39
	40	memory: memory {
	41	device_type = "memory";
	42	reg = <0x00000000 0x04000000>; // 64MB
	43	};
	44
	45	soc: soc5200@f0000000 {
	46	#address-cells = <1>;
	47	#size-cells = <1>;
	48	compatible = "fsl,mpc5200b-immr";
	49	ranges = <0 0xf0000000 0x0000c000>;
	50	reg = <0xf0000000 0x00000100>;
	51	bus-frequency = <0>; // from bootloader
	52	system-frequency = <0>; // from bootloader
	53
	54	cdm@200 {
	55	compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
	56	reg = <0x200 0x38>;
	57	};
	58
	59	mpc5200_pic: interrupt-controller@500 {
	60	// 5200 interrupts are encoded into two levels;
	61	interrupt-controller;
	62	#interrupt-cells = <3>;
	63	compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
	64	reg = <0x500 0x80>;
65	};
66
67	timer@600 { // General Purpose Timer
68	compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
69	reg = <0x600 0x10>;
70	interrupts = <1 9 0>;
71	};
72
73	timer@610 { // General Purpose Timer
74	compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
75	reg = <0x610 0x10>;
76	interrupts = <1 10 0>;
77	};
78
79	timer@620 { // General Purpose Timer
80	compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
81	reg = <0x620 0x10>;
82	interrupts = <1 11 0>;
83	};
84
85	timer@630 { // General Purpose Timer
86	compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
87	reg = <0x630 0x10>;
88	interrupts = <1 12 0>;
89	};
90
91	timer@640 { // General Purpose Timer
92	compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
93	reg = <0x640 0x10>;
94	interrupts = <1 13 0>;
95	};
96
97	timer@650 { // General Purpose Timer
98	compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
99	reg = <0x650 0x10>;
100	interrupts = <1 14 0>;
101	};
102
103	timer@660 { // General Purpose Timer
104	compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
105	reg = <0x660 0x10>;
106	interrupts = <1 15 0>;
107	};
108
109	timer@670 { // General Purpose Timer
110	compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
111	reg = <0x670 0x10>;
112	interrupts = <1 16 0>;
113	};
114
115	rtc@800 { // Real time clock
116	compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
117	reg = <0x800 0x100>;
118	interrupts = <1 5 0 1 6 0>;
119	};
120
121	can@900 {
122	compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
123	interrupts = <2 17 0>;
124	reg = <0x900 0x80>;
125	};
126
127	can@980 {
128	compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
129	interrupts = <2 18 0>;
130	reg = <0x980 0x80>;
131	};
132
133	gpio_simple: gpio@b00 {
134	compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
135	reg = <0xb00 0x40>;
136	interrupts = <1 7 0>;
137	gpio-controller;
138	#gpio-cells = <2>;
139	};
140
141	gpio_wkup: gpio@c00 {
142	compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
143	reg = <0xc00 0x40>;
144	interrupts = <1 8 0 0 3 0>;
145	gpio-controller;
146	#gpio-cells = <2>;
147	};
148
149	spi@f00 {
6cf1d0b8 AG	150	#address-cells = <1>;
6cf1d0b8 AG	151	#size-cells = <0>;
c8bf6b52 JB	152	compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
	153	reg = <0xf00 0x20>;
	154	interrupts = <2 13 0 2 14 0>;
	155	};
	156
	157	usb: usb@1000 {
	158	compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
	159	reg = <0x1000 0xff>;
	160	interrupts = <2 6 0>;
	161	};
	162
	163	dma-controller@1200 {
	164	compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
	165	reg = <0x1200 0x80>;
	166	interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
	167	3 4 0 3 5 0 3 6 0 3 7 0
	168	3 8 0 3 9 0 3 10 0 3 11 0
	169	3 12 0 3 13 0 3 14 0 3 15 0>;
	170	};
	171
	172	xlb@1f00 {
	173	compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
	174	reg = <0x1f00 0x100>;
	175	};
	176
	177	psc1: psc@2000 { // PSC1
	178	compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
	179	reg = <0x2000 0x100>;
	180	interrupts = <2 1 0>;
	181	};
	182
	183	psc2: psc@2200 { // PSC2
	184	compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
	185	reg = <0x2200 0x100>;
	186	interrupts = <2 2 0>;
	187	};
	188
	189	psc3: psc@2400 { // PSC3
	190	compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
	191	reg = <0x2400 0x100>;
	192	interrupts = <2 3 0>;
	193	};
	194
	195	psc4: psc@2600 { // PSC4
	196	compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
	197	reg = <0x2600 0x100>;
	198	interrupts = <2 11 0>;
	199	};
	200
	201	psc5: psc@2800 { // PSC5
	202	compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
	203	reg = <0x2800 0x100>;
	204	interrupts = <2 12 0>;
	205	};
	206
	207	psc6: psc@2c00 { // PSC6
	208	compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
	209	reg = <0x2c00 0x100>;
	210	interrupts = <2 4 0>;
	211	};
	212
	213	eth0: ethernet@3000 {
	214	compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
	215	reg = <0x3000 0x400>;
216	local-mac-address = [ 00 00 00 00 00 00 ];
217	interrupts = <2 5 0>;
218	};
219
220	mdio@3000 {
221	#address-cells = <1>;
222	#size-cells = <0>;
223	compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
224	reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
225	interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
226	};
227
228	ata@3a00 {
229	compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
230	reg = <0x3a00 0x100>;
231	interrupts = <2 7 0>;
232	};
233
234	i2c@3d00 {
235	#address-cells = <1>;
236	#size-cells = <0>;
237	compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
238	reg = <0x3d00 0x40>;
239	interrupts = <2 15 0>;
240	};
241
242	i2c@3d40 {
243	#address-cells = <1>;
244	#size-cells = <0>;
245	compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
246	reg = <0x3d40 0x40>;
247	interrupts = <2 16 0>;
248	};
249
250	sram@8000 {
251	compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
252	reg = <0x8000 0x4000>;
253	};
254	};
255
256	pci: pci@f0000d00 {
257	#interrupt-cells = <1>;
258	#size-cells = <2>;
259	#address-cells = <3>;
260	device_type = "pci";
261	compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
262	reg = <0xf0000d00 0x100>;
263	// interrupt-map-mask = need to add
264	// interrupt-map = need to add
265	clock-frequency = <0>; // From boot loader
266	interrupts = <2 8 0 2 9 0 2 10 0>;
267	bus-range = <0 0>;
268	// ranges = need to add
269	};
270
271	localbus: localbus {
272	compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
273	#address-cells = <2>;
274	#size-cells = <1>;
275	ranges = <0 0 0xfc000000 0x2000000>;
276	};
277	};