[deliverable/linux.git] / arch / powerpc / boot / dts / mpc832x_mds.dts

/*
 * MPC8323E EMDS Device Tree Source
 *
 * Copyright 2006 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.

 * To enable external serial I/O on a Freescale MPC 8323 SYS/MDS board, do
 * this:
 *
 * 1) On chip U61, lift (disconnect) pins 21 (TXD) and 22 (RXD) from the board.
 * 2) Solder a wire from U61-21 to P19A-23.  P19 is a grid of pins on the board
 *    next to the serial ports.
 * 3) Solder a wire from U61-22 to P19K-22.
 *
 * Note that there's a typo in the schematic.  The board labels the last column
 * of pins "P19K", but in the schematic, that column is called "P19J".  So if
 * you're going by the schematic, the pin is called "P19J-K22".
 */

/dts-v1/;

/ {
	model = "MPC8323EMDS";
	compatible = "MPC8323EMDS", "MPC832xMDS", "MPC83xxMDS";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8323@0 {
			device_type = "cpu";
			reg = <0x0>;
			d-cache-line-size = <32>;	// 32 bytes
			i-cache-line-size = <32>;	// 32 bytes
			d-cache-size = <16384>;		// L1, 16K
			i-cache-size = <16384>;		// L1, 16K
			timebase-frequency = <0>;
			bus-frequency = <0>;
			clock-frequency = <0>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x08000000>;
	};

	bcsr@f8000000 {
		compatible = "fsl,mpc8323mds-bcsr";
		reg = <0xf8000000 0x8000>;
	};

	soc8323@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		compatible = "simple-bus";
		ranges = <0x0 0xe0000000 0x00100000>;
		reg = <0xe0000000 0x00000200>;
		bus-frequency = <132000000>;

		wdt@200 {
			device_type = "watchdog";
			compatible = "mpc83xx_wdt";
			reg = <0x200 0x100>;
		};

		pmc: power@b00 {
			compatible = "fsl,mpc8323-pmc", "fsl,mpc8349-pmc";
			reg = <0xb00 0x100 0xa00 0x100>;
			interrupts = <80 0x8>;
			interrupt-parent = <&ipic>;
		};

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <14 0x8>;
			interrupt-parent = <&ipic>;
			dfsrr;

			rtc@68 {
				compatible = "dallas,ds1374";
				reg = <0x68>;
			};
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "fsl,ns16550", "ns16550";
			reg = <0x4500 0x100>;
			clock-frequency = <0>;
			interrupts = <9 0x8>;
			interrupt-parent = <&ipic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "fsl,ns16550", "ns16550";
			reg = <0x4600 0x100>;
			clock-frequency = <0>;
			interrupts = <10 0x8>;
			interrupt-parent = <&ipic>;
		};

		dma@82a8 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8323-dma", "fsl,elo-dma";
			reg = <0x82a8 4>;
			ranges = <0 0x8100 0x1a8>;
			interrupt-parent = <&ipic>;
			interrupts = <71 8>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
				reg = <0 0x80>;
				cell-index = <0>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
			dma-channel@80 {
				compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
			dma-channel@100 {
				compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
			dma-channel@180 {
				compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
				reg = <0x180 0x28>;
				cell-index = <3>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
		};

		crypto@30000 {
			compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
			reg = <0x30000 0x10000>;
			interrupts = <11 0x8>;
			interrupt-parent = <&ipic>;
			fsl,num-channels = <1>;
			fsl,channel-fifo-len = <24>;
			fsl,exec-units-mask = <0x4c>;
			fsl,descriptor-types-mask = <0x0122003f>;
			sleep = <&pmc 0x03000000>;
		};

		ipic: pic@700 {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x700 0x100>;
			device_type = "ipic";
		};

		par_io@1400 {
			reg = <0x1400 0x100>;
			device_type = "par_io";
			num-ports = <7>;

			pio3: ucc_pin@03 {
				pio-map = <
			/* port  pin  dir  open_drain  assignment  has_irq */
					3  4  3  0  2  0  /* MDIO */
					3  5  1  0  2  0  /* MDC */
					0 13  2  0  1  0 	/* RX_CLK (CLK9) */
					3 24  2  0  1  0 	/* TX_CLK (CLK10) */
					1  0  1  0  1  0 	/* TxD0 */
					1  1  1  0  1  0 	/* TxD1 */
					1  2  1  0  1  0 	/* TxD2 */
					1  3  1  0  1  0 	/* TxD3 */
					1  4  2  0  1  0 	/* RxD0 */
					1  5  2  0  1  0 	/* RxD1 */
					1  6  2  0  1  0 	/* RxD2 */
					1  7  2  0  1  0 	/* RxD3 */
					1  8  2  0  1  0 	/* RX_ER */
					1  9  1  0  1  0 	/* TX_ER */
					1 10  2  0  1  0 	/* RX_DV */
					1 11  2  0  1  0 	/* COL */
					1 12  1  0  1  0 	/* TX_EN */
					1 13  2  0  1  0>;	/* CRS */
			};
			pio4: ucc_pin@04 {
				pio-map = <
			/* port  pin  dir  open_drain  assignment  has_irq */
					3 31  2  0  1  0 	/* RX_CLK (CLK7) */
					3  6  2  0  1  0 	/* TX_CLK (CLK8) */
					1 18  1  0  1  0 	/* TxD0 */
					1 19  1  0  1  0 	/* TxD1 */
					1 20  1  0  1  0 	/* TxD2 */
					1 21  1  0  1  0 	/* TxD3 */
					1 22  2  0  1  0 	/* RxD0 */
					1 23  2  0  1  0 	/* RxD1 */
					1 24  2  0  1  0 	/* RxD2 */
					1 25  2  0  1  0 	/* RxD3 */
					1 26  2  0  1  0 	/* RX_ER */
					1 27  1  0  1  0 	/* TX_ER */
					1 28  2  0  1  0 	/* RX_DV */
					1 29  2  0  1  0 	/* COL */
					1 30  1  0  1  0 	/* TX_EN */
					1 31  2  0  1  0>;	/* CRS */
			};
			pio5: ucc_pin@05 {
				pio-map = <
				/*
				 *    		      open       has
				 *   port  pin  dir  drain  sel  irq
				 */
					2    0    1      0    2    0  /* TxD5 */
					2    8    2      0    2    0  /* RxD5 */

					2   29    2      0    0    0  /* CTS5 */
					2   31    1      0    2    0  /* RTS5 */

					2   24    2      0    0    0  /* CD */

				>;
			};

		};
	};

	qe@e0100000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "qe";
		compatible = "fsl,qe";
		ranges = <0x0 0xe0100000 0x00100000>;
		reg = <0xe0100000 0x480>;
		brg-frequency = <0>;
		bus-frequency = <198000000>;
		fsl,qe-num-riscs = <1>;
		fsl,qe-num-snums = <28>;

		muram@10000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,qe-muram", "fsl,cpm-muram";
			ranges = <0x0 0x00010000 0x00004000>;

			data-only@0 {
				compatible = "fsl,qe-muram-data",
					     "fsl,cpm-muram-data";
				reg = <0x0 0x4000>;
			};
		};

		spi@4c0 {
			cell-index = <0>;
			compatible = "fsl,spi";
			reg = <0x4c0 0x40>;
			interrupts = <2>;
			interrupt-parent = <&qeic>;
			mode = "cpu";
		};

		spi@500 {
			cell-index = <1>;
			compatible = "fsl,spi";
			reg = <0x500 0x40>;
			interrupts = <1>;
			interrupt-parent = <&qeic>;
			mode = "cpu";
		};

		usb@6c0 {
			compatible = "qe_udc";
			reg = <0x6c0 0x40 0x8b00 0x100>;
			interrupts = <11>;
			interrupt-parent = <&qeic>;
			mode = "slave";
		};

		enet0: ucc@2200 {
			device_type = "network";
			compatible = "ucc_geth";
			cell-index = <3>;
			reg = <0x2200 0x200>;
			interrupts = <34>;
			interrupt-parent = <&qeic>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			rx-clock-name = "clk9";
			tx-clock-name = "clk10";
			phy-handle = <&phy3>;
			pio-handle = <&pio3>;
		};

		enet1: ucc@3200 {
			device_type = "network";
			compatible = "ucc_geth";
			cell-index = <4>;
			reg = <0x3200 0x200>;
			interrupts = <35>;
			interrupt-parent = <&qeic>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			rx-clock-name = "clk7";
			tx-clock-name = "clk8";
			phy-handle = <&phy4>;
			pio-handle = <&pio4>;
		};

		ucc@2400 {
			device_type = "serial";
			compatible = "ucc_uart";
			cell-index = <5>;	/* The UCC number, 1-7*/
			port-number = <0>;	/* Which ttyQEx device */
			soft-uart;		/* We need Soft-UART */
			reg = <0x2400 0x200>;
			interrupts = <40>;	/* From Table 18-12 */
			interrupt-parent = < &qeic >;
			/*
			 * For Soft-UART, we need to set TX to 1X, which
			 * means specifying separate clock sources.
			 */
			rx-clock-name = "brg5";
			tx-clock-name = "brg6";
			pio-handle = < &pio5 >;
		};


		mdio@2320 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x2320 0x18>;
			compatible = "fsl,ucc-mdio";

			phy3: ethernet-phy@03 {
				interrupt-parent = <&ipic>;
				interrupts = <17 0x8>;
				reg = <0x3>;
			};
			phy4: ethernet-phy@04 {
				interrupt-parent = <&ipic>;
				interrupts = <18 0x8>;
				reg = <0x4>;
			};
		};

		qeic: interrupt-controller@80 {
			interrupt-controller;
			compatible = "fsl,qe-ic";
			#address-cells = <0>;
			#interrupt-cells = <1>;
			reg = <0x80 0x80>;
			big-endian;
			interrupts = <32 0x8 33 0x8>; //high:32 low:33
			interrupt-parent = <&ipic>;
		};
	};

	pci0: pci@e0008500 {
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <
				/* IDSEL 0x11 AD17 */
				 0x8800 0x0 0x0 0x1 &ipic 20 0x8
				 0x8800 0x0 0x0 0x2 &ipic 21 0x8
				 0x8800 0x0 0x0 0x3 &ipic 22 0x8
				 0x8800 0x0 0x0 0x4 &ipic 23 0x8

				/* IDSEL 0x12 AD18 */
				 0x9000 0x0 0x0 0x1 &ipic 22 0x8
				 0x9000 0x0 0x0 0x2 &ipic 23 0x8
				 0x9000 0x0 0x0 0x3 &ipic 20 0x8
				 0x9000 0x0 0x0 0x4 &ipic 21 0x8

				/* IDSEL 0x13 AD19 */
				 0x9800 0x0 0x0 0x1 &ipic 23 0x8
				 0x9800 0x0 0x0 0x2 &ipic 20 0x8
				 0x9800 0x0 0x0 0x3 &ipic 21 0x8
				 0x9800 0x0 0x0 0x4 &ipic 22 0x8

				/* IDSEL 0x15 AD21*/
				 0xa800 0x0 0x0 0x1 &ipic 20 0x8
				 0xa800 0x0 0x0 0x2 &ipic 21 0x8
				 0xa800 0x0 0x0 0x3 &ipic 22 0x8
				 0xa800 0x0 0x0 0x4 &ipic 23 0x8

				/* IDSEL 0x16 AD22*/
				 0xb000 0x0 0x0 0x1 &ipic 23 0x8
				 0xb000 0x0 0x0 0x2 &ipic 20 0x8
				 0xb000 0x0 0x0 0x3 &ipic 21 0x8
				 0xb000 0x0 0x0 0x4 &ipic 22 0x8

				/* IDSEL 0x17 AD23*/
				 0xb800 0x0 0x0 0x1 &ipic 22 0x8
				 0xb800 0x0 0x0 0x2 &ipic 23 0x8
				 0xb800 0x0 0x0 0x3 &ipic 20 0x8
				 0xb800 0x0 0x0 0x4 &ipic 21 0x8

				/* IDSEL 0x18 AD24*/
				 0xc000 0x0 0x0 0x1 &ipic 21 0x8
				 0xc000 0x0 0x0 0x2 &ipic 22 0x8
				 0xc000 0x0 0x0 0x3 &ipic 23 0x8
				 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
		interrupt-parent = <&ipic>;
		interrupts = <66 0x8>;
		bus-range = <0x0 0x0>;
		ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
			  0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
			  0x01000000 0x0 0x00000000 0xd0000000 0x0 0x00100000>;
		clock-frequency = <0>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0008500 0x100		/* internal registers */
		       0xe0008300 0x8>;		/* config space access registers */
		compatible = "fsl,mpc8349-pci";
		device_type = "pci";
		sleep = <&pmc 0x00010000>;
	};
};
Commit	Line	Data
18a1e4c3 KP	1	/*
	2	* MPC8323E EMDS Device Tree Source
	3	*
	4	* Copyright 2006 Freescale Semiconductor Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
845cf505 TT	10
	11	* To enable external serial I/O on a Freescale MPC 8323 SYS/MDS board, do
	12	* this:
	13	*
	14	* 1) On chip U61, lift (disconnect) pins 21 (TXD) and 22 (RXD) from the board.
	15	* 2) Solder a wire from U61-21 to P19A-23. P19 is a grid of pins on the board
	16	* next to the serial ports.
	17	* 3) Solder a wire from U61-22 to P19K-22.
	18	*
	19	* Note that there's a typo in the schematic. The board labels the last column
	20	* of pins "P19K", but in the schematic, that column is called "P19J". So if
	21	* you're going by the schematic, the pin is called "P19J-K22".
18a1e4c3 KP	22	*/
18a1e4c3 KP	23
cda13dd1 PG	24	/dts-v1/;
cda13dd1 PG	25
18a1e4c3 KP	26	/ {
18a1e4c3 KP	27	model = "MPC8323EMDS";
d71a1dc6	28	compatible = "MPC8323EMDS", "MPC832xMDS", "MPC83xxMDS";
18a1e4c3 KP	29	#address-cells = <1>;
18a1e4c3 KP	30	#size-cells = <1>;
18a1e4c3	31
ea082fa9 KG	32	aliases {
	33	ethernet0 = &enet0;
	34	ethernet1 = &enet1;
	35	serial0 = &serial0;
	36	serial1 = &serial1;
	37	pci0 = &pci0;
	38	};
	39
18a1e4c3	40	cpus {
18a1e4c3 KP	41	#address-cells = <1>;
18a1e4c3 KP	42	#size-cells = <0>;
18a1e4c3 KP	43
	44	PowerPC,8323@0 {
	45	device_type = "cpu";
cda13dd1 PG	46	reg = <0x0>;
	47	d-cache-line-size = <32>; // 32 bytes
	48	i-cache-line-size = <32>; // 32 bytes
	49	d-cache-size = <16384>; // L1, 16K
	50	i-cache-size = <16384>; // L1, 16K
18a1e4c3 KP	51	timebase-frequency = <0>;
	52	bus-frequency = <0>;
	53	clock-frequency = <0>;
18a1e4c3 KP	54	};
	55	};
	56
	57	memory {
	58	device_type = "memory";
cda13dd1	59	reg = <0x00000000 0x08000000>;
18a1e4c3 KP	60	};
	61
	62	bcsr@f8000000 {
fd657efc	63	compatible = "fsl,mpc8323mds-bcsr";
cda13dd1	64	reg = <0xf8000000 0x8000>;
18a1e4c3 KP	65	};
	66
	67	soc8323@e0000000 {
	68	#address-cells = <1>;
	69	#size-cells = <1>;
18a1e4c3	70	device_type = "soc";
cf0d19fb	71	compatible = "simple-bus";
cda13dd1 PG	72	ranges = <0x0 0xe0000000 0x00100000>;
	73	reg = <0xe0000000 0x00000200>;
	74	bus-frequency = <132000000>;
18a1e4c3 KP	75
	76	wdt@200 {
	77	device_type = "watchdog";
	78	compatible = "mpc83xx_wdt";
cda13dd1	79	reg = <0x200 0x100>;
18a1e4c3 KP	80	};
18a1e4c3 KP	81
1f8a25d4 AV	82	pmc: power@b00 {
	83	compatible = "fsl,mpc8323-pmc", "fsl,mpc8349-pmc";
	84	reg = <0xb00 0x100 0xa00 0x100>;
	85	interrupts = <80 0x8>;
	86	interrupt-parent = <&ipic>;
	87	};
	88
18a1e4c3	89	i2c@3000 {
27f49807 KP	90	#address-cells = <1>;
27f49807 KP	91	#size-cells = <0>;
ec9686c4	92	cell-index = <0>;
18a1e4c3	93	compatible = "fsl-i2c";
cda13dd1 PG	94	reg = <0x3000 0x100>;
	95	interrupts = <14 0x8>;
	96	interrupt-parent = <&ipic>;
18a1e4c3	97	dfsrr;
27f49807 KP	98
	99	rtc@68 {
	100	compatible = "dallas,ds1374";
cda13dd1	101	reg = <0x68>;
27f49807	102	};
18a1e4c3 KP	103	};
18a1e4c3 KP	104
ea082fa9 KG	105	serial0: serial@4500 {
ea082fa9 KG	106	cell-index = <0>;
18a1e4c3	107	device_type = "serial";
f706bed1	108	compatible = "fsl,ns16550", "ns16550";
cda13dd1	109	reg = <0x4500 0x100>;
18a1e4c3	110	clock-frequency = <0>;
cda13dd1 PG	111	interrupts = <9 0x8>;
cda13dd1 PG	112	interrupt-parent = <&ipic>;
18a1e4c3 KP	113	};
18a1e4c3 KP	114
ea082fa9 KG	115	serial1: serial@4600 {
ea082fa9 KG	116	cell-index = <1>;
18a1e4c3	117	device_type = "serial";
f706bed1	118	compatible = "fsl,ns16550", "ns16550";
cda13dd1	119	reg = <0x4600 0x100>;
18a1e4c3	120	clock-frequency = <0>;
cda13dd1 PG	121	interrupts = <10 0x8>;
cda13dd1 PG	122	interrupt-parent = <&ipic>;
18a1e4c3 KP	123	};
18a1e4c3 KP	124
dee80553 KG	125	dma@82a8 {
	126	#address-cells = <1>;
	127	#size-cells = <1>;
	128	compatible = "fsl,mpc8323-dma", "fsl,elo-dma";
	129	reg = <0x82a8 4>;
	130	ranges = <0 0x8100 0x1a8>;
	131	interrupt-parent = <&ipic>;
	132	interrupts = <71 8>;
	133	cell-index = <0>;
	134	dma-channel@0 {
	135	compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
	136	reg = <0 0x80>;
aeb42762	137	cell-index = <0>;
dee80553 KG	138	interrupt-parent = <&ipic>;
	139	interrupts = <71 8>;
	140	};
	141	dma-channel@80 {
	142	compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
	143	reg = <0x80 0x80>;
aeb42762	144	cell-index = <1>;
dee80553 KG	145	interrupt-parent = <&ipic>;
	146	interrupts = <71 8>;
	147	};
	148	dma-channel@100 {
	149	compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
	150	reg = <0x100 0x80>;
aeb42762	151	cell-index = <2>;
dee80553 KG	152	interrupt-parent = <&ipic>;
	153	interrupts = <71 8>;
	154	};
	155	dma-channel@180 {
	156	compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
	157	reg = <0x180 0x28>;
aeb42762	158	cell-index = <3>;
dee80553 KG	159	interrupt-parent = <&ipic>;
	160	interrupts = <71 8>;
	161	};
	162	};
	163
18a1e4c3	164	crypto@30000 {
3fd44736 KP	165	compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
3fd44736 KP	166	reg = <0x30000 0x10000>;
cda13dd1 PG	167	interrupts = <11 0x8>;
cda13dd1 PG	168	interrupt-parent = <&ipic>;
3fd44736 KP	169	fsl,num-channels = <1>;
	170	fsl,channel-fifo-len = <24>;
	171	fsl,exec-units-mask = <0x4c>;
	172	fsl,descriptor-types-mask = <0x0122003f>;
1f8a25d4	173	sleep = <&pmc 0x03000000>;
18a1e4c3 KP	174	};
18a1e4c3 KP	175
d71a1dc6	176	ipic: pic@700 {
18a1e4c3 KP	177	interrupt-controller;
	178	#address-cells = <0>;
	179	#interrupt-cells = <2>;
cda13dd1	180	reg = <0x700 0x100>;
18a1e4c3 KP	181	device_type = "ipic";
18a1e4c3 KP	182	};
4a2adca9	183
18a1e4c3	184	par_io@1400 {
cda13dd1	185	reg = <0x1400 0x100>;
18a1e4c3 KP	186	device_type = "par_io";
	187	num-ports = <7>;
	188
d71a1dc6	189	pio3: ucc_pin@03 {
18a1e4c3 KP	190	pio-map = <
	191	/* port pin dir open_drain assignment has_irq */
	192	3 4 3 0 2 0 /* MDIO */
	193	3 5 1 0 2 0 /* MDC */
cda13dd1 PG	194	0 13 2 0 1 0 /* RX_CLK (CLK9) */
cda13dd1 PG	195	3 24 2 0 1 0 /* TX_CLK (CLK10) */
18a1e4c3 KP	196	1 0 1 0 1 0 /* TxD0 */
	197	1 1 1 0 1 0 /* TxD1 */
	198	1 2 1 0 1 0 /* TxD2 */
	199	1 3 1 0 1 0 /* TxD3 */
	200	1 4 2 0 1 0 /* RxD0 */
	201	1 5 2 0 1 0 /* RxD1 */
	202	1 6 2 0 1 0 /* RxD2 */
	203	1 7 2 0 1 0 /* RxD3 */
	204	1 8 2 0 1 0 /* RX_ER */
	205	1 9 1 0 1 0 /* TX_ER */
cda13dd1 PG	206	1 10 2 0 1 0 /* RX_DV */
	207	1 11 2 0 1 0 /* COL */
	208	1 12 1 0 1 0 /* TX_EN */
	209	1 13 2 0 1 0>; /* CRS */
18a1e4c3	210	};
d71a1dc6	211	pio4: ucc_pin@04 {
18a1e4c3 KP	212	pio-map = <
18a1e4c3 KP	213	/* port pin dir open_drain assignment has_irq */
cda13dd1	214	3 31 2 0 1 0 /* RX_CLK (CLK7) */
18a1e4c3	215	3 6 2 0 1 0 /* TX_CLK (CLK8) */
cda13dd1 PG	216	1 18 1 0 1 0 /* TxD0 */
	217	1 19 1 0 1 0 /* TxD1 */
	218	1 20 1 0 1 0 /* TxD2 */
	219	1 21 1 0 1 0 /* TxD3 */
	220	1 22 2 0 1 0 /* RxD0 */
	221	1 23 2 0 1 0 /* RxD1 */
	222	1 24 2 0 1 0 /* RxD2 */
	223	1 25 2 0 1 0 /* RxD3 */
	224	1 26 2 0 1 0 /* RX_ER */
	225	1 27 1 0 1 0 /* TX_ER */
	226	1 28 2 0 1 0 /* RX_DV */
	227	1 29 2 0 1 0 /* COL */
	228	1 30 1 0 1 0 /* TX_EN */
	229	1 31 2 0 1 0>; /* CRS */
18a1e4c3	230	};
845cf505 TT	231	pio5: ucc_pin@05 {
	232	pio-map = <
	233	/*
	234	* open has
	235	* port pin dir drain sel irq
	236	*/
	237	2 0 1 0 2 0 /* TxD5 */
	238	2 8 2 0 2 0 /* RxD5 */
	239
cda13dd1 PG	240	2 29 2 0 0 0 /* CTS5 */
cda13dd1 PG	241	2 31 1 0 2 0 /* RTS5 */
845cf505	242
cda13dd1	243	2 24 2 0 0 0 /* CD */
845cf505 TT	244
	245	>;
	246	};
	247
18a1e4c3 KP	248	};
	249	};
	250
	251	qe@e0100000 {
	252	#address-cells = <1>;
	253	#size-cells = <1>;
	254	device_type = "qe";
845cf505	255	compatible = "fsl,qe";
cda13dd1 PG	256	ranges = <0x0 0xe0100000 0x00100000>;
cda13dd1 PG	257	reg = <0xe0100000 0x480>;
18a1e4c3	258	brg-frequency = <0>;
cda13dd1	259	bus-frequency = <198000000>;
01b14a90 HW	260	fsl,qe-num-riscs = <1>;
01b14a90 HW	261	fsl,qe-num-snums = <28>;
4a2adca9	262
18a1e4c3	263	muram@10000 {
cda13dd1 PG	264	#address-cells = <1>;
cda13dd1 PG	265	#size-cells = <1>;
a2dd70a1	266	compatible = "fsl,qe-muram", "fsl,cpm-muram";
cda13dd1	267	ranges = <0x0 0x00010000 0x00004000>;
4a2adca9	268
18a1e4c3	269	data-only@0 {
a2dd70a1 AV	270	compatible = "fsl,qe-muram-data",
a2dd70a1 AV	271	"fsl,cpm-muram-data";
cda13dd1	272	reg = <0x0 0x4000>;
18a1e4c3 KP	273	};
	274	};
	275
	276	spi@4c0 {
f3a2b29d AV	277	cell-index = <0>;
f3a2b29d AV	278	compatible = "fsl,spi";
cda13dd1	279	reg = <0x4c0 0x40>;
18a1e4c3	280	interrupts = <2>;
cda13dd1	281	interrupt-parent = <&qeic>;
18a1e4c3 KP	282	mode = "cpu";
	283	};
	284
	285	spi@500 {
f3a2b29d AV	286	cell-index = <1>;
f3a2b29d AV	287	compatible = "fsl,spi";
cda13dd1	288	reg = <0x500 0x40>;
18a1e4c3	289	interrupts = <1>;
cda13dd1	290	interrupt-parent = <&qeic>;
18a1e4c3 KP	291	mode = "cpu";
	292	};
	293
	294	usb@6c0 {
18a1e4c3	295	compatible = "qe_udc";
cda13dd1 PG	296	reg = <0x6c0 0x40 0x8b00 0x100>;
	297	interrupts = <11>;
	298	interrupt-parent = <&qeic>;
18a1e4c3 KP	299	mode = "slave";
	300	};
	301
e77b28eb	302	enet0: ucc@2200 {
18a1e4c3 KP	303	device_type = "network";
18a1e4c3 KP	304	compatible = "ucc_geth";
e77b28eb	305	cell-index = <3>;
cda13dd1 PG	306	reg = <0x2200 0x200>;
	307	interrupts = <34>;
	308	interrupt-parent = <&qeic>;
eae98266	309	local-mac-address = [ 00 00 00 00 00 00 ];
9fb1e350 TT	310	rx-clock-name = "clk9";
9fb1e350 TT	311	tx-clock-name = "clk10";
cda13dd1 PG	312	phy-handle = <&phy3>;
cda13dd1 PG	313	pio-handle = <&pio3>;
18a1e4c3 KP	314	};
18a1e4c3 KP	315
e77b28eb	316	enet1: ucc@3200 {
18a1e4c3 KP	317	device_type = "network";
18a1e4c3 KP	318	compatible = "ucc_geth";
e77b28eb	319	cell-index = <4>;
cda13dd1 PG	320	reg = <0x3200 0x200>;
	321	interrupts = <35>;
	322	interrupt-parent = <&qeic>;
eae98266	323	local-mac-address = [ 00 00 00 00 00 00 ];
9fb1e350 TT	324	rx-clock-name = "clk7";
9fb1e350 TT	325	tx-clock-name = "clk8";
cda13dd1 PG	326	phy-handle = <&phy4>;
cda13dd1 PG	327	pio-handle = <&pio4>;
18a1e4c3 KP	328	};
18a1e4c3 KP	329
845cf505 TT	330	ucc@2400 {
	331	device_type = "serial";
	332	compatible = "ucc_uart";
56626f33	333	cell-index = <5>; /* The UCC number, 1-7*/
845cf505 TT	334	port-number = <0>; /* Which ttyQEx device */
845cf505 TT	335	soft-uart; /* We need Soft-UART */
cda13dd1 PG	336	reg = <0x2400 0x200>;
cda13dd1 PG	337	interrupts = <40>; /* From Table 18-12 */
845cf505 TT	338	interrupt-parent = < &qeic >;
	339	/*
	340	* For Soft-UART, we need to set TX to 1X, which
	341	* means specifying separate clock sources.
	342	*/
	343	rx-clock-name = "brg5";
	344	tx-clock-name = "brg6";
	345	pio-handle = < &pio5 >;
	346	};
	347
	348
18a1e4c3 KP	349	mdio@2320 {
	350	#address-cells = <1>;
	351	#size-cells = <0>;
cda13dd1	352	reg = <0x2320 0x18>;
d0a2f82d	353	compatible = "fsl,ucc-mdio";
18a1e4c3	354
d71a1dc6	355	phy3: ethernet-phy@03 {
cda13dd1 PG	356	interrupt-parent = <&ipic>;
	357	interrupts = <17 0x8>;
	358	reg = <0x3>;
18a1e4c3	359	};
d71a1dc6	360	phy4: ethernet-phy@04 {
cda13dd1 PG	361	interrupt-parent = <&ipic>;
	362	interrupts = <18 0x8>;
	363	reg = <0x4>;
18a1e4c3 KP	364	};
	365	};
	366
a2dd70a1	367	qeic: interrupt-controller@80 {
18a1e4c3	368	interrupt-controller;
a2dd70a1	369	compatible = "fsl,qe-ic";
18a1e4c3 KP	370	#address-cells = <0>;
18a1e4c3 KP	371	#interrupt-cells = <1>;
cda13dd1	372	reg = <0x80 0x80>;
18a1e4c3	373	big-endian;
cda13dd1 PG	374	interrupts = <32 0x8 33 0x8>; //high:32 low:33
cda13dd1 PG	375	interrupt-parent = <&ipic>;
18a1e4c3 KP	376	};
18a1e4c3 KP	377	};
1b3c5cda	378
ea082fa9	379	pci0: pci@e0008500 {
cda13dd1	380	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
1b3c5cda KG	381	interrupt-map = <
1b3c5cda KG	382	/* IDSEL 0x11 AD17 */
cda13dd1 PG	383	0x8800 0x0 0x0 0x1 &ipic 20 0x8
	384	0x8800 0x0 0x0 0x2 &ipic 21 0x8
	385	0x8800 0x0 0x0 0x3 &ipic 22 0x8
	386	0x8800 0x0 0x0 0x4 &ipic 23 0x8
1b3c5cda KG	387
1b3c5cda KG	388	/* IDSEL 0x12 AD18 */
cda13dd1 PG	389	0x9000 0x0 0x0 0x1 &ipic 22 0x8
	390	0x9000 0x0 0x0 0x2 &ipic 23 0x8
	391	0x9000 0x0 0x0 0x3 &ipic 20 0x8
	392	0x9000 0x0 0x0 0x4 &ipic 21 0x8
1b3c5cda KG	393
1b3c5cda KG	394	/* IDSEL 0x13 AD19 */
cda13dd1 PG	395	0x9800 0x0 0x0 0x1 &ipic 23 0x8
	396	0x9800 0x0 0x0 0x2 &ipic 20 0x8
	397	0x9800 0x0 0x0 0x3 &ipic 21 0x8
	398	0x9800 0x0 0x0 0x4 &ipic 22 0x8
1b3c5cda KG	399
1b3c5cda KG	400	/* IDSEL 0x15 AD21*/
cda13dd1 PG	401	0xa800 0x0 0x0 0x1 &ipic 20 0x8
	402	0xa800 0x0 0x0 0x2 &ipic 21 0x8
	403	0xa800 0x0 0x0 0x3 &ipic 22 0x8
	404	0xa800 0x0 0x0 0x4 &ipic 23 0x8
1b3c5cda KG	405
1b3c5cda KG	406	/* IDSEL 0x16 AD22*/
cda13dd1 PG	407	0xb000 0x0 0x0 0x1 &ipic 23 0x8
	408	0xb000 0x0 0x0 0x2 &ipic 20 0x8
	409	0xb000 0x0 0x0 0x3 &ipic 21 0x8
	410	0xb000 0x0 0x0 0x4 &ipic 22 0x8
1b3c5cda KG	411
1b3c5cda KG	412	/* IDSEL 0x17 AD23*/
cda13dd1 PG	413	0xb800 0x0 0x0 0x1 &ipic 22 0x8
	414	0xb800 0x0 0x0 0x2 &ipic 23 0x8
	415	0xb800 0x0 0x0 0x3 &ipic 20 0x8
	416	0xb800 0x0 0x0 0x4 &ipic 21 0x8
1b3c5cda KG	417
1b3c5cda KG	418	/* IDSEL 0x18 AD24*/
cda13dd1 PG	419	0xc000 0x0 0x0 0x1 &ipic 21 0x8
	420	0xc000 0x0 0x0 0x2 &ipic 22 0x8
	421	0xc000 0x0 0x0 0x3 &ipic 23 0x8
	422	0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
	423	interrupt-parent = <&ipic>;
	424	interrupts = <66 0x8>;
	425	bus-range = <0x0 0x0>;
	426	ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
	427	0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
	428	0x01000000 0x0 0x00000000 0xd0000000 0x0 0x00100000>;
1b3c5cda KG	429	clock-frequency = <0>;
	430	#interrupt-cells = <1>;
	431	#size-cells = <2>;
	432	#address-cells = <3>;
5b70a097 JR	433	reg = <0xe0008500 0x100 /* internal registers */
5b70a097 JR	434	0xe0008300 0x8>; /* config space access registers */
1b3c5cda KG	435	compatible = "fsl,mpc8349-pci";
1b3c5cda KG	436	device_type = "pci";
1f8a25d4	437	sleep = <&pmc 0x00010000>;
1b3c5cda	438	};
18a1e4c3	439	};