[deliverable/linux.git] / arch / powerpc / boot / dts / mpc8377_rdb.dts

/*
 * MPC8377E RDB Device Tree Source
 *
 * Copyright 2007, 2008 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/dts-v1/;

/ {
	compatible = "fsl,mpc8377rdb";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
		pci1 = &pci1;
		pci2 = &pci2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8377@0 {
			device_type = "cpu";
			reg = <0x0>;
			d-cache-line-size = <32>;
			i-cache-line-size = <32>;
			d-cache-size = <32768>;
			i-cache-size = <32768>;
			timebase-frequency = <0>;
			bus-frequency = <0>;
			clock-frequency = <0>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x10000000>;	// 256MB at 0
	};

	localbus@e0005000 {
		#address-cells = <2>;
		#size-cells = <1>;
		compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
		reg = <0xe0005000 0x1000>;
		interrupts = <77 0x8>;
		interrupt-parent = <&ipic>;

		// CS0 and CS1 are swapped when
		// booting from nand, but the
		// addresses are the same.
		ranges = <0x0 0x0 0xfe000000 0x00800000
		          0x1 0x0 0xe0600000 0x00008000
		          0x2 0x0 0xf0000000 0x00020000
		          0x3 0x0 0xfa000000 0x00008000>;

		flash@0,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "cfi-flash";
			reg = <0x0 0x0 0x800000>;
			bank-width = <2>;
			device-width = <1>;
		};

		nand@1,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8377-fcm-nand",
			             "fsl,elbc-fcm-nand";
			reg = <0x1 0x0 0x8000>;

			u-boot@0 {
				reg = <0x0 0x100000>;
				read-only;
			};

			kernel@100000 {
				reg = <0x100000 0x300000>;
			};
			fs@400000 {
				reg = <0x400000 0x1c00000>;
			};
		};
	};

	immr@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		compatible = "simple-bus";
		ranges = <0x0 0xe0000000 0x00100000>;
		reg = <0xe0000000 0x00000200>;
		bus-frequency = <0>;

		wdt@200 {
			device_type = "watchdog";
			compatible = "mpc83xx_wdt";
			reg = <0x200 0x100>;
		};

		gpio1: gpio-controller@c00 {
			#gpio-cells = <2>;
			compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
			reg = <0xc00 0x100>;
			interrupts = <74 0x8>;
			interrupt-parent = <&ipic>;
			gpio-controller;
		};

		gpio2: gpio-controller@d00 {
			#gpio-cells = <2>;
			compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
			reg = <0xd00 0x100>;
			interrupts = <75 0x8>;
			interrupt-parent = <&ipic>;
			gpio-controller;
		};

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <14 0x8>;
			interrupt-parent = <&ipic>;
			dfsrr;

			at24@50 {
				compatible = "at24,24c256";
				reg = <0x50>;
			};

			rtc@68 {
				compatible = "dallas,ds1339";
				reg = <0x68>;
			};

			mcu_pio: mcu@a {
				#gpio-cells = <2>;
				compatible = "fsl,mc9s08qg8-mpc8377erdb",
					     "fsl,mcu-mpc8349emitx";
				reg = <0x0a>;
				gpio-controller;
			};
		};

		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <15 0x8>;
			interrupt-parent = <&ipic>;
			dfsrr;
		};

		spi@7000 {
			cell-index = <0>;
			compatible = "fsl,spi";
			reg = <0x7000 0x1000>;
			interrupts = <16 0x8>;
			interrupt-parent = <&ipic>;
			mode = "cpu";
		};

		dma@82a8 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8377-dma", "fsl,elo-dma";
			reg = <0x82a8 4>;
			ranges = <0 0x8100 0x1a8>;
			interrupt-parent = <&ipic>;
			interrupts = <71 8>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
				reg = <0 0x80>;
				cell-index = <0>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
			dma-channel@80 {
				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
			dma-channel@100 {
				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
			dma-channel@180 {
				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
				reg = <0x180 0x28>;
				cell-index = <3>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
		};

		usb@23000 {
			compatible = "fsl-usb2-dr";
			reg = <0x23000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupt-parent = <&ipic>;
			interrupts = <38 0x8>;
			phy_type = "ulpi";
		};

		mdio@24520 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,gianfar-mdio";
			reg = <0x24520 0x20>;
			phy2: ethernet-phy@2 {
				interrupt-parent = <&ipic>;
				interrupts = <17 0x8>;
				reg = <0x2>;
				device_type = "ethernet-phy";
			};
			tbi0: tbi-phy@11 {
				reg = <0x11>;
				device_type = "tbi-phy";
			};
		};

		mdio@25520 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,gianfar-tbi";
			reg = <0x25520 0x20>;

			tbi1: tbi-phy@11 {
				reg = <0x11>;
				device_type = "tbi-phy";
			};
		};


		enet0: ethernet@24000 {
			cell-index = <0>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x24000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <32 0x8 33 0x8 34 0x8>;
			phy-connection-type = "mii";
			interrupt-parent = <&ipic>;
			tbi-handle = <&tbi0>;
			phy-handle = <&phy2>;
		};

		enet1: ethernet@25000 {
			cell-index = <1>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x25000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <35 0x8 36 0x8 37 0x8>;
			phy-connection-type = "mii";
			interrupt-parent = <&ipic>;
			fixed-link = <1 1 1000 0 0>;
			tbi-handle = <&tbi1>;
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4500 0x100>;
			clock-frequency = <0>;
			interrupts = <9 0x8>;
			interrupt-parent = <&ipic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4600 0x100>;
			clock-frequency = <0>;
			interrupts = <10 0x8>;
			interrupt-parent = <&ipic>;
		};

		crypto@30000 {
			compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
				     "fsl,sec2.1", "fsl,sec2.0";
			reg = <0x30000 0x10000>;
			interrupts = <11 0x8>;
			interrupt-parent = <&ipic>;
			fsl,num-channels = <4>;
			fsl,channel-fifo-len = <24>;
			fsl,exec-units-mask = <0x9fe>;
			fsl,descriptor-types-mask = <0x3ab0ebf>;
		};

		sata@18000 {
			compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
			reg = <0x18000 0x1000>;
			interrupts = <44 0x8>;
			interrupt-parent = <&ipic>;
		};

		sata@19000 {
			compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
			reg = <0x19000 0x1000>;
			interrupts = <45 0x8>;
			interrupt-parent = <&ipic>;
		};

		/* IPIC
		 * interrupts cell = <intr #, sense>
		 * sense values match linux IORESOURCE_IRQ_* defines:
		 * sense == 8: Level, low assertion
		 * sense == 2: Edge, high-to-low change
		 */
		ipic: interrupt-controller@700 {
			compatible = "fsl,ipic";
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x700 0x100>;
		};
	};

	pci0: pci@e0008500 {
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <
				/* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */

				/* IDSEL AD14 IRQ6 inta */
				 0x7000 0x0 0x0 0x1 &ipic 22 0x8

				/* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */
				 0x7800 0x0 0x0 0x1 &ipic 21 0x8
				 0x7800 0x0 0x0 0x2 &ipic 22 0x8
				 0x7800 0x0 0x0 0x4 &ipic 23 0x8

				/* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/
				 0xE000 0x0 0x0 0x1 &ipic 23 0x8
				 0xE000 0x0 0x0 0x2 &ipic 21 0x8
				 0xE000 0x0 0x0 0x3 &ipic 22 0x8>;
		interrupt-parent = <&ipic>;
		interrupts = <66 0x8>;
		bus-range = <0 0>;
		ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
		          0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
		          0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
		clock-frequency = <66666666>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0008500 0x100		/* internal registers */
		       0xe0008300 0x8>;		/* config space access registers */
		compatible = "fsl,mpc8349-pci";
		device_type = "pci";
	};

	pci1: pcie@e0009000 {
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		device_type = "pci";
		compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
		reg = <0xe0009000 0x00001000>;
		ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
		          0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
		bus-range = <0 255>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <0 0 0 1 &ipic 1 8
				 0 0 0 2 &ipic 1 8
				 0 0 0 3 &ipic 1 8
				 0 0 0 4 &ipic 1 8>;
		clock-frequency = <0>;

		pcie@0 {
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			reg = <0 0 0 0 0>;
			ranges = <0x02000000 0 0xa8000000
				  0x02000000 0 0xa8000000
				  0 0x10000000
				  0x01000000 0 0x00000000
				  0x01000000 0 0x00000000
				  0 0x00800000>;
		};
	};

	pci2: pcie@e000a000 {
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		device_type = "pci";
		compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
		reg = <0xe000a000 0x00001000>;
		ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
			  0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
		bus-range = <0 255>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <0 0 0 1 &ipic 2 8
				 0 0 0 2 &ipic 2 8
				 0 0 0 3 &ipic 2 8
				 0 0 0 4 &ipic 2 8>;
		clock-frequency = <0>;

		pcie@0 {
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			reg = <0 0 0 0 0>;
			ranges = <0x02000000 0 0xc8000000
				  0x02000000 0 0xc8000000
				  0 0x10000000
				  0x01000000 0 0x00000000
				  0x01000000 0 0x00000000
				  0 0x00800000>;
		};
	};
};
Commit	Line	Data
23dd1cbf KP	1	/*
	2	* MPC8377E RDB Device Tree Source
	3	*
	4	* Copyright 2007, 2008 Freescale Semiconductor Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*/
	11
	12	/dts-v1/;
	13
	14	/ {
3b29dade	15	compatible = "fsl,mpc8377rdb";
23dd1cbf KP	16	#address-cells = <1>;
	17	#size-cells = <1>;
	18
	19	aliases {
	20	ethernet0 = &enet0;
	21	ethernet1 = &enet1;
	22	serial0 = &serial0;
	23	serial1 = &serial1;
	24	pci0 = &pci0;
0585a155 AV	25	pci1 = &pci1;
0585a155 AV	26	pci2 = &pci2;
23dd1cbf KP	27	};
	28
	29	cpus {
	30	#address-cells = <1>;
	31	#size-cells = <0>;
	32
	33	PowerPC,8377@0 {
	34	device_type = "cpu";
cda13dd1	35	reg = <0x0>;
23dd1cbf KP	36	d-cache-line-size = <32>;
	37	i-cache-line-size = <32>;
	38	d-cache-size = <32768>;
	39	i-cache-size = <32768>;
	40	timebase-frequency = <0>;
	41	bus-frequency = <0>;
	42	clock-frequency = <0>;
	43	};
	44	};
	45
	46	memory {
	47	device_type = "memory";
	48	reg = <0x00000000 0x10000000>; // 256MB at 0
	49	};
	50
	51	localbus@e0005000 {
	52	#address-cells = <2>;
	53	#size-cells = <1>;
	54	compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
	55	reg = <0xe0005000 0x1000>;
cda13dd1	56	interrupts = <77 0x8>;
23dd1cbf KP	57	interrupt-parent = <&ipic>;
	58
	59	// CS0 and CS1 are swapped when
	60	// booting from nand, but the
	61	// addresses are the same.
cda13dd1 PG	62	ranges = <0x0 0x0 0xfe000000 0x00800000
	63	0x1 0x0 0xe0600000 0x00008000
	64	0x2 0x0 0xf0000000 0x00020000
	65	0x3 0x0 0xfa000000 0x00008000>;
23dd1cbf KP	66
	67	flash@0,0 {
	68	#address-cells = <1>;
	69	#size-cells = <1>;
	70	compatible = "cfi-flash";
cda13dd1	71	reg = <0x0 0x0 0x800000>;
23dd1cbf KP	72	bank-width = <2>;
	73	device-width = <1>;
	74	};
	75
	76	nand@1,0 {
	77	#address-cells = <1>;
	78	#size-cells = <1>;
	79	compatible = "fsl,mpc8377-fcm-nand",
	80	"fsl,elbc-fcm-nand";
cda13dd1	81	reg = <0x1 0x0 0x8000>;
23dd1cbf KP	82
	83	u-boot@0 {
	84	reg = <0x0 0x100000>;
	85	read-only;
	86	};
	87
	88	kernel@100000 {
	89	reg = <0x100000 0x300000>;
	90	};
	91	fs@400000 {
	92	reg = <0x400000 0x1c00000>;
	93	};
	94	};
	95	};
	96
	97	immr@e0000000 {
	98	#address-cells = <1>;
	99	#size-cells = <1>;
	100	device_type = "soc";
	101	compatible = "simple-bus";
cda13dd1	102	ranges = <0x0 0xe0000000 0x00100000>;
23dd1cbf KP	103	reg = <0xe0000000 0x00000200>;
	104	bus-frequency = <0>;
	105
	106	wdt@200 {
	107	device_type = "watchdog";
	108	compatible = "mpc83xx_wdt";
	109	reg = <0x200 0x100>;
	110	};
	111
9e7d95c1 RP	112	gpio1: gpio-controller@c00 {
	113	#gpio-cells = <2>;
	114	compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
	115	reg = <0xc00 0x100>;
	116	interrupts = <74 0x8>;
	117	interrupt-parent = <&ipic>;
	118	gpio-controller;
	119	};
	120
	121	gpio2: gpio-controller@d00 {
	122	#gpio-cells = <2>;
	123	compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
	124	reg = <0xd00 0x100>;
	125	interrupts = <75 0x8>;
	126	interrupt-parent = <&ipic>;
	127	gpio-controller;
	128	};
	129
23dd1cbf KP	130	i2c@3000 {
	131	#address-cells = <1>;
	132	#size-cells = <0>;
	133	cell-index = <0>;
	134	compatible = "fsl-i2c";
	135	reg = <0x3000 0x100>;
cda13dd1 PG	136	interrupts = <14 0x8>;
cda13dd1 PG	137	interrupt-parent = <&ipic>;
23dd1cbf	138	dfsrr;
f7a0be45 RP	139
	140	at24@50 {
	141	compatible = "at24,24c256";
	142	reg = <0x50>;
	143	};
	144
23dd1cbf	145	rtc@68 {
23dd1cbf KP	146	compatible = "dallas,ds1339";
	147	reg = <0x68>;
	148	};
44274698 AV	149
	150	mcu_pio: mcu@a {
	151	#gpio-cells = <2>;
	152	compatible = "fsl,mc9s08qg8-mpc8377erdb",
	153	"fsl,mcu-mpc8349emitx";
	154	reg = <0x0a>;
	155	gpio-controller;
	156	};
23dd1cbf KP	157	};
	158
	159	i2c@3100 {
	160	#address-cells = <1>;
	161	#size-cells = <0>;
	162	cell-index = <1>;
	163	compatible = "fsl-i2c";
	164	reg = <0x3100 0x100>;
cda13dd1 PG	165	interrupts = <15 0x8>;
cda13dd1 PG	166	interrupt-parent = <&ipic>;
23dd1cbf KP	167	dfsrr;
	168	};
	169
	170	spi@7000 {
	171	cell-index = <0>;
	172	compatible = "fsl,spi";
	173	reg = <0x7000 0x1000>;
cda13dd1 PG	174	interrupts = <16 0x8>;
cda13dd1 PG	175	interrupt-parent = <&ipic>;
23dd1cbf KP	176	mode = "cpu";
	177	};
	178
dee80553 KG	179	dma@82a8 {
	180	#address-cells = <1>;
	181	#size-cells = <1>;
	182	compatible = "fsl,mpc8377-dma", "fsl,elo-dma";
	183	reg = <0x82a8 4>;
	184	ranges = <0 0x8100 0x1a8>;
	185	interrupt-parent = <&ipic>;
	186	interrupts = <71 8>;
	187	cell-index = <0>;
	188	dma-channel@0 {
	189	compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
	190	reg = <0 0x80>;
aeb42762	191	cell-index = <0>;
dee80553 KG	192	interrupt-parent = <&ipic>;
	193	interrupts = <71 8>;
	194	};
	195	dma-channel@80 {
	196	compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
	197	reg = <0x80 0x80>;
aeb42762	198	cell-index = <1>;
dee80553 KG	199	interrupt-parent = <&ipic>;
	200	interrupts = <71 8>;
	201	};
	202	dma-channel@100 {
	203	compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
	204	reg = <0x100 0x80>;
aeb42762	205	cell-index = <2>;
dee80553 KG	206	interrupt-parent = <&ipic>;
	207	interrupts = <71 8>;
	208	};
	209	dma-channel@180 {
	210	compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
	211	reg = <0x180 0x28>;
aeb42762	212	cell-index = <3>;
dee80553 KG	213	interrupt-parent = <&ipic>;
	214	interrupts = <71 8>;
	215	};
	216	};
	217
23dd1cbf KP	218	usb@23000 {
	219	compatible = "fsl-usb2-dr";
	220	reg = <0x23000 0x1000>;
	221	#address-cells = <1>;
	222	#size-cells = <0>;
cda13dd1 PG	223	interrupt-parent = <&ipic>;
cda13dd1 PG	224	interrupts = <38 0x8>;
8e8ff3a3	225	phy_type = "ulpi";
23dd1cbf KP	226	};
	227
	228	mdio@24520 {
	229	#address-cells = <1>;
	230	#size-cells = <0>;
	231	compatible = "fsl,gianfar-mdio";
	232	reg = <0x24520 0x20>;
	233	phy2: ethernet-phy@2 {
cda13dd1 PG	234	interrupt-parent = <&ipic>;
	235	interrupts = <17 0x8>;
	236	reg = <0x2>;
23dd1cbf KP	237	device_type = "ethernet-phy";
23dd1cbf KP	238	};
b31a1d8b AF	239	tbi0: tbi-phy@11 {
	240	reg = <0x11>;
	241	device_type = "tbi-phy";
	242	};
	243	};
	244
	245	mdio@25520 {
	246	#address-cells = <1>;
	247	#size-cells = <0>;
	248	compatible = "fsl,gianfar-tbi";
	249	reg = <0x25520 0x20>;
	250
	251	tbi1: tbi-phy@11 {
	252	reg = <0x11>;
	253	device_type = "tbi-phy";
	254	};
23dd1cbf KP	255	};
23dd1cbf KP	256
b31a1d8b	257
23dd1cbf KP	258	enet0: ethernet@24000 {
	259	cell-index = <0>;
	260	device_type = "network";
	261	model = "eTSEC";
	262	compatible = "gianfar";
	263	reg = <0x24000 0x1000>;
	264	local-mac-address = [ 00 00 00 00 00 00 ];
cda13dd1	265	interrupts = <32 0x8 33 0x8 34 0x8>;
23dd1cbf	266	phy-connection-type = "mii";
cda13dd1	267	interrupt-parent = <&ipic>;
b31a1d8b	268	tbi-handle = <&tbi0>;
cda13dd1	269	phy-handle = <&phy2>;
23dd1cbf KP	270	};
	271
	272	enet1: ethernet@25000 {
	273	cell-index = <1>;
	274	device_type = "network";
	275	model = "eTSEC";
	276	compatible = "gianfar";
	277	reg = <0x25000 0x1000>;
	278	local-mac-address = [ 00 00 00 00 00 00 ];
cda13dd1	279	interrupts = <35 0x8 36 0x8 37 0x8>;
23dd1cbf	280	phy-connection-type = "mii";
cda13dd1	281	interrupt-parent = <&ipic>;
f17c6323	282	fixed-link = <1 1 1000 0 0>;
b31a1d8b	283	tbi-handle = <&tbi1>;
23dd1cbf KP	284	};
	285
	286	serial0: serial@4500 {
	287	cell-index = <0>;
	288	device_type = "serial";
	289	compatible = "ns16550";
	290	reg = <0x4500 0x100>;
	291	clock-frequency = <0>;
cda13dd1 PG	292	interrupts = <9 0x8>;
cda13dd1 PG	293	interrupt-parent = <&ipic>;
23dd1cbf KP	294	};
	295
	296	serial1: serial@4600 {
	297	cell-index = <1>;
	298	device_type = "serial";
	299	compatible = "ns16550";
	300	reg = <0x4600 0x100>;
	301	clock-frequency = <0>;
cda13dd1 PG	302	interrupts = <10 0x8>;
cda13dd1 PG	303	interrupt-parent = <&ipic>;
23dd1cbf KP	304	};
	305
	306	crypto@30000 {
3fd44736 KP	307	compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
3fd44736 KP	308	"fsl,sec2.1", "fsl,sec2.0";
23dd1cbf	309	reg = <0x30000 0x10000>;
cda13dd1 PG	310	interrupts = <11 0x8>;
cda13dd1 PG	311	interrupt-parent = <&ipic>;
3fd44736 KP	312	fsl,num-channels = <4>;
	313	fsl,channel-fifo-len = <24>;
	314	fsl,exec-units-mask = <0x9fe>;
	315	fsl,descriptor-types-mask = <0x3ab0ebf>;
23dd1cbf KP	316	};
	317
	318	sata@18000 {
	319	compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
	320	reg = <0x18000 0x1000>;
cda13dd1 PG	321	interrupts = <44 0x8>;
cda13dd1 PG	322	interrupt-parent = <&ipic>;
23dd1cbf KP	323	};
	324
	325	sata@19000 {
	326	compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
	327	reg = <0x19000 0x1000>;
cda13dd1 PG	328	interrupts = <45 0x8>;
cda13dd1 PG	329	interrupt-parent = <&ipic>;
23dd1cbf KP	330	};
	331
	332	/* IPIC
	333	* interrupts cell = <intr #, sense>
	334	* sense values match linux IORESOURCE_IRQ_* defines:
	335	* sense == 8: Level, low assertion
	336	* sense == 2: Edge, high-to-low change
	337	*/
	338	ipic: interrupt-controller@700 {
	339	compatible = "fsl,ipic";
	340	interrupt-controller;
	341	#address-cells = <0>;
	342	#interrupt-cells = <2>;
	343	reg = <0x700 0x100>;
	344	};
	345	};
	346
	347	pci0: pci@e0008500 {
	348	interrupt-map-mask = <0xf800 0 0 7>;
	349	interrupt-map = <
	350	/* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
	351
	352	/* IDSEL AD14 IRQ6 inta */
cda13dd1	353	0x7000 0x0 0x0 0x1 &ipic 22 0x8
23dd1cbf KP	354
23dd1cbf KP	355	/* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */
cda13dd1 PG	356	0x7800 0x0 0x0 0x1 &ipic 21 0x8
	357	0x7800 0x0 0x0 0x2 &ipic 22 0x8
	358	0x7800 0x0 0x0 0x4 &ipic 23 0x8
23dd1cbf KP	359
23dd1cbf KP	360	/* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/
cda13dd1 PG	361	0xE000 0x0 0x0 0x1 &ipic 23 0x8
	362	0xE000 0x0 0x0 0x2 &ipic 21 0x8
	363	0xE000 0x0 0x0 0x3 &ipic 22 0x8>;
	364	interrupt-parent = <&ipic>;
	365	interrupts = <66 0x8>;
23dd1cbf	366	bus-range = <0 0>;
cda13dd1 PG	367	ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
	368	0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
	369	0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
23dd1cbf KP	370	clock-frequency = <66666666>;
	371	#interrupt-cells = <1>;
	372	#size-cells = <2>;
	373	#address-cells = <3>;
5b70a097 JR	374	reg = <0xe0008500 0x100 /* internal registers */
5b70a097 JR	375	0xe0008300 0x8>; /* config space access registers */
23dd1cbf KP	376	compatible = "fsl,mpc8349-pci";
	377	device_type = "pci";
	378	};
0585a155 AV	379
	380	pci1: pcie@e0009000 {
	381	#address-cells = <3>;
	382	#size-cells = <2>;
	383	#interrupt-cells = <1>;
	384	device_type = "pci";
	385	compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
	386	reg = <0xe0009000 0x00001000>;
	387	ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
	388	0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
	389	bus-range = <0 255>;
	390	interrupt-map-mask = <0xf800 0 0 7>;
	391	interrupt-map = <0 0 0 1 &ipic 1 8
	392	0 0 0 2 &ipic 1 8
	393	0 0 0 3 &ipic 1 8
	394	0 0 0 4 &ipic 1 8>;
	395	clock-frequency = <0>;
	396
	397	pcie@0 {
	398	#address-cells = <3>;
	399	#size-cells = <2>;
	400	device_type = "pci";
	401	reg = <0 0 0 0 0>;
	402	ranges = <0x02000000 0 0xa8000000
	403	0x02000000 0 0xa8000000
	404	0 0x10000000
	405	0x01000000 0 0x00000000
	406	0x01000000 0 0x00000000
	407	0 0x00800000>;
	408	};
	409	};
	410
	411	pci2: pcie@e000a000 {
	412	#address-cells = <3>;
	413	#size-cells = <2>;
	414	#interrupt-cells = <1>;
	415	device_type = "pci";
	416	compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
	417	reg = <0xe000a000 0x00001000>;
	418	ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
	419	0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
	420	bus-range = <0 255>;
	421	interrupt-map-mask = <0xf800 0 0 7>;
	422	interrupt-map = <0 0 0 1 &ipic 2 8
	423	0 0 0 2 &ipic 2 8
	424	0 0 0 3 &ipic 2 8
	425	0 0 0 4 &ipic 2 8>;
	426	clock-frequency = <0>;
	427
	428	pcie@0 {
	429	#address-cells = <3>;
	430	#size-cells = <2>;
	431	device_type = "pci";
	432	reg = <0 0 0 0 0>;
	433	ranges = <0x02000000 0 0xc8000000
	434	0x02000000 0 0xc8000000
	435	0 0x10000000
	436	0x01000000 0 0x00000000
	437	0x01000000 0 0x00000000
	438	0 0x00800000>;
	439	};
	440	};
23dd1cbf	441	};