[deliverable/linux.git] / arch / powerpc / boot / dts / mpc8377_rdb.dts

/*
 * MPC8377E RDB Device Tree Source
 *
 * Copyright 2007, 2008 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/dts-v1/;

/ {
	compatible = "fsl,mpc8377rdb";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
		pci1 = &pci1;
		pci2 = &pci2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8377@0 {
			device_type = "cpu";
			reg = <0x0>;
			d-cache-line-size = <32>;
			i-cache-line-size = <32>;
			d-cache-size = <32768>;
			i-cache-size = <32768>;
			timebase-frequency = <0>;
			bus-frequency = <0>;
			clock-frequency = <0>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x10000000>;	// 256MB at 0
	};

	localbus@e0005000 {
		#address-cells = <2>;
		#size-cells = <1>;
		compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
		reg = <0xe0005000 0x1000>;
		interrupts = <77 0x8>;
		interrupt-parent = <&ipic>;

		// CS0 and CS1 are swapped when
		// booting from nand, but the
		// addresses are the same.
		ranges = <0x0 0x0 0xfe000000 0x00800000
		          0x1 0x0 0xe0600000 0x00008000
		          0x2 0x0 0xf0000000 0x00020000
		          0x3 0x0 0xfa000000 0x00008000>;

		flash@0,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "cfi-flash";
			reg = <0x0 0x0 0x800000>;
			bank-width = <2>;
			device-width = <1>;
		};

		nand@1,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8377-fcm-nand",
			             "fsl,elbc-fcm-nand";
			reg = <0x1 0x0 0x8000>;

			u-boot@0 {
				reg = <0x0 0x100000>;
				read-only;
			};

			kernel@100000 {
				reg = <0x100000 0x300000>;
			};
			fs@400000 {
				reg = <0x400000 0x1c00000>;
			};
		};
	};

	immr@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		compatible = "simple-bus";
		ranges = <0x0 0xe0000000 0x00100000>;
		reg = <0xe0000000 0x00000200>;
		bus-frequency = <0>;

		wdt@200 {
			device_type = "watchdog";
			compatible = "mpc83xx_wdt";
			reg = <0x200 0x100>;
		};

		gpio1: gpio-controller@c00 {
			#gpio-cells = <2>;
			compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
			reg = <0xc00 0x100>;
			interrupts = <74 0x8>;
			interrupt-parent = <&ipic>;
			gpio-controller;
		};

		gpio2: gpio-controller@d00 {
			#gpio-cells = <2>;
			compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
			reg = <0xd00 0x100>;
			interrupts = <75 0x8>;
			interrupt-parent = <&ipic>;
			gpio-controller;
		};

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <14 0x8>;
			interrupt-parent = <&ipic>;
			dfsrr;

			dtt@48 {
				compatible = "national,lm75";
				reg = <0x48>;
			};

			at24@50 {
				compatible = "at24,24c256";
				reg = <0x50>;
			};

			rtc@68 {
				compatible = "dallas,ds1339";
				reg = <0x68>;
			};

			mcu_pio: mcu@a {
				#gpio-cells = <2>;
				compatible = "fsl,mc9s08qg8-mpc8377erdb",
					     "fsl,mcu-mpc8349emitx";
				reg = <0x0a>;
				gpio-controller;
			};
		};

		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <15 0x8>;
			interrupt-parent = <&ipic>;
			dfsrr;
		};

		spi@7000 {
			cell-index = <0>;
			compatible = "fsl,spi";
			reg = <0x7000 0x1000>;
			interrupts = <16 0x8>;
			interrupt-parent = <&ipic>;
			mode = "cpu";
		};

		dma@82a8 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8377-dma", "fsl,elo-dma";
			reg = <0x82a8 4>;
			ranges = <0 0x8100 0x1a8>;
			interrupt-parent = <&ipic>;
			interrupts = <71 8>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
				reg = <0 0x80>;
				cell-index = <0>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
			dma-channel@80 {
				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
			dma-channel@100 {
				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
			dma-channel@180 {
				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
				reg = <0x180 0x28>;
				cell-index = <3>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
		};

		usb@23000 {
			compatible = "fsl-usb2-dr";
			reg = <0x23000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupt-parent = <&ipic>;
			interrupts = <38 0x8>;
			phy_type = "ulpi";
		};

		mdio@24520 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,gianfar-mdio";
			reg = <0x24520 0x20>;
			phy2: ethernet-phy@2 {
				interrupt-parent = <&ipic>;
				interrupts = <17 0x8>;
				reg = <0x2>;
				device_type = "ethernet-phy";
			};
			tbi0: tbi-phy@11 {
				reg = <0x11>;
				device_type = "tbi-phy";
			};
		};

		mdio@25520 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,gianfar-tbi";
			reg = <0x25520 0x20>;

			tbi1: tbi-phy@11 {
				reg = <0x11>;
				device_type = "tbi-phy";
			};
		};


		enet0: ethernet@24000 {
			cell-index = <0>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x24000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <32 0x8 33 0x8 34 0x8>;
			phy-connection-type = "mii";
			interrupt-parent = <&ipic>;
			tbi-handle = <&tbi0>;
			phy-handle = <&phy2>;
		};

		enet1: ethernet@25000 {
			cell-index = <1>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x25000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <35 0x8 36 0x8 37 0x8>;
			phy-connection-type = "mii";
			interrupt-parent = <&ipic>;
			fixed-link = <1 1 1000 0 0>;
			tbi-handle = <&tbi1>;
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4500 0x100>;
			clock-frequency = <0>;
			interrupts = <9 0x8>;
			interrupt-parent = <&ipic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4600 0x100>;
			clock-frequency = <0>;
			interrupts = <10 0x8>;
			interrupt-parent = <&ipic>;
		};

		crypto@30000 {
			compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
				     "fsl,sec2.1", "fsl,sec2.0";
			reg = <0x30000 0x10000>;
			interrupts = <11 0x8>;
			interrupt-parent = <&ipic>;
			fsl,num-channels = <4>;
			fsl,channel-fifo-len = <24>;
			fsl,exec-units-mask = <0x9fe>;
			fsl,descriptor-types-mask = <0x3ab0ebf>;
		};

		sdhci@2e000 {
			compatible = "fsl,mpc8377-esdhc", "fsl,mpc8379-esdhc";
			reg = <0x2e000 0x1000>;
			interrupts = <42 0x8>;
			interrupt-parent = <&ipic>;
			/* Filled in by U-Boot */
			clock-frequency = <0>;
		};

		sata@18000 {
			compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
			reg = <0x18000 0x1000>;
			interrupts = <44 0x8>;
			interrupt-parent = <&ipic>;
		};

		sata@19000 {
			compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
			reg = <0x19000 0x1000>;
			interrupts = <45 0x8>;
			interrupt-parent = <&ipic>;
		};

		/* IPIC
		 * interrupts cell = <intr #, sense>
		 * sense values match linux IORESOURCE_IRQ_* defines:
		 * sense == 8: Level, low assertion
		 * sense == 2: Edge, high-to-low change
		 */
		ipic: interrupt-controller@700 {
			compatible = "fsl,ipic";
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x700 0x100>;
		};
	};

	pci0: pci@e0008500 {
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <
				/* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */

				/* IDSEL AD14 IRQ6 inta */
				 0x7000 0x0 0x0 0x1 &ipic 22 0x8

				/* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */
				 0x7800 0x0 0x0 0x1 &ipic 21 0x8
				 0x7800 0x0 0x0 0x2 &ipic 22 0x8
				 0x7800 0x0 0x0 0x4 &ipic 23 0x8

				/* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/
				 0xE000 0x0 0x0 0x1 &ipic 23 0x8
				 0xE000 0x0 0x0 0x2 &ipic 21 0x8
				 0xE000 0x0 0x0 0x3 &ipic 22 0x8>;
		interrupt-parent = <&ipic>;
		interrupts = <66 0x8>;
		bus-range = <0 0>;
		ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
		          0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
		          0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
		clock-frequency = <66666666>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0008500 0x100		/* internal registers */
		       0xe0008300 0x8>;		/* config space access registers */
		compatible = "fsl,mpc8349-pci";
		device_type = "pci";
	};

	pci1: pcie@e0009000 {
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		device_type = "pci";
		compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
		reg = <0xe0009000 0x00001000>;
		ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
		          0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
		bus-range = <0 255>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <0 0 0 1 &ipic 1 8
				 0 0 0 2 &ipic 1 8
				 0 0 0 3 &ipic 1 8
				 0 0 0 4 &ipic 1 8>;
		clock-frequency = <0>;

		pcie@0 {
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			reg = <0 0 0 0 0>;
			ranges = <0x02000000 0 0xa8000000
				  0x02000000 0 0xa8000000
				  0 0x10000000
				  0x01000000 0 0x00000000
				  0x01000000 0 0x00000000
				  0 0x00800000>;
		};
	};

	pci2: pcie@e000a000 {
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		device_type = "pci";
		compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
		reg = <0xe000a000 0x00001000>;
		ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
			  0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
		bus-range = <0 255>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <0 0 0 1 &ipic 2 8
				 0 0 0 2 &ipic 2 8
				 0 0 0 3 &ipic 2 8
				 0 0 0 4 &ipic 2 8>;
		clock-frequency = <0>;

		pcie@0 {
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			reg = <0 0 0 0 0>;
			ranges = <0x02000000 0 0xc8000000
				  0x02000000 0 0xc8000000
				  0 0x10000000
				  0x01000000 0 0x00000000
				  0x01000000 0 0x00000000
				  0 0x00800000>;
		};
	};
};
Commit	Line	Data
23dd1cbf KP	1	/*
	2	* MPC8377E RDB Device Tree Source
	3	*
	4	* Copyright 2007, 2008 Freescale Semiconductor Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*/
	11
	12	/dts-v1/;
	13
	14	/ {
3b29dade	15	compatible = "fsl,mpc8377rdb";
23dd1cbf KP	16	#address-cells = <1>;
	17	#size-cells = <1>;
	18
	19	aliases {
	20	ethernet0 = &enet0;
	21	ethernet1 = &enet1;
	22	serial0 = &serial0;
	23	serial1 = &serial1;
	24	pci0 = &pci0;
0585a155 AV	25	pci1 = &pci1;
0585a155 AV	26	pci2 = &pci2;
23dd1cbf KP	27	};
	28
	29	cpus {
	30	#address-cells = <1>;
	31	#size-cells = <0>;
	32
	33	PowerPC,8377@0 {
	34	device_type = "cpu";
cda13dd1	35	reg = <0x0>;
23dd1cbf KP	36	d-cache-line-size = <32>;
	37	i-cache-line-size = <32>;
	38	d-cache-size = <32768>;
	39	i-cache-size = <32768>;
	40	timebase-frequency = <0>;
	41	bus-frequency = <0>;
	42	clock-frequency = <0>;
	43	};
	44	};
	45
	46	memory {
	47	device_type = "memory";
	48	reg = <0x00000000 0x10000000>; // 256MB at 0
	49	};
	50
	51	localbus@e0005000 {
	52	#address-cells = <2>;
	53	#size-cells = <1>;
	54	compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
	55	reg = <0xe0005000 0x1000>;
cda13dd1	56	interrupts = <77 0x8>;
23dd1cbf KP	57	interrupt-parent = <&ipic>;
	58
	59	// CS0 and CS1 are swapped when
	60	// booting from nand, but the
	61	// addresses are the same.
cda13dd1 PG	62	ranges = <0x0 0x0 0xfe000000 0x00800000
	63	0x1 0x0 0xe0600000 0x00008000
	64	0x2 0x0 0xf0000000 0x00020000
	65	0x3 0x0 0xfa000000 0x00008000>;
23dd1cbf KP	66
	67	flash@0,0 {
	68	#address-cells = <1>;
	69	#size-cells = <1>;
	70	compatible = "cfi-flash";
cda13dd1	71	reg = <0x0 0x0 0x800000>;
23dd1cbf KP	72	bank-width = <2>;
	73	device-width = <1>;
	74	};
	75
	76	nand@1,0 {
	77	#address-cells = <1>;
	78	#size-cells = <1>;
	79	compatible = "fsl,mpc8377-fcm-nand",
	80	"fsl,elbc-fcm-nand";
cda13dd1	81	reg = <0x1 0x0 0x8000>;
23dd1cbf KP	82
	83	u-boot@0 {
	84	reg = <0x0 0x100000>;
	85	read-only;
	86	};
	87
	88	kernel@100000 {
	89	reg = <0x100000 0x300000>;
	90	};
	91	fs@400000 {
	92	reg = <0x400000 0x1c00000>;
	93	};
	94	};
	95	};
	96
	97	immr@e0000000 {
	98	#address-cells = <1>;
	99	#size-cells = <1>;
	100	device_type = "soc";
	101	compatible = "simple-bus";
cda13dd1	102	ranges = <0x0 0xe0000000 0x00100000>;
23dd1cbf KP	103	reg = <0xe0000000 0x00000200>;
	104	bus-frequency = <0>;
	105
	106	wdt@200 {
	107	device_type = "watchdog";
	108	compatible = "mpc83xx_wdt";
	109	reg = <0x200 0x100>;
	110	};
	111
9e7d95c1 RP	112	gpio1: gpio-controller@c00 {
	113	#gpio-cells = <2>;
	114	compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
	115	reg = <0xc00 0x100>;
	116	interrupts = <74 0x8>;
	117	interrupt-parent = <&ipic>;
	118	gpio-controller;
	119	};
	120
	121	gpio2: gpio-controller@d00 {
	122	#gpio-cells = <2>;
	123	compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
	124	reg = <0xd00 0x100>;
	125	interrupts = <75 0x8>;
	126	interrupt-parent = <&ipic>;
	127	gpio-controller;
	128	};
	129
23dd1cbf KP	130	i2c@3000 {
	131	#address-cells = <1>;
	132	#size-cells = <0>;
	133	cell-index = <0>;
	134	compatible = "fsl-i2c";
	135	reg = <0x3000 0x100>;
cda13dd1 PG	136	interrupts = <14 0x8>;
cda13dd1 PG	137	interrupt-parent = <&ipic>;
23dd1cbf	138	dfsrr;
f7a0be45	139
960d82aa RP	140	dtt@48 {
	141	compatible = "national,lm75";
	142	reg = <0x48>;
	143	};
	144
f7a0be45 RP	145	at24@50 {
	146	compatible = "at24,24c256";
	147	reg = <0x50>;
	148	};
	149
23dd1cbf	150	rtc@68 {
23dd1cbf KP	151	compatible = "dallas,ds1339";
	152	reg = <0x68>;
	153	};
44274698 AV	154
	155	mcu_pio: mcu@a {
	156	#gpio-cells = <2>;
	157	compatible = "fsl,mc9s08qg8-mpc8377erdb",
	158	"fsl,mcu-mpc8349emitx";
	159	reg = <0x0a>;
	160	gpio-controller;
	161	};
23dd1cbf KP	162	};
	163
	164	i2c@3100 {
	165	#address-cells = <1>;
	166	#size-cells = <0>;
	167	cell-index = <1>;
	168	compatible = "fsl-i2c";
	169	reg = <0x3100 0x100>;
cda13dd1 PG	170	interrupts = <15 0x8>;
cda13dd1 PG	171	interrupt-parent = <&ipic>;
23dd1cbf KP	172	dfsrr;
	173	};
	174
	175	spi@7000 {
	176	cell-index = <0>;
	177	compatible = "fsl,spi";
	178	reg = <0x7000 0x1000>;
cda13dd1 PG	179	interrupts = <16 0x8>;
cda13dd1 PG	180	interrupt-parent = <&ipic>;
23dd1cbf KP	181	mode = "cpu";
	182	};
	183
dee80553 KG	184	dma@82a8 {
	185	#address-cells = <1>;
	186	#size-cells = <1>;
	187	compatible = "fsl,mpc8377-dma", "fsl,elo-dma";
	188	reg = <0x82a8 4>;
	189	ranges = <0 0x8100 0x1a8>;
	190	interrupt-parent = <&ipic>;
	191	interrupts = <71 8>;
	192	cell-index = <0>;
	193	dma-channel@0 {
	194	compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
	195	reg = <0 0x80>;
aeb42762	196	cell-index = <0>;
dee80553 KG	197	interrupt-parent = <&ipic>;
	198	interrupts = <71 8>;
	199	};
	200	dma-channel@80 {
	201	compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
	202	reg = <0x80 0x80>;
aeb42762	203	cell-index = <1>;
dee80553 KG	204	interrupt-parent = <&ipic>;
	205	interrupts = <71 8>;
	206	};
	207	dma-channel@100 {
	208	compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
	209	reg = <0x100 0x80>;
aeb42762	210	cell-index = <2>;
dee80553 KG	211	interrupt-parent = <&ipic>;
	212	interrupts = <71 8>;
	213	};
	214	dma-channel@180 {
	215	compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
	216	reg = <0x180 0x28>;
aeb42762	217	cell-index = <3>;
dee80553 KG	218	interrupt-parent = <&ipic>;
	219	interrupts = <71 8>;
	220	};
	221	};
	222
23dd1cbf KP	223	usb@23000 {
	224	compatible = "fsl-usb2-dr";
	225	reg = <0x23000 0x1000>;
	226	#address-cells = <1>;
	227	#size-cells = <0>;
cda13dd1 PG	228	interrupt-parent = <&ipic>;
cda13dd1 PG	229	interrupts = <38 0x8>;
8e8ff3a3	230	phy_type = "ulpi";
23dd1cbf KP	231	};
	232
	233	mdio@24520 {
	234	#address-cells = <1>;
	235	#size-cells = <0>;
	236	compatible = "fsl,gianfar-mdio";
	237	reg = <0x24520 0x20>;
	238	phy2: ethernet-phy@2 {
cda13dd1 PG	239	interrupt-parent = <&ipic>;
	240	interrupts = <17 0x8>;
	241	reg = <0x2>;
23dd1cbf KP	242	device_type = "ethernet-phy";
23dd1cbf KP	243	};
b31a1d8b AF	244	tbi0: tbi-phy@11 {
	245	reg = <0x11>;
	246	device_type = "tbi-phy";
	247	};
	248	};
	249
	250	mdio@25520 {
	251	#address-cells = <1>;
	252	#size-cells = <0>;
	253	compatible = "fsl,gianfar-tbi";
	254	reg = <0x25520 0x20>;
	255
	256	tbi1: tbi-phy@11 {
	257	reg = <0x11>;
	258	device_type = "tbi-phy";
	259	};
23dd1cbf KP	260	};
23dd1cbf KP	261
b31a1d8b	262
23dd1cbf KP	263	enet0: ethernet@24000 {
	264	cell-index = <0>;
	265	device_type = "network";
	266	model = "eTSEC";
	267	compatible = "gianfar";
	268	reg = <0x24000 0x1000>;
	269	local-mac-address = [ 00 00 00 00 00 00 ];
cda13dd1	270	interrupts = <32 0x8 33 0x8 34 0x8>;
23dd1cbf	271	phy-connection-type = "mii";
cda13dd1	272	interrupt-parent = <&ipic>;
b31a1d8b	273	tbi-handle = <&tbi0>;
cda13dd1	274	phy-handle = <&phy2>;
23dd1cbf KP	275	};
	276
	277	enet1: ethernet@25000 {
	278	cell-index = <1>;
	279	device_type = "network";
	280	model = "eTSEC";
	281	compatible = "gianfar";
	282	reg = <0x25000 0x1000>;
	283	local-mac-address = [ 00 00 00 00 00 00 ];
cda13dd1	284	interrupts = <35 0x8 36 0x8 37 0x8>;
23dd1cbf	285	phy-connection-type = "mii";
cda13dd1	286	interrupt-parent = <&ipic>;
f17c6323	287	fixed-link = <1 1 1000 0 0>;
b31a1d8b	288	tbi-handle = <&tbi1>;
23dd1cbf KP	289	};
	290
	291	serial0: serial@4500 {
	292	cell-index = <0>;
	293	device_type = "serial";
	294	compatible = "ns16550";
	295	reg = <0x4500 0x100>;
	296	clock-frequency = <0>;
cda13dd1 PG	297	interrupts = <9 0x8>;
cda13dd1 PG	298	interrupt-parent = <&ipic>;
23dd1cbf KP	299	};
	300
	301	serial1: serial@4600 {
	302	cell-index = <1>;
	303	device_type = "serial";
	304	compatible = "ns16550";
	305	reg = <0x4600 0x100>;
	306	clock-frequency = <0>;
cda13dd1 PG	307	interrupts = <10 0x8>;
cda13dd1 PG	308	interrupt-parent = <&ipic>;
23dd1cbf KP	309	};
	310
	311	crypto@30000 {
3fd44736 KP	312	compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
3fd44736 KP	313	"fsl,sec2.1", "fsl,sec2.0";
23dd1cbf	314	reg = <0x30000 0x10000>;
cda13dd1 PG	315	interrupts = <11 0x8>;
cda13dd1 PG	316	interrupt-parent = <&ipic>;
3fd44736 KP	317	fsl,num-channels = <4>;
	318	fsl,channel-fifo-len = <24>;
	319	fsl,exec-units-mask = <0x9fe>;
	320	fsl,descriptor-types-mask = <0x3ab0ebf>;
23dd1cbf KP	321	};
23dd1cbf KP	322
a0e8618c AV	323	sdhci@2e000 {
	324	compatible = "fsl,mpc8377-esdhc", "fsl,mpc8379-esdhc";
	325	reg = <0x2e000 0x1000>;
	326	interrupts = <42 0x8>;
	327	interrupt-parent = <&ipic>;
	328	/* Filled in by U-Boot */
	329	clock-frequency = <0>;
	330	};
	331
23dd1cbf KP	332	sata@18000 {
	333	compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
	334	reg = <0x18000 0x1000>;
cda13dd1 PG	335	interrupts = <44 0x8>;
cda13dd1 PG	336	interrupt-parent = <&ipic>;
23dd1cbf KP	337	};
	338
	339	sata@19000 {
	340	compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
	341	reg = <0x19000 0x1000>;
cda13dd1 PG	342	interrupts = <45 0x8>;
cda13dd1 PG	343	interrupt-parent = <&ipic>;
23dd1cbf KP	344	};
	345
	346	/* IPIC
	347	* interrupts cell = <intr #, sense>
	348	* sense values match linux IORESOURCE_IRQ_* defines:
	349	* sense == 8: Level, low assertion
	350	* sense == 2: Edge, high-to-low change
	351	*/
	352	ipic: interrupt-controller@700 {
	353	compatible = "fsl,ipic";
	354	interrupt-controller;
	355	#address-cells = <0>;
	356	#interrupt-cells = <2>;
	357	reg = <0x700 0x100>;
	358	};
	359	};
	360
	361	pci0: pci@e0008500 {
	362	interrupt-map-mask = <0xf800 0 0 7>;
	363	interrupt-map = <
	364	/* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
	365
	366	/* IDSEL AD14 IRQ6 inta */
cda13dd1	367	0x7000 0x0 0x0 0x1 &ipic 22 0x8
23dd1cbf KP	368
23dd1cbf KP	369	/* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */
cda13dd1 PG	370	0x7800 0x0 0x0 0x1 &ipic 21 0x8
	371	0x7800 0x0 0x0 0x2 &ipic 22 0x8
	372	0x7800 0x0 0x0 0x4 &ipic 23 0x8
23dd1cbf KP	373
23dd1cbf KP	374	/* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/
cda13dd1 PG	375	0xE000 0x0 0x0 0x1 &ipic 23 0x8
	376	0xE000 0x0 0x0 0x2 &ipic 21 0x8
	377	0xE000 0x0 0x0 0x3 &ipic 22 0x8>;
	378	interrupt-parent = <&ipic>;
	379	interrupts = <66 0x8>;
23dd1cbf	380	bus-range = <0 0>;
cda13dd1 PG	381	ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
	382	0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
	383	0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
23dd1cbf KP	384	clock-frequency = <66666666>;
	385	#interrupt-cells = <1>;
	386	#size-cells = <2>;
	387	#address-cells = <3>;
5b70a097 JR	388	reg = <0xe0008500 0x100 /* internal registers */
5b70a097 JR	389	0xe0008300 0x8>; /* config space access registers */
23dd1cbf KP	390	compatible = "fsl,mpc8349-pci";
	391	device_type = "pci";
	392	};
0585a155 AV	393
	394	pci1: pcie@e0009000 {
	395	#address-cells = <3>;
	396	#size-cells = <2>;
	397	#interrupt-cells = <1>;
	398	device_type = "pci";
	399	compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
	400	reg = <0xe0009000 0x00001000>;
	401	ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
	402	0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
	403	bus-range = <0 255>;
	404	interrupt-map-mask = <0xf800 0 0 7>;
	405	interrupt-map = <0 0 0 1 &ipic 1 8
	406	0 0 0 2 &ipic 1 8
	407	0 0 0 3 &ipic 1 8
	408	0 0 0 4 &ipic 1 8>;
	409	clock-frequency = <0>;
	410
	411	pcie@0 {
	412	#address-cells = <3>;
	413	#size-cells = <2>;
	414	device_type = "pci";
	415	reg = <0 0 0 0 0>;
	416	ranges = <0x02000000 0 0xa8000000
	417	0x02000000 0 0xa8000000
	418	0 0x10000000
	419	0x01000000 0 0x00000000
	420	0x01000000 0 0x00000000
	421	0 0x00800000>;
	422	};
	423	};
	424
	425	pci2: pcie@e000a000 {
	426	#address-cells = <3>;
	427	#size-cells = <2>;
	428	#interrupt-cells = <1>;
	429	device_type = "pci";
	430	compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
	431	reg = <0xe000a000 0x00001000>;
	432	ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
	433	0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
	434	bus-range = <0 255>;
	435	interrupt-map-mask = <0xf800 0 0 7>;
	436	interrupt-map = <0 0 0 1 &ipic 2 8
	437	0 0 0 2 &ipic 2 8
	438	0 0 0 3 &ipic 2 8
	439	0 0 0 4 &ipic 2 8>;
	440	clock-frequency = <0>;
	441
	442	pcie@0 {
	443	#address-cells = <3>;
	444	#size-cells = <2>;
	445	device_type = "pci";
	446	reg = <0 0 0 0 0>;
	447	ranges = <0x02000000 0 0xc8000000
	448	0x02000000 0 0xc8000000
	449	0 0x10000000
	450	0x01000000 0 0x00000000
	451	0x01000000 0 0x00000000
	452	0 0x00800000>;
	453	};
	454	};
23dd1cbf	455	};