[deliverable/linux.git] / arch / powerpc / boot / dts / mpc8379_mds.dts

/*
 * MPC8379E MDS Device Tree Source
 *
 * Copyright 2007 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/dts-v1/;

/ {
	model = "fsl,mpc8379emds";
	compatible = "fsl,mpc8379emds","fsl,mpc837xmds";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8379@0 {
			device_type = "cpu";
			reg = <0x0>;
			d-cache-line-size = <32>;
			i-cache-line-size = <32>;
			d-cache-size = <32768>;
			i-cache-size = <32768>;
			timebase-frequency = <0>;
			bus-frequency = <0>;
			clock-frequency = <0>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x20000000>;	// 512MB at 0
	};

	localbus@e0005000 {
		#address-cells = <2>;
		#size-cells = <1>;
		compatible = "fsl,mpc8379-elbc", "fsl,elbc", "simple-bus";
		reg = <0xe0005000 0x1000>;
		interrupts = <77 0x8>;
		interrupt-parent = <&ipic>;

		// booting from NOR flash
		ranges = <0 0x0 0xfe000000 0x02000000
		          1 0x0 0xf8000000 0x00008000
		          3 0x0 0xe0600000 0x00008000>;

		flash@0,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "cfi-flash";
			reg = <0 0x0 0x2000000>;
			bank-width = <2>;
			device-width = <1>;

			u-boot@0 {
				reg = <0x0 0x100000>;
				read-only;
			};

			fs@100000 {
				reg = <0x100000 0x800000>;
			};

			kernel@1d00000 {
				reg = <0x1d00000 0x200000>;
			};

			dtb@1f00000 {
				reg = <0x1f00000 0x100000>;
			};
		};

		bcsr@1,0 {
			reg = <1 0x0 0x8000>;
			compatible = "fsl,mpc837xmds-bcsr";
		};

		nand@3,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8379-fcm-nand",
			             "fsl,elbc-fcm-nand";
			reg = <3 0x0 0x8000>;

			u-boot@0 {
				reg = <0x0 0x100000>;
				read-only;
			};

			kernel@100000 {
				reg = <0x100000 0x300000>;
			};

			fs@400000 {
				reg = <0x400000 0x1c00000>;
			};
		};
	};

	soc@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		compatible = "simple-bus";
		ranges = <0x0 0xe0000000 0x00100000>;
		reg = <0xe0000000 0x00000200>;
		bus-frequency = <0>;

		wdt@200 {
			compatible = "mpc83xx_wdt";
			reg = <0x200 0x100>;
		};

		sleep-nexus {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "simple-bus";
			sleep = <&pmc 0x0c000000>;
			ranges;

			i2c@3000 {
				#address-cells = <1>;
				#size-cells = <0>;
				cell-index = <0>;
				compatible = "fsl-i2c";
				reg = <0x3000 0x100>;
				interrupts = <14 0x8>;
				interrupt-parent = <&ipic>;
				dfsrr;

				rtc@68 {
					compatible = "dallas,ds1374";
					reg = <0x68>;
					interrupts = <19 0x8>;
					interrupt-parent = <&ipic>;
				};
			};

			sdhci@2e000 {
				compatible = "fsl,mpc8379-esdhc", "fsl,esdhc";
				reg = <0x2e000 0x1000>;
				interrupts = <42 0x8>;
				interrupt-parent = <&ipic>;
				sdhci,wp-inverted;
				/* Filled in by U-Boot */
				clock-frequency = <0>;
			};
		};

		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <15 0x8>;
			interrupt-parent = <&ipic>;
			dfsrr;
		};

		spi@7000 {
			cell-index = <0>;
			compatible = "fsl,spi";
			reg = <0x7000 0x1000>;
			interrupts = <16 0x8>;
			interrupt-parent = <&ipic>;
			mode = "cpu";
		};

		dma@82a8 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8379-dma", "fsl,elo-dma";
			reg = <0x82a8 4>;
			ranges = <0 0x8100 0x1a8>;
			interrupt-parent = <&ipic>;
			interrupts = <71 8>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
				reg = <0 0x80>;
				cell-index = <0>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
			dma-channel@80 {
				compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
			dma-channel@100 {
				compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
			dma-channel@180 {
				compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
				reg = <0x180 0x28>;
				cell-index = <3>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
		};

		usb@23000 {
			compatible = "fsl-usb2-dr";
			reg = <0x23000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupt-parent = <&ipic>;
			interrupts = <38 0x8>;
			dr_mode = "host";
			phy_type = "ulpi";
			sleep = <&pmc 0x00c00000>;
		};

		enet0: ethernet@24000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <0>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x24000 0x1000>;
			ranges = <0x0 0x24000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <32 0x8 33 0x8 34 0x8>;
			phy-connection-type = "mii";
			interrupt-parent = <&ipic>;
			tbi-handle = <&tbi0>;
			phy-handle = <&phy2>;
			sleep = <&pmc 0xc0000000>;
			fsl,magic-packet;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-mdio";
				reg = <0x520 0x20>;

				phy2: ethernet-phy@2 {
					interrupt-parent = <&ipic>;
					interrupts = <17 0x8>;
					reg = <0x2>;
				};

				phy3: ethernet-phy@3 {
					interrupt-parent = <&ipic>;
					interrupts = <18 0x8>;
					reg = <0x3>;
				};

				tbi0: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		enet1: ethernet@25000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <1>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x25000 0x1000>;
			ranges = <0x0 0x25000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <35 0x8 36 0x8 37 0x8>;
			phy-connection-type = "mii";
			interrupt-parent = <&ipic>;
			tbi-handle = <&tbi1>;
			phy-handle = <&phy3>;
			sleep = <&pmc 0x30000000>;
			fsl,magic-packet;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-tbi";
				reg = <0x520 0x20>;

				tbi1: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "fsl,ns16550", "ns16550";
			reg = <0x4500 0x100>;
			clock-frequency = <0>;
			interrupts = <9 0x8>;
			interrupt-parent = <&ipic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "fsl,ns16550", "ns16550";
			reg = <0x4600 0x100>;
			clock-frequency = <0>;
			interrupts = <10 0x8>;
			interrupt-parent = <&ipic>;
		};

		crypto@30000 {
			compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
				     "fsl,sec2.1", "fsl,sec2.0";
			reg = <0x30000 0x10000>;
			interrupts = <11 0x8>;
			interrupt-parent = <&ipic>;
			fsl,num-channels = <4>;
			fsl,channel-fifo-len = <24>;
			fsl,exec-units-mask = <0x9fe>;
			fsl,descriptor-types-mask = <0x3ab0ebf>;
			sleep = <&pmc 0x03000000>;
		};

		sata@18000 {
			compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
			reg = <0x18000 0x1000>;
			interrupts = <44 0x8>;
			interrupt-parent = <&ipic>;
			sleep = <&pmc 0x000000c0>;
		};

		sata@19000 {
			compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
			reg = <0x19000 0x1000>;
			interrupts = <45 0x8>;
			interrupt-parent = <&ipic>;
			sleep = <&pmc 0x00000030>;
		};

		sata@1a000 {
			compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
			reg = <0x1a000 0x1000>;
			interrupts = <46 0x8>;
			interrupt-parent = <&ipic>;
			sleep = <&pmc 0x0000000c>;
		};

		sata@1b000 {
			compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
			reg = <0x1b000 0x1000>;
			interrupts = <47 0x8>;
			interrupt-parent = <&ipic>;
			sleep = <&pmc 0x00000003>;
		};

		/* IPIC
		 * interrupts cell = <intr #, sense>
		 * sense values match linux IORESOURCE_IRQ_* defines:
		 * sense == 8: Level, low assertion
		 * sense == 2: Edge, high-to-low change
		 */
		ipic: pic@700 {
			compatible = "fsl,ipic";
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x700 0x100>;
		};

		pmc: power@b00 {
			compatible = "fsl,mpc8379-pmc", "fsl,mpc8349-pmc";
			reg = <0xb00 0x100 0xa00 0x100>;
			interrupts = <80 0x8>;
			interrupt-parent = <&ipic>;
		};
	};

	pci0: pci@e0008500 {
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <

				/* IDSEL 0x11 */
				 0x8800 0x0 0x0 0x1 &ipic 20 0x8
				 0x8800 0x0 0x0 0x2 &ipic 21 0x8
				 0x8800 0x0 0x0 0x3 &ipic 22 0x8
				 0x8800 0x0 0x0 0x4 &ipic 23 0x8

				/* IDSEL 0x12 */
				 0x9000 0x0 0x0 0x1 &ipic 22 0x8
				 0x9000 0x0 0x0 0x2 &ipic 23 0x8
				 0x9000 0x0 0x0 0x3 &ipic 20 0x8
				 0x9000 0x0 0x0 0x4 &ipic 21 0x8

				/* IDSEL 0x13 */
				 0x9800 0x0 0x0 0x1 &ipic 23 0x8
				 0x9800 0x0 0x0 0x2 &ipic 20 0x8
				 0x9800 0x0 0x0 0x3 &ipic 21 0x8
				 0x9800 0x0 0x0 0x4 &ipic 22 0x8

				/* IDSEL 0x15 */
				 0xa800 0x0 0x0 0x1 &ipic 20 0x8
				 0xa800 0x0 0x0 0x2 &ipic 21 0x8
				 0xa800 0x0 0x0 0x3 &ipic 22 0x8
				 0xa800 0x0 0x0 0x4 &ipic 23 0x8

				/* IDSEL 0x16 */
				 0xb000 0x0 0x0 0x1 &ipic 23 0x8
				 0xb000 0x0 0x0 0x2 &ipic 20 0x8
				 0xb000 0x0 0x0 0x3 &ipic 21 0x8
				 0xb000 0x0 0x0 0x4 &ipic 22 0x8

				/* IDSEL 0x17 */
				 0xb800 0x0 0x0 0x1 &ipic 22 0x8
				 0xb800 0x0 0x0 0x2 &ipic 23 0x8
				 0xb800 0x0 0x0 0x3 &ipic 20 0x8
				 0xb800 0x0 0x0 0x4 &ipic 21 0x8

				/* IDSEL 0x18 */
				 0xc000 0x0 0x0 0x1 &ipic 21 0x8
				 0xc000 0x0 0x0 0x2 &ipic 22 0x8
				 0xc000 0x0 0x0 0x3 &ipic 23 0x8
				 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
		interrupt-parent = <&ipic>;
		interrupts = <66 0x8>;
		bus-range = <0x0 0x0>;
		ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
		          0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
		          0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
		sleep = <&pmc 0x00010000>;
		clock-frequency = <0>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0008500 0x100		/* internal registers */
		       0xe0008300 0x8>;		/* config space access registers */
		compatible = "fsl,mpc8349-pci";
		device_type = "pci";
	};
};
Commit	Line	Data
5761bc5d LY	1	/*
	2	* MPC8379E MDS Device Tree Source
	3	*
	4	* Copyright 2007 Freescale Semiconductor Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*/
	11
	12	/dts-v1/;
	13
	14	/ {
	15	model = "fsl,mpc8379emds";
	16	compatible = "fsl,mpc8379emds","fsl,mpc837xmds";
	17	#address-cells = <1>;
	18	#size-cells = <1>;
	19
	20	aliases {
	21	ethernet0 = &enet0;
	22	ethernet1 = &enet1;
	23	serial0 = &serial0;
	24	serial1 = &serial1;
	25	pci0 = &pci0;
	26	};
	27
	28	cpus {
	29	#address-cells = <1>;
	30	#size-cells = <0>;
	31
	32	PowerPC,8379@0 {
	33	device_type = "cpu";
cda13dd1 PG	34	reg = <0x0>;
	35	d-cache-line-size = <32>;
	36	i-cache-line-size = <32>;
	37	d-cache-size = <32768>;
	38	i-cache-size = <32768>;
5761bc5d LY	39	timebase-frequency = <0>;
	40	bus-frequency = <0>;
	41	clock-frequency = <0>;
	42	};
	43	};
	44
	45	memory {
	46	device_type = "memory";
	47	reg = <0x00000000 0x20000000>; // 512MB at 0
	48	};
	49
d7f46190 LY	50	localbus@e0005000 {
	51	#address-cells = <2>;
	52	#size-cells = <1>;
	53	compatible = "fsl,mpc8379-elbc", "fsl,elbc", "simple-bus";
	54	reg = <0xe0005000 0x1000>;
	55	interrupts = <77 0x8>;
	56	interrupt-parent = <&ipic>;
	57
	58	// booting from NOR flash
	59	ranges = <0 0x0 0xfe000000 0x02000000
	60	1 0x0 0xf8000000 0x00008000
	61	3 0x0 0xe0600000 0x00008000>;
	62
	63	flash@0,0 {
	64	#address-cells = <1>;
	65	#size-cells = <1>;
	66	compatible = "cfi-flash";
	67	reg = <0 0x0 0x2000000>;
	68	bank-width = <2>;
	69	device-width = <1>;
	70
	71	u-boot@0 {
	72	reg = <0x0 0x100000>;
	73	read-only;
	74	};
	75
	76	fs@100000 {
	77	reg = <0x100000 0x800000>;
	78	};
	79
	80	kernel@1d00000 {
	81	reg = <0x1d00000 0x200000>;
	82	};
	83
	84	dtb@1f00000 {
	85	reg = <0x1f00000 0x100000>;
	86	};
	87	};
	88
	89	bcsr@1,0 {
	90	reg = <1 0x0 0x8000>;
	91	compatible = "fsl,mpc837xmds-bcsr";
	92	};
	93
	94	nand@3,0 {
	95	#address-cells = <1>;
	96	#size-cells = <1>;
	97	compatible = "fsl,mpc8379-fcm-nand",
	98	"fsl,elbc-fcm-nand";
	99	reg = <3 0x0 0x8000>;
	100
	101	u-boot@0 {
	102	reg = <0x0 0x100000>;
	103	read-only;
	104	};
	105
	106	kernel@100000 {
	107	reg = <0x100000 0x300000>;
	108	};
	109
	110	fs@400000 {
	111	reg = <0x400000 0x1c00000>;
	112	};
	113	};
114	};
115
5761bc5d LY	116	soc@e0000000 {
	117	#address-cells = <1>;
	118	#size-cells = <1>;
	119	device_type = "soc";
cf0d19fb	120	compatible = "simple-bus";
5761bc5d LY	121	ranges = <0x0 0xe0000000 0x00100000>;
	122	reg = <0xe0000000 0x00000200>;
	123	bus-frequency = <0>;
	124
	125	wdt@200 {
	126	compatible = "mpc83xx_wdt";
	127	reg = <0x200 0x100>;
	128	};
	129
125a00d7	130	sleep-nexus {
5761bc5d	131	#address-cells = <1>;
125a00d7 AV	132	#size-cells = <1>;
	133	compatible = "simple-bus";
	134	sleep = <&pmc 0x0c000000>;
	135	ranges;
8b77aeb4	136
125a00d7 AV	137	i2c@3000 {
	138	#address-cells = <1>;
	139	#size-cells = <0>;
	140	cell-index = <0>;
	141	compatible = "fsl-i2c";
	142	reg = <0x3000 0x100>;
	143	interrupts = <14 0x8>;
8b77aeb4	144	interrupt-parent = <&ipic>;
125a00d7 AV	145	dfsrr;
	146
	147	rtc@68 {
	148	compatible = "dallas,ds1374";
	149	reg = <0x68>;
	150	interrupts = <19 0x8>;
	151	interrupt-parent = <&ipic>;
	152	};
	153	};
	154
	155	sdhci@2e000 {
1a2eceaa	156	compatible = "fsl,mpc8379-esdhc", "fsl,esdhc";
125a00d7 AV	157	reg = <0x2e000 0x1000>;
	158	interrupts = <42 0x8>;
	159	interrupt-parent = <&ipic>;
50dfe70f	160	sdhci,wp-inverted;
125a00d7 AV	161	/* Filled in by U-Boot */
125a00d7 AV	162	clock-frequency = <0>;
8b77aeb4	163	};
5761bc5d LY	164	};
	165
	166	i2c@3100 {
	167	#address-cells = <1>;
	168	#size-cells = <0>;
	169	cell-index = <1>;
	170	compatible = "fsl-i2c";
	171	reg = <0x3100 0x100>;
cda13dd1 PG	172	interrupts = <15 0x8>;
cda13dd1 PG	173	interrupt-parent = <&ipic>;
5761bc5d LY	174	dfsrr;
	175	};
	176
	177	spi@7000 {
f3a2b29d AV	178	cell-index = <0>;
f3a2b29d AV	179	compatible = "fsl,spi";
5761bc5d	180	reg = <0x7000 0x1000>;
cda13dd1 PG	181	interrupts = <16 0x8>;
cda13dd1 PG	182	interrupt-parent = <&ipic>;
5761bc5d LY	183	mode = "cpu";
	184	};
	185
dee80553 KG	186	dma@82a8 {
	187	#address-cells = <1>;
	188	#size-cells = <1>;
	189	compatible = "fsl,mpc8379-dma", "fsl,elo-dma";
	190	reg = <0x82a8 4>;
	191	ranges = <0 0x8100 0x1a8>;
	192	interrupt-parent = <&ipic>;
	193	interrupts = <71 8>;
	194	cell-index = <0>;
	195	dma-channel@0 {
	196	compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
	197	reg = <0 0x80>;
aeb42762	198	cell-index = <0>;
dee80553 KG	199	interrupt-parent = <&ipic>;
	200	interrupts = <71 8>;
	201	};
	202	dma-channel@80 {
	203	compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
	204	reg = <0x80 0x80>;
aeb42762	205	cell-index = <1>;
dee80553 KG	206	interrupt-parent = <&ipic>;
	207	interrupts = <71 8>;
	208	};
	209	dma-channel@100 {
	210	compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
	211	reg = <0x100 0x80>;
aeb42762	212	cell-index = <2>;
dee80553 KG	213	interrupt-parent = <&ipic>;
	214	interrupts = <71 8>;
	215	};
	216	dma-channel@180 {
	217	compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
	218	reg = <0x180 0x28>;
aeb42762	219	cell-index = <3>;
dee80553 KG	220	interrupt-parent = <&ipic>;
	221	interrupts = <71 8>;
	222	};
	223	};
	224
5761bc5d LY	225	usb@23000 {
	226	compatible = "fsl-usb2-dr";
	227	reg = <0x23000 0x1000>;
	228	#address-cells = <1>;
	229	#size-cells = <0>;
cda13dd1 PG	230	interrupt-parent = <&ipic>;
cda13dd1 PG	231	interrupts = <38 0x8>;
28b95885 LY	232	dr_mode = "host";
28b95885 LY	233	phy_type = "ulpi";
125a00d7	234	sleep = <&pmc 0x00c00000>;
5761bc5d LY	235	};
5761bc5d LY	236
5761bc5d	237	enet0: ethernet@24000 {
70b3adbb AV	238	#address-cells = <1>;
70b3adbb AV	239	#size-cells = <1>;
5761bc5d LY	240	cell-index = <0>;
	241	device_type = "network";
	242	model = "eTSEC";
	243	compatible = "gianfar";
	244	reg = <0x24000 0x1000>;
70b3adbb	245	ranges = <0x0 0x24000 0x1000>;
5761bc5d	246	local-mac-address = [ 00 00 00 00 00 00 ];
cda13dd1	247	interrupts = <32 0x8 33 0x8 34 0x8>;
5761bc5d	248	phy-connection-type = "mii";
cda13dd1	249	interrupt-parent = <&ipic>;
b31a1d8b	250	tbi-handle = <&tbi0>;
cda13dd1	251	phy-handle = <&phy2>;
125a00d7 AV	252	sleep = <&pmc 0xc0000000>;
125a00d7 AV	253	fsl,magic-packet;
70b3adbb AV	254
	255	mdio@520 {
	256	#address-cells = <1>;
	257	#size-cells = <0>;
	258	compatible = "fsl,gianfar-mdio";
	259	reg = <0x520 0x20>;
	260
	261	phy2: ethernet-phy@2 {
	262	interrupt-parent = <&ipic>;
	263	interrupts = <17 0x8>;
	264	reg = <0x2>;
70b3adbb AV	265	};
	266
	267	phy3: ethernet-phy@3 {
	268	interrupt-parent = <&ipic>;
	269	interrupts = <18 0x8>;
	270	reg = <0x3>;
70b3adbb AV	271	};
	272
	273	tbi0: tbi-phy@11 {
	274	reg = <0x11>;
	275	device_type = "tbi-phy";
	276	};
	277	};
5761bc5d LY	278	};
	279
	280	enet1: ethernet@25000 {
70b3adbb AV	281	#address-cells = <1>;
70b3adbb AV	282	#size-cells = <1>;
5761bc5d LY	283	cell-index = <1>;
	284	device_type = "network";
	285	model = "eTSEC";
	286	compatible = "gianfar";
	287	reg = <0x25000 0x1000>;
70b3adbb	288	ranges = <0x0 0x25000 0x1000>;
5761bc5d	289	local-mac-address = [ 00 00 00 00 00 00 ];
cda13dd1	290	interrupts = <35 0x8 36 0x8 37 0x8>;
5761bc5d	291	phy-connection-type = "mii";
cda13dd1	292	interrupt-parent = <&ipic>;
b31a1d8b	293	tbi-handle = <&tbi1>;
cda13dd1	294	phy-handle = <&phy3>;
125a00d7 AV	295	sleep = <&pmc 0x30000000>;
125a00d7 AV	296	fsl,magic-packet;
70b3adbb AV	297
	298	mdio@520 {
	299	#address-cells = <1>;
	300	#size-cells = <0>;
	301	compatible = "fsl,gianfar-tbi";
	302	reg = <0x520 0x20>;
	303
	304	tbi1: tbi-phy@11 {
	305	reg = <0x11>;
	306	device_type = "tbi-phy";
	307	};
	308	};
5761bc5d LY	309	};
	310
	311	serial0: serial@4500 {
	312	cell-index = <0>;
	313	device_type = "serial";
f706bed1	314	compatible = "fsl,ns16550", "ns16550";
5761bc5d LY	315	reg = <0x4500 0x100>;
5761bc5d LY	316	clock-frequency = <0>;
cda13dd1 PG	317	interrupts = <9 0x8>;
cda13dd1 PG	318	interrupt-parent = <&ipic>;
5761bc5d LY	319	};
	320
	321	serial1: serial@4600 {
	322	cell-index = <1>;
	323	device_type = "serial";
f706bed1	324	compatible = "fsl,ns16550", "ns16550";
5761bc5d LY	325	reg = <0x4600 0x100>;
5761bc5d LY	326	clock-frequency = <0>;
cda13dd1 PG	327	interrupts = <10 0x8>;
cda13dd1 PG	328	interrupt-parent = <&ipic>;
5761bc5d LY	329	};
	330
	331	crypto@30000 {
3fd44736 KP	332	compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
3fd44736 KP	333	"fsl,sec2.1", "fsl,sec2.0";
5761bc5d	334	reg = <0x30000 0x10000>;
cda13dd1 PG	335	interrupts = <11 0x8>;
cda13dd1 PG	336	interrupt-parent = <&ipic>;
3fd44736 KP	337	fsl,num-channels = <4>;
	338	fsl,channel-fifo-len = <24>;
	339	fsl,exec-units-mask = <0x9fe>;
	340	fsl,descriptor-types-mask = <0x3ab0ebf>;
125a00d7	341	sleep = <&pmc 0x03000000>;
5761bc5d LY	342	};
	343
	344	sata@18000 {
96ce1b6d	345	compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
5761bc5d	346	reg = <0x18000 0x1000>;
cda13dd1 PG	347	interrupts = <44 0x8>;
cda13dd1 PG	348	interrupt-parent = <&ipic>;
125a00d7	349	sleep = <&pmc 0x000000c0>;
5761bc5d LY	350	};
	351
	352	sata@19000 {
96ce1b6d	353	compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
5761bc5d	354	reg = <0x19000 0x1000>;
cda13dd1 PG	355	interrupts = <45 0x8>;
cda13dd1 PG	356	interrupt-parent = <&ipic>;
125a00d7	357	sleep = <&pmc 0x00000030>;
5761bc5d LY	358	};
	359
	360	sata@1a000 {
96ce1b6d	361	compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
5761bc5d	362	reg = <0x1a000 0x1000>;
cda13dd1 PG	363	interrupts = <46 0x8>;
cda13dd1 PG	364	interrupt-parent = <&ipic>;
125a00d7	365	sleep = <&pmc 0x0000000c>;
5761bc5d LY	366	};
	367
	368	sata@1b000 {
96ce1b6d	369	compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
5761bc5d	370	reg = <0x1b000 0x1000>;
cda13dd1 PG	371	interrupts = <47 0x8>;
cda13dd1 PG	372	interrupt-parent = <&ipic>;
125a00d7	373	sleep = <&pmc 0x00000003>;
5761bc5d LY	374	};
	375
	376	/* IPIC
	377	* interrupts cell = <intr #, sense>
	378	* sense values match linux IORESOURCE_IRQ_* defines:
	379	* sense == 8: Level, low assertion
	380	* sense == 2: Edge, high-to-low change
	381	*/
	382	ipic: pic@700 {
	383	compatible = "fsl,ipic";
	384	interrupt-controller;
	385	#address-cells = <0>;
	386	#interrupt-cells = <2>;
	387	reg = <0x700 0x100>;
	388	};
125a00d7 AV	389
	390	pmc: power@b00 {
	391	compatible = "fsl,mpc8379-pmc", "fsl,mpc8349-pmc";
	392	reg = <0xb00 0x100 0xa00 0x100>;
	393	interrupts = <80 0x8>;
	394	interrupt-parent = <&ipic>;
	395	};
5761bc5d LY	396	};
	397
	398	pci0: pci@e0008500 {
5761bc5d LY	399	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
	400	interrupt-map = <
	401
	402	/* IDSEL 0x11 */
cda13dd1 PG	403	0x8800 0x0 0x0 0x1 &ipic 20 0x8
	404	0x8800 0x0 0x0 0x2 &ipic 21 0x8
	405	0x8800 0x0 0x0 0x3 &ipic 22 0x8
	406	0x8800 0x0 0x0 0x4 &ipic 23 0x8
5761bc5d LY	407
5761bc5d LY	408	/* IDSEL 0x12 */
cda13dd1 PG	409	0x9000 0x0 0x0 0x1 &ipic 22 0x8
	410	0x9000 0x0 0x0 0x2 &ipic 23 0x8
	411	0x9000 0x0 0x0 0x3 &ipic 20 0x8
	412	0x9000 0x0 0x0 0x4 &ipic 21 0x8
5761bc5d LY	413
5761bc5d LY	414	/* IDSEL 0x13 */
cda13dd1 PG	415	0x9800 0x0 0x0 0x1 &ipic 23 0x8
	416	0x9800 0x0 0x0 0x2 &ipic 20 0x8
	417	0x9800 0x0 0x0 0x3 &ipic 21 0x8
	418	0x9800 0x0 0x0 0x4 &ipic 22 0x8
5761bc5d LY	419
5761bc5d LY	420	/* IDSEL 0x15 */
cda13dd1 PG	421	0xa800 0x0 0x0 0x1 &ipic 20 0x8
	422	0xa800 0x0 0x0 0x2 &ipic 21 0x8
	423	0xa800 0x0 0x0 0x3 &ipic 22 0x8
	424	0xa800 0x0 0x0 0x4 &ipic 23 0x8
5761bc5d LY	425
5761bc5d LY	426	/* IDSEL 0x16 */
cda13dd1 PG	427	0xb000 0x0 0x0 0x1 &ipic 23 0x8
	428	0xb000 0x0 0x0 0x2 &ipic 20 0x8
	429	0xb000 0x0 0x0 0x3 &ipic 21 0x8
	430	0xb000 0x0 0x0 0x4 &ipic 22 0x8
5761bc5d LY	431
5761bc5d LY	432	/* IDSEL 0x17 */
cda13dd1 PG	433	0xb800 0x0 0x0 0x1 &ipic 22 0x8
	434	0xb800 0x0 0x0 0x2 &ipic 23 0x8
	435	0xb800 0x0 0x0 0x3 &ipic 20 0x8
	436	0xb800 0x0 0x0 0x4 &ipic 21 0x8
5761bc5d LY	437
5761bc5d LY	438	/* IDSEL 0x18 */
cda13dd1 PG	439	0xc000 0x0 0x0 0x1 &ipic 21 0x8
	440	0xc000 0x0 0x0 0x2 &ipic 22 0x8
	441	0xc000 0x0 0x0 0x3 &ipic 23 0x8
	442	0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
	443	interrupt-parent = <&ipic>;
	444	interrupts = <66 0x8>;
	445	bus-range = <0x0 0x0>;
5761bc5d LY	446	ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
	447	0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
	448	0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
125a00d7	449	sleep = <&pmc 0x00010000>;
5761bc5d LY	450	clock-frequency = <0>;
	451	#interrupt-cells = <1>;
	452	#size-cells = <2>;
	453	#address-cells = <3>;
5b70a097 JR	454	reg = <0xe0008500 0x100 /* internal registers */
5b70a097 JR	455	0xe0008300 0x8>; /* config space access registers */
5761bc5d LY	456	compatible = "fsl,mpc8349-pci";
	457	device_type = "pci";
	458	};
	459	};