[deliverable/linux.git] / arch / powerpc / boot / dts / mpc8379_mds.dts

/*
 * MPC8379E MDS Device Tree Source
 *
 * Copyright 2007 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/dts-v1/;

/ {
	model = "fsl,mpc8379emds";
	compatible = "fsl,mpc8379emds","fsl,mpc837xmds";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8379@0 {
			device_type = "cpu";
			reg = <0x0>;
			d-cache-line-size = <32>;
			i-cache-line-size = <32>;
			d-cache-size = <32768>;
			i-cache-size = <32768>;
			timebase-frequency = <0>;
			bus-frequency = <0>;
			clock-frequency = <0>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x20000000>;	// 512MB at 0
	};

	localbus@e0005000 {
		#address-cells = <2>;
		#size-cells = <1>;
		compatible = "fsl,mpc8379-elbc", "fsl,elbc", "simple-bus";
		reg = <0xe0005000 0x1000>;
		interrupts = <77 0x8>;
		interrupt-parent = <&ipic>;

		// booting from NOR flash
		ranges = <0 0x0 0xfe000000 0x02000000
		          1 0x0 0xf8000000 0x00008000
		          3 0x0 0xe0600000 0x00008000>;

		flash@0,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "cfi-flash";
			reg = <0 0x0 0x2000000>;
			bank-width = <2>;
			device-width = <1>;

			u-boot@0 {
				reg = <0x0 0x100000>;
				read-only;
			};

			fs@100000 {
				reg = <0x100000 0x800000>;
			};

			kernel@1d00000 {
				reg = <0x1d00000 0x200000>;
			};

			dtb@1f00000 {
				reg = <0x1f00000 0x100000>;
			};
		};

		bcsr@1,0 {
			reg = <1 0x0 0x8000>;
			compatible = "fsl,mpc837xmds-bcsr";
		};

		nand@3,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8379-fcm-nand",
			             "fsl,elbc-fcm-nand";
			reg = <3 0x0 0x8000>;

			u-boot@0 {
				reg = <0x0 0x100000>;
				read-only;
			};

			kernel@100000 {
				reg = <0x100000 0x300000>;
			};

			fs@400000 {
				reg = <0x400000 0x1c00000>;
			};
		};
	};

	soc@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		compatible = "simple-bus";
		ranges = <0x0 0xe0000000 0x00100000>;
		reg = <0xe0000000 0x00000200>;
		bus-frequency = <0>;

		wdt@200 {
			compatible = "mpc83xx_wdt";
			reg = <0x200 0x100>;
		};

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <14 0x8>;
			interrupt-parent = <&ipic>;
			dfsrr;
		};

		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <15 0x8>;
			interrupt-parent = <&ipic>;
			dfsrr;
		};

		spi@7000 {
			cell-index = <0>;
			compatible = "fsl,spi";
			reg = <0x7000 0x1000>;
			interrupts = <16 0x8>;
			interrupt-parent = <&ipic>;
			mode = "cpu";
		};

		dma@82a8 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8379-dma", "fsl,elo-dma";
			reg = <0x82a8 4>;
			ranges = <0 0x8100 0x1a8>;
			interrupt-parent = <&ipic>;
			interrupts = <71 8>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
				reg = <0 0x80>;
				cell-index = <0>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
			dma-channel@80 {
				compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
			dma-channel@100 {
				compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
			dma-channel@180 {
				compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
				reg = <0x180 0x28>;
				cell-index = <3>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
		};

		usb@23000 {
			compatible = "fsl-usb2-dr";
			reg = <0x23000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupt-parent = <&ipic>;
			interrupts = <38 0x8>;
			dr_mode = "host";
			phy_type = "ulpi";
		};

		mdio@24520 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,gianfar-mdio";
			reg = <0x24520 0x20>;
			phy2: ethernet-phy@2 {
				interrupt-parent = <&ipic>;
				interrupts = <17 0x8>;
				reg = <0x2>;
				device_type = "ethernet-phy";
			};
			phy3: ethernet-phy@3 {
				interrupt-parent = <&ipic>;
				interrupts = <18 0x8>;
				reg = <0x3>;
				device_type = "ethernet-phy";
			};
		};

		enet0: ethernet@24000 {
			cell-index = <0>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x24000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <32 0x8 33 0x8 34 0x8>;
			phy-connection-type = "mii";
			interrupt-parent = <&ipic>;
			phy-handle = <&phy2>;
		};

		enet1: ethernet@25000 {
			cell-index = <1>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x25000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <35 0x8 36 0x8 37 0x8>;
			phy-connection-type = "mii";
			interrupt-parent = <&ipic>;
			phy-handle = <&phy3>;
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4500 0x100>;
			clock-frequency = <0>;
			interrupts = <9 0x8>;
			interrupt-parent = <&ipic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4600 0x100>;
			clock-frequency = <0>;
			interrupts = <10 0x8>;
			interrupt-parent = <&ipic>;
		};

		crypto@30000 {
			compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
				     "fsl,sec2.1", "fsl,sec2.0";
			reg = <0x30000 0x10000>;
			interrupts = <11 0x8>;
			interrupt-parent = <&ipic>;
			fsl,num-channels = <4>;
			fsl,channel-fifo-len = <24>;
			fsl,exec-units-mask = <0x9fe>;
			fsl,descriptor-types-mask = <0x3ab0ebf>;
		};

		sdhc@2e000 {
			model = "eSDHC";
			compatible = "fsl,esdhc";
			reg = <0x2e000 0x1000>;
			interrupts = <42 0x8>;
			interrupt-parent = <&ipic>;
		};

		sata@18000 {
			compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
			reg = <0x18000 0x1000>;
			interrupts = <44 0x8>;
			interrupt-parent = <&ipic>;
		};

		sata@19000 {
			compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
			reg = <0x19000 0x1000>;
			interrupts = <45 0x8>;
			interrupt-parent = <&ipic>;
		};

		sata@1a000 {
			compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
			reg = <0x1a000 0x1000>;
			interrupts = <46 0x8>;
			interrupt-parent = <&ipic>;
		};

		sata@1b000 {
			compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
			reg = <0x1b000 0x1000>;
			interrupts = <47 0x8>;
			interrupt-parent = <&ipic>;
		};

		/* IPIC
		 * interrupts cell = <intr #, sense>
		 * sense values match linux IORESOURCE_IRQ_* defines:
		 * sense == 8: Level, low assertion
		 * sense == 2: Edge, high-to-low change
		 */
		ipic: pic@700 {
			compatible = "fsl,ipic";
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x700 0x100>;
		};
	};

	pci0: pci@e0008500 {
		cell-index = <0>;
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <

				/* IDSEL 0x11 */
				 0x8800 0x0 0x0 0x1 &ipic 20 0x8
				 0x8800 0x0 0x0 0x2 &ipic 21 0x8
				 0x8800 0x0 0x0 0x3 &ipic 22 0x8
				 0x8800 0x0 0x0 0x4 &ipic 23 0x8

				/* IDSEL 0x12 */
				 0x9000 0x0 0x0 0x1 &ipic 22 0x8
				 0x9000 0x0 0x0 0x2 &ipic 23 0x8
				 0x9000 0x0 0x0 0x3 &ipic 20 0x8
				 0x9000 0x0 0x0 0x4 &ipic 21 0x8

				/* IDSEL 0x13 */
				 0x9800 0x0 0x0 0x1 &ipic 23 0x8
				 0x9800 0x0 0x0 0x2 &ipic 20 0x8
				 0x9800 0x0 0x0 0x3 &ipic 21 0x8
				 0x9800 0x0 0x0 0x4 &ipic 22 0x8

				/* IDSEL 0x15 */
				 0xa800 0x0 0x0 0x1 &ipic 20 0x8
				 0xa800 0x0 0x0 0x2 &ipic 21 0x8
				 0xa800 0x0 0x0 0x3 &ipic 22 0x8
				 0xa800 0x0 0x0 0x4 &ipic 23 0x8

				/* IDSEL 0x16 */
				 0xb000 0x0 0x0 0x1 &ipic 23 0x8
				 0xb000 0x0 0x0 0x2 &ipic 20 0x8
				 0xb000 0x0 0x0 0x3 &ipic 21 0x8
				 0xb000 0x0 0x0 0x4 &ipic 22 0x8

				/* IDSEL 0x17 */
				 0xb800 0x0 0x0 0x1 &ipic 22 0x8
				 0xb800 0x0 0x0 0x2 &ipic 23 0x8
				 0xb800 0x0 0x0 0x3 &ipic 20 0x8
				 0xb800 0x0 0x0 0x4 &ipic 21 0x8

				/* IDSEL 0x18 */
				 0xc000 0x0 0x0 0x1 &ipic 21 0x8
				 0xc000 0x0 0x0 0x2 &ipic 22 0x8
				 0xc000 0x0 0x0 0x3 &ipic 23 0x8
				 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
		interrupt-parent = <&ipic>;
		interrupts = <66 0x8>;
		bus-range = <0x0 0x0>;
		ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
		          0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
		          0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
		clock-frequency = <0>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0008500 0x100>;
		compatible = "fsl,mpc8349-pci";
		device_type = "pci";
	};
};
Commit	Line	Data
5761bc5d LY	1	/*
	2	* MPC8379E MDS Device Tree Source
	3	*
	4	* Copyright 2007 Freescale Semiconductor Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*/
	11
	12	/dts-v1/;
	13
	14	/ {
	15	model = "fsl,mpc8379emds";
	16	compatible = "fsl,mpc8379emds","fsl,mpc837xmds";
	17	#address-cells = <1>;
	18	#size-cells = <1>;
	19
	20	aliases {
	21	ethernet0 = &enet0;
	22	ethernet1 = &enet1;
	23	serial0 = &serial0;
	24	serial1 = &serial1;
	25	pci0 = &pci0;
	26	};
	27
	28	cpus {
	29	#address-cells = <1>;
	30	#size-cells = <0>;
	31
	32	PowerPC,8379@0 {
	33	device_type = "cpu";
cda13dd1 PG	34	reg = <0x0>;
	35	d-cache-line-size = <32>;
	36	i-cache-line-size = <32>;
	37	d-cache-size = <32768>;
	38	i-cache-size = <32768>;
5761bc5d LY	39	timebase-frequency = <0>;
	40	bus-frequency = <0>;
	41	clock-frequency = <0>;
	42	};
	43	};
	44
	45	memory {
	46	device_type = "memory";
	47	reg = <0x00000000 0x20000000>; // 512MB at 0
	48	};
	49
d7f46190 LY	50	localbus@e0005000 {
	51	#address-cells = <2>;
	52	#size-cells = <1>;
	53	compatible = "fsl,mpc8379-elbc", "fsl,elbc", "simple-bus";
	54	reg = <0xe0005000 0x1000>;
	55	interrupts = <77 0x8>;
	56	interrupt-parent = <&ipic>;
	57
	58	// booting from NOR flash
	59	ranges = <0 0x0 0xfe000000 0x02000000
	60	1 0x0 0xf8000000 0x00008000
	61	3 0x0 0xe0600000 0x00008000>;
	62
	63	flash@0,0 {
	64	#address-cells = <1>;
	65	#size-cells = <1>;
	66	compatible = "cfi-flash";
	67	reg = <0 0x0 0x2000000>;
	68	bank-width = <2>;
	69	device-width = <1>;
	70
	71	u-boot@0 {
	72	reg = <0x0 0x100000>;
	73	read-only;
	74	};
	75
	76	fs@100000 {
	77	reg = <0x100000 0x800000>;
	78	};
	79
	80	kernel@1d00000 {
	81	reg = <0x1d00000 0x200000>;
	82	};
	83
	84	dtb@1f00000 {
	85	reg = <0x1f00000 0x100000>;
	86	};
	87	};
	88
	89	bcsr@1,0 {
	90	reg = <1 0x0 0x8000>;
	91	compatible = "fsl,mpc837xmds-bcsr";
	92	};
	93
	94	nand@3,0 {
	95	#address-cells = <1>;
	96	#size-cells = <1>;
	97	compatible = "fsl,mpc8379-fcm-nand",
	98	"fsl,elbc-fcm-nand";
	99	reg = <3 0x0 0x8000>;
	100
	101	u-boot@0 {
	102	reg = <0x0 0x100000>;
	103	read-only;
	104	};
	105
	106	kernel@100000 {
	107	reg = <0x100000 0x300000>;
	108	};
	109
	110	fs@400000 {
	111	reg = <0x400000 0x1c00000>;
	112	};
	113	};
114	};
115
5761bc5d LY	116	soc@e0000000 {
	117	#address-cells = <1>;
	118	#size-cells = <1>;
	119	device_type = "soc";
cf0d19fb	120	compatible = "simple-bus";
5761bc5d LY	121	ranges = <0x0 0xe0000000 0x00100000>;
	122	reg = <0xe0000000 0x00000200>;
	123	bus-frequency = <0>;
	124
	125	wdt@200 {
	126	compatible = "mpc83xx_wdt";
	127	reg = <0x200 0x100>;
	128	};
	129
	130	i2c@3000 {
	131	#address-cells = <1>;
	132	#size-cells = <0>;
	133	cell-index = <0>;
	134	compatible = "fsl-i2c";
	135	reg = <0x3000 0x100>;
cda13dd1 PG	136	interrupts = <14 0x8>;
cda13dd1 PG	137	interrupt-parent = <&ipic>;
5761bc5d LY	138	dfsrr;
	139	};
	140
	141	i2c@3100 {
	142	#address-cells = <1>;
	143	#size-cells = <0>;
	144	cell-index = <1>;
	145	compatible = "fsl-i2c";
	146	reg = <0x3100 0x100>;
cda13dd1 PG	147	interrupts = <15 0x8>;
cda13dd1 PG	148	interrupt-parent = <&ipic>;
5761bc5d LY	149	dfsrr;
	150	};
	151
	152	spi@7000 {
f3a2b29d AV	153	cell-index = <0>;
f3a2b29d AV	154	compatible = "fsl,spi";
5761bc5d	155	reg = <0x7000 0x1000>;
cda13dd1 PG	156	interrupts = <16 0x8>;
cda13dd1 PG	157	interrupt-parent = <&ipic>;
5761bc5d LY	158	mode = "cpu";
	159	};
	160
dee80553 KG	161	dma@82a8 {
	162	#address-cells = <1>;
	163	#size-cells = <1>;
	164	compatible = "fsl,mpc8379-dma", "fsl,elo-dma";
	165	reg = <0x82a8 4>;
	166	ranges = <0 0x8100 0x1a8>;
	167	interrupt-parent = <&ipic>;
	168	interrupts = <71 8>;
	169	cell-index = <0>;
	170	dma-channel@0 {
	171	compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
	172	reg = <0 0x80>;
aeb42762	173	cell-index = <0>;
dee80553 KG	174	interrupt-parent = <&ipic>;
	175	interrupts = <71 8>;
	176	};
	177	dma-channel@80 {
	178	compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
	179	reg = <0x80 0x80>;
aeb42762	180	cell-index = <1>;
dee80553 KG	181	interrupt-parent = <&ipic>;
	182	interrupts = <71 8>;
	183	};
	184	dma-channel@100 {
	185	compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
	186	reg = <0x100 0x80>;
aeb42762	187	cell-index = <2>;
dee80553 KG	188	interrupt-parent = <&ipic>;
	189	interrupts = <71 8>;
	190	};
	191	dma-channel@180 {
	192	compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
	193	reg = <0x180 0x28>;
aeb42762	194	cell-index = <3>;
dee80553 KG	195	interrupt-parent = <&ipic>;
	196	interrupts = <71 8>;
	197	};
	198	};
	199
5761bc5d LY	200	usb@23000 {
	201	compatible = "fsl-usb2-dr";
	202	reg = <0x23000 0x1000>;
	203	#address-cells = <1>;
	204	#size-cells = <0>;
cda13dd1 PG	205	interrupt-parent = <&ipic>;
cda13dd1 PG	206	interrupts = <38 0x8>;
28b95885 LY	207	dr_mode = "host";
28b95885 LY	208	phy_type = "ulpi";
5761bc5d LY	209	};
	210
	211	mdio@24520 {
	212	#address-cells = <1>;
	213	#size-cells = <0>;
	214	compatible = "fsl,gianfar-mdio";
	215	reg = <0x24520 0x20>;
	216	phy2: ethernet-phy@2 {
cda13dd1 PG	217	interrupt-parent = <&ipic>;
	218	interrupts = <17 0x8>;
	219	reg = <0x2>;
5761bc5d LY	220	device_type = "ethernet-phy";
	221	};
	222	phy3: ethernet-phy@3 {
cda13dd1 PG	223	interrupt-parent = <&ipic>;
	224	interrupts = <18 0x8>;
	225	reg = <0x3>;
5761bc5d LY	226	device_type = "ethernet-phy";
	227	};
	228	};
	229
	230	enet0: ethernet@24000 {
	231	cell-index = <0>;
	232	device_type = "network";
	233	model = "eTSEC";
	234	compatible = "gianfar";
	235	reg = <0x24000 0x1000>;
	236	local-mac-address = [ 00 00 00 00 00 00 ];
cda13dd1	237	interrupts = <32 0x8 33 0x8 34 0x8>;
5761bc5d	238	phy-connection-type = "mii";
cda13dd1 PG	239	interrupt-parent = <&ipic>;
cda13dd1 PG	240	phy-handle = <&phy2>;
5761bc5d LY	241	};
	242
	243	enet1: ethernet@25000 {
	244	cell-index = <1>;
	245	device_type = "network";
	246	model = "eTSEC";
	247	compatible = "gianfar";
	248	reg = <0x25000 0x1000>;
	249	local-mac-address = [ 00 00 00 00 00 00 ];
cda13dd1	250	interrupts = <35 0x8 36 0x8 37 0x8>;
5761bc5d	251	phy-connection-type = "mii";
cda13dd1 PG	252	interrupt-parent = <&ipic>;
cda13dd1 PG	253	phy-handle = <&phy3>;
5761bc5d LY	254	};
	255
	256	serial0: serial@4500 {
	257	cell-index = <0>;
	258	device_type = "serial";
	259	compatible = "ns16550";
	260	reg = <0x4500 0x100>;
	261	clock-frequency = <0>;
cda13dd1 PG	262	interrupts = <9 0x8>;
cda13dd1 PG	263	interrupt-parent = <&ipic>;
5761bc5d LY	264	};
	265
	266	serial1: serial@4600 {
	267	cell-index = <1>;
	268	device_type = "serial";
	269	compatible = "ns16550";
	270	reg = <0x4600 0x100>;
	271	clock-frequency = <0>;
cda13dd1 PG	272	interrupts = <10 0x8>;
cda13dd1 PG	273	interrupt-parent = <&ipic>;
5761bc5d LY	274	};
	275
	276	crypto@30000 {
3fd44736 KP	277	compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
3fd44736 KP	278	"fsl,sec2.1", "fsl,sec2.0";
5761bc5d	279	reg = <0x30000 0x10000>;
cda13dd1 PG	280	interrupts = <11 0x8>;
cda13dd1 PG	281	interrupt-parent = <&ipic>;
3fd44736 KP	282	fsl,num-channels = <4>;
	283	fsl,channel-fifo-len = <24>;
	284	fsl,exec-units-mask = <0x9fe>;
	285	fsl,descriptor-types-mask = <0x3ab0ebf>;
5761bc5d LY	286	};
	287
	288	sdhc@2e000 {
	289	model = "eSDHC";
	290	compatible = "fsl,esdhc";
	291	reg = <0x2e000 0x1000>;
cda13dd1 PG	292	interrupts = <42 0x8>;
cda13dd1 PG	293	interrupt-parent = <&ipic>;
5761bc5d LY	294	};
	295
	296	sata@18000 {
96ce1b6d	297	compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
5761bc5d	298	reg = <0x18000 0x1000>;
cda13dd1 PG	299	interrupts = <44 0x8>;
cda13dd1 PG	300	interrupt-parent = <&ipic>;
5761bc5d LY	301	};
	302
	303	sata@19000 {
96ce1b6d	304	compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
5761bc5d	305	reg = <0x19000 0x1000>;
cda13dd1 PG	306	interrupts = <45 0x8>;
cda13dd1 PG	307	interrupt-parent = <&ipic>;
5761bc5d LY	308	};
	309
	310	sata@1a000 {
96ce1b6d	311	compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
5761bc5d	312	reg = <0x1a000 0x1000>;
cda13dd1 PG	313	interrupts = <46 0x8>;
cda13dd1 PG	314	interrupt-parent = <&ipic>;
5761bc5d LY	315	};
	316
	317	sata@1b000 {
96ce1b6d	318	compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
5761bc5d	319	reg = <0x1b000 0x1000>;
cda13dd1 PG	320	interrupts = <47 0x8>;
cda13dd1 PG	321	interrupt-parent = <&ipic>;
5761bc5d LY	322	};
	323
	324	/* IPIC
	325	* interrupts cell = <intr #, sense>
	326	* sense values match linux IORESOURCE_IRQ_* defines:
	327	* sense == 8: Level, low assertion
	328	* sense == 2: Edge, high-to-low change
	329	*/
	330	ipic: pic@700 {
	331	compatible = "fsl,ipic";
	332	interrupt-controller;
	333	#address-cells = <0>;
	334	#interrupt-cells = <2>;
	335	reg = <0x700 0x100>;
	336	};
	337	};
	338
	339	pci0: pci@e0008500 {
	340	cell-index = <0>;
	341	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
	342	interrupt-map = <
	343
	344	/* IDSEL 0x11 */
cda13dd1 PG	345	0x8800 0x0 0x0 0x1 &ipic 20 0x8
	346	0x8800 0x0 0x0 0x2 &ipic 21 0x8
	347	0x8800 0x0 0x0 0x3 &ipic 22 0x8
	348	0x8800 0x0 0x0 0x4 &ipic 23 0x8
5761bc5d LY	349
5761bc5d LY	350	/* IDSEL 0x12 */
cda13dd1 PG	351	0x9000 0x0 0x0 0x1 &ipic 22 0x8
	352	0x9000 0x0 0x0 0x2 &ipic 23 0x8
	353	0x9000 0x0 0x0 0x3 &ipic 20 0x8
	354	0x9000 0x0 0x0 0x4 &ipic 21 0x8
5761bc5d LY	355
5761bc5d LY	356	/* IDSEL 0x13 */
cda13dd1 PG	357	0x9800 0x0 0x0 0x1 &ipic 23 0x8
	358	0x9800 0x0 0x0 0x2 &ipic 20 0x8
	359	0x9800 0x0 0x0 0x3 &ipic 21 0x8
	360	0x9800 0x0 0x0 0x4 &ipic 22 0x8
5761bc5d LY	361
5761bc5d LY	362	/* IDSEL 0x15 */
cda13dd1 PG	363	0xa800 0x0 0x0 0x1 &ipic 20 0x8
	364	0xa800 0x0 0x0 0x2 &ipic 21 0x8
	365	0xa800 0x0 0x0 0x3 &ipic 22 0x8
	366	0xa800 0x0 0x0 0x4 &ipic 23 0x8
5761bc5d LY	367
5761bc5d LY	368	/* IDSEL 0x16 */
cda13dd1 PG	369	0xb000 0x0 0x0 0x1 &ipic 23 0x8
	370	0xb000 0x0 0x0 0x2 &ipic 20 0x8
	371	0xb000 0x0 0x0 0x3 &ipic 21 0x8
	372	0xb000 0x0 0x0 0x4 &ipic 22 0x8
5761bc5d LY	373
5761bc5d LY	374	/* IDSEL 0x17 */
cda13dd1 PG	375	0xb800 0x0 0x0 0x1 &ipic 22 0x8
	376	0xb800 0x0 0x0 0x2 &ipic 23 0x8
	377	0xb800 0x0 0x0 0x3 &ipic 20 0x8
	378	0xb800 0x0 0x0 0x4 &ipic 21 0x8
5761bc5d LY	379
5761bc5d LY	380	/* IDSEL 0x18 */
cda13dd1 PG	381	0xc000 0x0 0x0 0x1 &ipic 21 0x8
	382	0xc000 0x0 0x0 0x2 &ipic 22 0x8
	383	0xc000 0x0 0x0 0x3 &ipic 23 0x8
	384	0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
	385	interrupt-parent = <&ipic>;
	386	interrupts = <66 0x8>;
	387	bus-range = <0x0 0x0>;
5761bc5d LY	388	ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
	389	0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
	390	0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
	391	clock-frequency = <0>;
	392	#interrupt-cells = <1>;
	393	#size-cells = <2>;
	394	#address-cells = <3>;
	395	reg = <0xe0008500 0x100>;
	396	compatible = "fsl,mpc8349-pci";
	397	device_type = "pci";
	398	};
	399	};