[deliverable/linux.git] / arch / powerpc / boot / dts / mpc8379_mds.dts

/*
 * MPC8379E MDS Device Tree Source
 *
 * Copyright 2007 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/dts-v1/;

/ {
	model = "fsl,mpc8379emds";
	compatible = "fsl,mpc8379emds","fsl,mpc837xmds";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8379@0 {
			device_type = "cpu";
			reg = <0>;
			d-cache-line-size = <0x20>;
			i-cache-line-size = <0x20>;
			d-cache-size = <0x8000>;		// L1, 32K
			i-cache-size = <0x8000>;		// L1, 32K
			timebase-frequency = <0>;
			bus-frequency = <0>;
			clock-frequency = <0>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x20000000>;	// 512MB at 0
	};

	soc@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		ranges = <0x0 0xe0000000 0x00100000>;
		reg = <0xe0000000 0x00000200>;
		bus-frequency = <0>;

		wdt@200 {
			compatible = "mpc83xx_wdt";
			reg = <0x200 0x100>;
		};

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <0xe 0x8>;
			interrupt-parent = < &ipic >;
			dfsrr;
		};

		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <0xf 0x8>;
			interrupt-parent = < &ipic >;
			dfsrr;
		};

		spi@7000 {
			compatible = "fsl_spi";
			reg = <0x7000 0x1000>;
			interrupts = <0x10 0x8>;
			interrupt-parent = < &ipic >;
			mode = "cpu";
		};

		/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
		usb@23000 {
			compatible = "fsl-usb2-dr";
			reg = <0x23000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupt-parent = < &ipic >;
			interrupts = <0x26 0x8>;
			phy_type = "utmi_wide";
		};

		mdio@24520 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,gianfar-mdio";
			reg = <0x24520 0x20>;
			phy2: ethernet-phy@2 {
				interrupt-parent = < &ipic >;
				interrupts = <0x11 0x8>;
				reg = <2>;
				device_type = "ethernet-phy";
			};
			phy3: ethernet-phy@3 {
				interrupt-parent = < &ipic >;
				interrupts = <0x12 0x8>;
				reg = <3>;
				device_type = "ethernet-phy";
			};
		};

		enet0: ethernet@24000 {
			cell-index = <0>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x24000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <0x20 0x8 0x21 0x8 0x22 0x8>;
			phy-connection-type = "mii";
			interrupt-parent = < &ipic >;
			phy-handle = < &phy2 >;
		};

		enet1: ethernet@25000 {
			cell-index = <1>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x25000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <0x23 0x8 0x24 0x8 0x25 0x8>;
			phy-connection-type = "mii";
			interrupt-parent = < &ipic >;
			phy-handle = < &phy3 >;
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4500 0x100>;
			clock-frequency = <0>;
			interrupts = <0x9 0x8>;
			interrupt-parent = < &ipic >;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4600 0x100>;
			clock-frequency = <0>;
			interrupts = <0xa 0x8>;
			interrupt-parent = < &ipic >;
		};

		crypto@30000 {
			model = "SEC3";
			compatible = "talitos";
			reg = <0x30000 0x10000>;
			interrupts = <0xb 0x8>;
			interrupt-parent = < &ipic >;
			/* Rev. 3.0 geometry */
			num-channels = <4>;
			channel-fifo-len = <0x18>;
			exec-units-mask = <0x000001fe>;
			descriptor-types-mask = <0x03ab0ebf>;
		};

		sdhc@2e000 {
			model = "eSDHC";
			compatible = "fsl,esdhc";
			reg = <0x2e000 0x1000>;
			interrupts = <0x2a 0x8>;
			interrupt-parent = < &ipic >;
		};

		sata@18000 {
			compatible = "fsl,mpc8379-sata";
			reg = <0x18000 0x1000>;
			interrupts = <0x2c 0x8>;
			interrupt-parent = < &ipic >;
		};

		sata@19000 {
			compatible = "fsl,mpc8379-sata";
			reg = <0x19000 0x1000>;
			interrupts = <0x2d 0x8>;
			interrupt-parent = < &ipic >;
		};

		sata@1a000 {
			compatible = "fsl,mpc8379-sata";
			reg = <0x1a000 0x1000>;
			interrupts = <0x2e 0x8>;
			interrupt-parent = < &ipic >;
		};

		sata@1b000 {
			compatible = "fsl,mpc8379-sata";
			reg = <0x1b000 0x1000>;
			interrupts = <0x2f 0x8>;
			interrupt-parent = < &ipic >;
		};

		/* IPIC
		 * interrupts cell = <intr #, sense>
		 * sense values match linux IORESOURCE_IRQ_* defines:
		 * sense == 8: Level, low assertion
		 * sense == 2: Edge, high-to-low change
		 */
		ipic: pic@700 {
			compatible = "fsl,ipic";
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x700 0x100>;
		};
	};

	pci0: pci@e0008500 {
		cell-index = <0>;
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <

				/* IDSEL 0x11 */
				 0x8800 0x0 0x0 0x1 &ipic 0x14 0x8
				 0x8800 0x0 0x0 0x2 &ipic 0x15 0x8
				 0x8800 0x0 0x0 0x3 &ipic 0x16 0x8
				 0x8800 0x0 0x0 0x4 &ipic 0x17 0x8

				/* IDSEL 0x12 */
				 0x9000 0x0 0x0 0x1 &ipic 0x16 0x8
				 0x9000 0x0 0x0 0x2 &ipic 0x17 0x8
				 0x9000 0x0 0x0 0x3 &ipic 0x14 0x8
				 0x9000 0x0 0x0 0x4 &ipic 0x15 0x8

				/* IDSEL 0x13 */
				 0x9800 0x0 0x0 0x1 &ipic 0x17 0x8
				 0x9800 0x0 0x0 0x2 &ipic 0x14 0x8
				 0x9800 0x0 0x0 0x3 &ipic 0x15 0x8
				 0x9800 0x0 0x0 0x4 &ipic 0x16 0x8

				/* IDSEL 0x15 */
				 0xa800 0x0 0x0 0x1 &ipic 0x14 0x8
				 0xa800 0x0 0x0 0x2 &ipic 0x15 0x8
				 0xa800 0x0 0x0 0x3 &ipic 0x16 0x8
				 0xa800 0x0 0x0 0x4 &ipic 0x17 0x8

				/* IDSEL 0x16 */
				 0xb000 0x0 0x0 0x1 &ipic 0x17 0x8
				 0xb000 0x0 0x0 0x2 &ipic 0x14 0x8
				 0xb000 0x0 0x0 0x3 &ipic 0x15 0x8
				 0xb000 0x0 0x0 0x4 &ipic 0x16 0x8

				/* IDSEL 0x17 */
				 0xb800 0x0 0x0 0x1 &ipic 0x16 0x8
				 0xb800 0x0 0x0 0x2 &ipic 0x17 0x8
				 0xb800 0x0 0x0 0x3 &ipic 0x14 0x8
				 0xb800 0x0 0x0 0x4 &ipic 0x15 0x8

				/* IDSEL 0x18 */
				 0xc000 0x0 0x0 0x1 &ipic 0x15 0x8
				 0xc000 0x0 0x0 0x2 &ipic 0x16 0x8
				 0xc000 0x0 0x0 0x3 &ipic 0x17 0x8
				 0xc000 0x0 0x0 0x4 &ipic 0x14 0x8>;
		interrupt-parent = < &ipic >;
		interrupts = <0x42 0x8>;
		bus-range = <0 0>;
		ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
		          0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
		          0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
		clock-frequency = <0>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0008500 0x100>;
		compatible = "fsl,mpc8349-pci";
		device_type = "pci";
	};
};
Commit	Line	Data
5761bc5d LY	1	/*
	2	* MPC8379E MDS Device Tree Source
	3	*
	4	* Copyright 2007 Freescale Semiconductor Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*/
	11
	12	/dts-v1/;
	13
	14	/ {
	15	model = "fsl,mpc8379emds";
	16	compatible = "fsl,mpc8379emds","fsl,mpc837xmds";
	17	#address-cells = <1>;
	18	#size-cells = <1>;
	19
	20	aliases {
	21	ethernet0 = &enet0;
	22	ethernet1 = &enet1;
	23	serial0 = &serial0;
	24	serial1 = &serial1;
	25	pci0 = &pci0;
	26	};
	27
	28	cpus {
	29	#address-cells = <1>;
	30	#size-cells = <0>;
	31
	32	PowerPC,8379@0 {
	33	device_type = "cpu";
	34	reg = <0>;
	35	d-cache-line-size = <0x20>;
	36	i-cache-line-size = <0x20>;
	37	d-cache-size = <0x8000>; // L1, 32K
	38	i-cache-size = <0x8000>; // L1, 32K
	39	timebase-frequency = <0>;
	40	bus-frequency = <0>;
	41	clock-frequency = <0>;
	42	};
	43	};
	44
	45	memory {
	46	device_type = "memory";
	47	reg = <0x00000000 0x20000000>; // 512MB at 0
	48	};
	49
	50	soc@e0000000 {
	51	#address-cells = <1>;
	52	#size-cells = <1>;
	53	device_type = "soc";
	54	ranges = <0x0 0xe0000000 0x00100000>;
	55	reg = <0xe0000000 0x00000200>;
	56	bus-frequency = <0>;
	57
	58	wdt@200 {
	59	compatible = "mpc83xx_wdt";
	60	reg = <0x200 0x100>;
	61	};
	62
	63	i2c@3000 {
	64	#address-cells = <1>;
65	#size-cells = <0>;
66	cell-index = <0>;
67	compatible = "fsl-i2c";
68	reg = <0x3000 0x100>;
69	interrupts = <0xe 0x8>;
70	interrupt-parent = < &ipic >;
71	dfsrr;
72	};
73
74	i2c@3100 {
75	#address-cells = <1>;
76	#size-cells = <0>;
77	cell-index = <1>;
78	compatible = "fsl-i2c";
79	reg = <0x3100 0x100>;
80	interrupts = <0xf 0x8>;
81	interrupt-parent = < &ipic >;
82	dfsrr;
83	};
84
85	spi@7000 {
86	compatible = "fsl_spi";
87	reg = <0x7000 0x1000>;
88	interrupts = <0x10 0x8>;
89	interrupt-parent = < &ipic >;
90	mode = "cpu";
91	};
92
93	/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
94	usb@23000 {
95	compatible = "fsl-usb2-dr";
96	reg = <0x23000 0x1000>;
97	#address-cells = <1>;
98	#size-cells = <0>;
99	interrupt-parent = < &ipic >;
100	interrupts = <0x26 0x8>;
101	phy_type = "utmi_wide";
102	};
103
104	mdio@24520 {
105	#address-cells = <1>;
106	#size-cells = <0>;
107	compatible = "fsl,gianfar-mdio";
108	reg = <0x24520 0x20>;
109	phy2: ethernet-phy@2 {
110	interrupt-parent = < &ipic >;
111	interrupts = <0x11 0x8>;
112	reg = <2>;
113	device_type = "ethernet-phy";
114	};
115	phy3: ethernet-phy@3 {
116	interrupt-parent = < &ipic >;
117	interrupts = <0x12 0x8>;
118	reg = <3>;
119	device_type = "ethernet-phy";
120	};
121	};
122
123	enet0: ethernet@24000 {
124	cell-index = <0>;
125	device_type = "network";
126	model = "eTSEC";
127	compatible = "gianfar";
128	reg = <0x24000 0x1000>;
129	local-mac-address = [ 00 00 00 00 00 00 ];
130	interrupts = <0x20 0x8 0x21 0x8 0x22 0x8>;
131	phy-connection-type = "mii";
132	interrupt-parent = < &ipic >;
133	phy-handle = < &phy2 >;
134	};
135
136	enet1: ethernet@25000 {
137	cell-index = <1>;
138	device_type = "network";
139	model = "eTSEC";
140	compatible = "gianfar";
141	reg = <0x25000 0x1000>;
142	local-mac-address = [ 00 00 00 00 00 00 ];
143	interrupts = <0x23 0x8 0x24 0x8 0x25 0x8>;
144	phy-connection-type = "mii";
145	interrupt-parent = < &ipic >;
146	phy-handle = < &phy3 >;
147	};
148
149	serial0: serial@4500 {
150	cell-index = <0>;
151	device_type = "serial";
152	compatible = "ns16550";
153	reg = <0x4500 0x100>;
154	clock-frequency = <0>;
155	interrupts = <0x9 0x8>;
156	interrupt-parent = < &ipic >;
157	};
158
159	serial1: serial@4600 {
160	cell-index = <1>;
161	device_type = "serial";
162	compatible = "ns16550";
163	reg = <0x4600 0x100>;
164	clock-frequency = <0>;
165	interrupts = <0xa 0x8>;
166	interrupt-parent = < &ipic >;
167	};
168
169	crypto@30000 {
170	model = "SEC3";
171	compatible = "talitos";
172	reg = <0x30000 0x10000>;
173	interrupts = <0xb 0x8>;
174	interrupt-parent = < &ipic >;
175	/* Rev. 3.0 geometry */
176	num-channels = <4>;
177	channel-fifo-len = <0x18>;
178	exec-units-mask = <0x000001fe>;
179	descriptor-types-mask = <0x03ab0ebf>;
180	};
181
182	sdhc@2e000 {
183	model = "eSDHC";
184	compatible = "fsl,esdhc";
185	reg = <0x2e000 0x1000>;
186	interrupts = <0x2a 0x8>;
187	interrupt-parent = < &ipic >;
188	};
189
190	sata@18000 {
191	compatible = "fsl,mpc8379-sata";
192	reg = <0x18000 0x1000>;
193	interrupts = <0x2c 0x8>;
194	interrupt-parent = < &ipic >;
195	};
196
197	sata@19000 {
198	compatible = "fsl,mpc8379-sata";
199	reg = <0x19000 0x1000>;
200	interrupts = <0x2d 0x8>;
201	interrupt-parent = < &ipic >;
202	};
203
204	sata@1a000 {
205	compatible = "fsl,mpc8379-sata";
206	reg = <0x1a000 0x1000>;
207	interrupts = <0x2e 0x8>;
208	interrupt-parent = < &ipic >;
209	};
210
211	sata@1b000 {
212	compatible = "fsl,mpc8379-sata";
213	reg = <0x1b000 0x1000>;
214	interrupts = <0x2f 0x8>;
215	interrupt-parent = < &ipic >;
216	};
217
218	/* IPIC
219	* interrupts cell = <intr #, sense>
220	* sense values match linux IORESOURCE_IRQ_* defines:
221	* sense == 8: Level, low assertion
222	* sense == 2: Edge, high-to-low change
223	*/
224	ipic: pic@700 {
225	compatible = "fsl,ipic";
226	interrupt-controller;
227	#address-cells = <0>;
228	#interrupt-cells = <2>;
229	reg = <0x700 0x100>;
230	};
231	};
232
233	pci0: pci@e0008500 {
234	cell-index = <0>;
235	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
236	interrupt-map = <
237
238	/* IDSEL 0x11 */
239	0x8800 0x0 0x0 0x1 &ipic 0x14 0x8
240	0x8800 0x0 0x0 0x2 &ipic 0x15 0x8
241	0x8800 0x0 0x0 0x3 &ipic 0x16 0x8
242	0x8800 0x0 0x0 0x4 &ipic 0x17 0x8
243
244	/* IDSEL 0x12 */
245	0x9000 0x0 0x0 0x1 &ipic 0x16 0x8
246	0x9000 0x0 0x0 0x2 &ipic 0x17 0x8
247	0x9000 0x0 0x0 0x3 &ipic 0x14 0x8
248	0x9000 0x0 0x0 0x4 &ipic 0x15 0x8
249
250	/* IDSEL 0x13 */
251	0x9800 0x0 0x0 0x1 &ipic 0x17 0x8
252	0x9800 0x0 0x0 0x2 &ipic 0x14 0x8
253	0x9800 0x0 0x0 0x3 &ipic 0x15 0x8
254	0x9800 0x0 0x0 0x4 &ipic 0x16 0x8
255
256	/* IDSEL 0x15 */
257	0xa800 0x0 0x0 0x1 &ipic 0x14 0x8
258	0xa800 0x0 0x0 0x2 &ipic 0x15 0x8
259	0xa800 0x0 0x0 0x3 &ipic 0x16 0x8
260	0xa800 0x0 0x0 0x4 &ipic 0x17 0x8
261
262	/* IDSEL 0x16 */
263	0xb000 0x0 0x0 0x1 &ipic 0x17 0x8
264	0xb000 0x0 0x0 0x2 &ipic 0x14 0x8
265	0xb000 0x0 0x0 0x3 &ipic 0x15 0x8
266	0xb000 0x0 0x0 0x4 &ipic 0x16 0x8
267
268	/* IDSEL 0x17 */
269	0xb800 0x0 0x0 0x1 &ipic 0x16 0x8
270	0xb800 0x0 0x0 0x2 &ipic 0x17 0x8
271	0xb800 0x0 0x0 0x3 &ipic 0x14 0x8
272	0xb800 0x0 0x0 0x4 &ipic 0x15 0x8
273
274	/* IDSEL 0x18 */
275	0xc000 0x0 0x0 0x1 &ipic 0x15 0x8
276	0xc000 0x0 0x0 0x2 &ipic 0x16 0x8
277	0xc000 0x0 0x0 0x3 &ipic 0x17 0x8
278	0xc000 0x0 0x0 0x4 &ipic 0x14 0x8>;
279	interrupt-parent = < &ipic >;
280	interrupts = <0x42 0x8>;
281	bus-range = <0 0>;
282	ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
283	0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
284	0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
285	clock-frequency = <0>;
286	#interrupt-cells = <1>;
287	#size-cells = <2>;
288	#address-cells = <3>;
289	reg = <0xe0008500 0x100>;
290	compatible = "fsl,mpc8349-pci";
291	device_type = "pci";
292	};
293	};