[deliverable/linux.git] / arch / powerpc / boot / dts / mpc8379_mds.dts

/*
 * MPC8379E MDS Device Tree Source
 *
 * Copyright 2007 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/dts-v1/;

/ {
	model = "fsl,mpc8379emds";
	compatible = "fsl,mpc8379emds","fsl,mpc837xmds";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8379@0 {
			device_type = "cpu";
			reg = <0x0>;
			d-cache-line-size = <32>;
			i-cache-line-size = <32>;
			d-cache-size = <32768>;
			i-cache-size = <32768>;
			timebase-frequency = <0>;
			bus-frequency = <0>;
			clock-frequency = <0>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x20000000>;	// 512MB at 0
	};

	localbus@e0005000 {
		#address-cells = <2>;
		#size-cells = <1>;
		compatible = "fsl,mpc8379-elbc", "fsl,elbc", "simple-bus";
		reg = <0xe0005000 0x1000>;
		interrupts = <77 0x8>;
		interrupt-parent = <&ipic>;

		// booting from NOR flash
		ranges = <0 0x0 0xfe000000 0x02000000
		          1 0x0 0xf8000000 0x00008000
		          3 0x0 0xe0600000 0x00008000>;

		flash@0,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "cfi-flash";
			reg = <0 0x0 0x2000000>;
			bank-width = <2>;
			device-width = <1>;

			u-boot@0 {
				reg = <0x0 0x100000>;
				read-only;
			};

			fs@100000 {
				reg = <0x100000 0x800000>;
			};

			kernel@1d00000 {
				reg = <0x1d00000 0x200000>;
			};

			dtb@1f00000 {
				reg = <0x1f00000 0x100000>;
			};
		};

		bcsr@1,0 {
			reg = <1 0x0 0x8000>;
			compatible = "fsl,mpc837xmds-bcsr";
		};

		nand@3,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8379-fcm-nand",
			             "fsl,elbc-fcm-nand";
			reg = <3 0x0 0x8000>;

			u-boot@0 {
				reg = <0x0 0x100000>;
				read-only;
			};

			kernel@100000 {
				reg = <0x100000 0x300000>;
			};

			fs@400000 {
				reg = <0x400000 0x1c00000>;
			};
		};
	};

	soc@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		ranges = <0x0 0xe0000000 0x00100000>;
		reg = <0xe0000000 0x00000200>;
		bus-frequency = <0>;

		wdt@200 {
			compatible = "mpc83xx_wdt";
			reg = <0x200 0x100>;
		};

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <14 0x8>;
			interrupt-parent = <&ipic>;
			dfsrr;
		};

		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <15 0x8>;
			interrupt-parent = <&ipic>;
			dfsrr;
		};

		spi@7000 {
			cell-index = <0>;
			compatible = "fsl,spi";
			reg = <0x7000 0x1000>;
			interrupts = <16 0x8>;
			interrupt-parent = <&ipic>;
			mode = "cpu";
		};

		dma@82a8 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8379-dma", "fsl,elo-dma";
			reg = <0x82a8 4>;
			ranges = <0 0x8100 0x1a8>;
			interrupt-parent = <&ipic>;
			interrupts = <71 8>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
				reg = <0 0x80>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
			dma-channel@80 {
				compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
				reg = <0x80 0x80>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
			dma-channel@100 {
				compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
				reg = <0x100 0x80>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
			dma-channel@180 {
				compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
				reg = <0x180 0x28>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
		};

		usb@23000 {
			compatible = "fsl-usb2-dr";
			reg = <0x23000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupt-parent = <&ipic>;
			interrupts = <38 0x8>;
			dr_mode = "host";
			phy_type = "ulpi";
		};

		mdio@24520 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,gianfar-mdio";
			reg = <0x24520 0x20>;
			phy2: ethernet-phy@2 {
				interrupt-parent = <&ipic>;
				interrupts = <17 0x8>;
				reg = <0x2>;
				device_type = "ethernet-phy";
			};
			phy3: ethernet-phy@3 {
				interrupt-parent = <&ipic>;
				interrupts = <18 0x8>;
				reg = <0x3>;
				device_type = "ethernet-phy";
			};
		};

		enet0: ethernet@24000 {
			cell-index = <0>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x24000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <32 0x8 33 0x8 34 0x8>;
			phy-connection-type = "mii";
			interrupt-parent = <&ipic>;
			phy-handle = <&phy2>;
		};

		enet1: ethernet@25000 {
			cell-index = <1>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x25000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <35 0x8 36 0x8 37 0x8>;
			phy-connection-type = "mii";
			interrupt-parent = <&ipic>;
			phy-handle = <&phy3>;
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4500 0x100>;
			clock-frequency = <0>;
			interrupts = <9 0x8>;
			interrupt-parent = <&ipic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4600 0x100>;
			clock-frequency = <0>;
			interrupts = <10 0x8>;
			interrupt-parent = <&ipic>;
		};

		crypto@30000 {
			compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
				     "fsl,sec2.1", "fsl,sec2.0";
			reg = <0x30000 0x10000>;
			interrupts = <11 0x8>;
			interrupt-parent = <&ipic>;
			fsl,num-channels = <4>;
			fsl,channel-fifo-len = <24>;
			fsl,exec-units-mask = <0x9fe>;
			fsl,descriptor-types-mask = <0x3ab0ebf>;
		};

		sdhc@2e000 {
			model = "eSDHC";
			compatible = "fsl,esdhc";
			reg = <0x2e000 0x1000>;
			interrupts = <42 0x8>;
			interrupt-parent = <&ipic>;
		};

		sata@18000 {
			compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
			reg = <0x18000 0x1000>;
			interrupts = <44 0x8>;
			interrupt-parent = <&ipic>;
		};

		sata@19000 {
			compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
			reg = <0x19000 0x1000>;
			interrupts = <45 0x8>;
			interrupt-parent = <&ipic>;
		};

		sata@1a000 {
			compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
			reg = <0x1a000 0x1000>;
			interrupts = <46 0x8>;
			interrupt-parent = <&ipic>;
		};

		sata@1b000 {
			compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
			reg = <0x1b000 0x1000>;
			interrupts = <47 0x8>;
			interrupt-parent = <&ipic>;
		};

		/* IPIC
		 * interrupts cell = <intr #, sense>
		 * sense values match linux IORESOURCE_IRQ_* defines:
		 * sense == 8: Level, low assertion
		 * sense == 2: Edge, high-to-low change
		 */
		ipic: pic@700 {
			compatible = "fsl,ipic";
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x700 0x100>;
		};
	};

	pci0: pci@e0008500 {
		cell-index = <0>;
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <

				/* IDSEL 0x11 */
				 0x8800 0x0 0x0 0x1 &ipic 20 0x8
				 0x8800 0x0 0x0 0x2 &ipic 21 0x8
				 0x8800 0x0 0x0 0x3 &ipic 22 0x8
				 0x8800 0x0 0x0 0x4 &ipic 23 0x8

				/* IDSEL 0x12 */
				 0x9000 0x0 0x0 0x1 &ipic 22 0x8
				 0x9000 0x0 0x0 0x2 &ipic 23 0x8
				 0x9000 0x0 0x0 0x3 &ipic 20 0x8
				 0x9000 0x0 0x0 0x4 &ipic 21 0x8

				/* IDSEL 0x13 */
				 0x9800 0x0 0x0 0x1 &ipic 23 0x8
				 0x9800 0x0 0x0 0x2 &ipic 20 0x8
				 0x9800 0x0 0x0 0x3 &ipic 21 0x8
				 0x9800 0x0 0x0 0x4 &ipic 22 0x8

				/* IDSEL 0x15 */
				 0xa800 0x0 0x0 0x1 &ipic 20 0x8
				 0xa800 0x0 0x0 0x2 &ipic 21 0x8
				 0xa800 0x0 0x0 0x3 &ipic 22 0x8
				 0xa800 0x0 0x0 0x4 &ipic 23 0x8

				/* IDSEL 0x16 */
				 0xb000 0x0 0x0 0x1 &ipic 23 0x8
				 0xb000 0x0 0x0 0x2 &ipic 20 0x8
				 0xb000 0x0 0x0 0x3 &ipic 21 0x8
				 0xb000 0x0 0x0 0x4 &ipic 22 0x8

				/* IDSEL 0x17 */
				 0xb800 0x0 0x0 0x1 &ipic 22 0x8
				 0xb800 0x0 0x0 0x2 &ipic 23 0x8
				 0xb800 0x0 0x0 0x3 &ipic 20 0x8
				 0xb800 0x0 0x0 0x4 &ipic 21 0x8

				/* IDSEL 0x18 */
				 0xc000 0x0 0x0 0x1 &ipic 21 0x8
				 0xc000 0x0 0x0 0x2 &ipic 22 0x8
				 0xc000 0x0 0x0 0x3 &ipic 23 0x8
				 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
		interrupt-parent = <&ipic>;
		interrupts = <66 0x8>;
		bus-range = <0x0 0x0>;
		ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
		          0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
		          0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
		clock-frequency = <0>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0008500 0x100>;
		compatible = "fsl,mpc8349-pci";
		device_type = "pci";
	};
};
Commit	Line	Data
5761bc5d LY	1	/*
	2	* MPC8379E MDS Device Tree Source
	3	*
	4	* Copyright 2007 Freescale Semiconductor Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*/
	11
	12	/dts-v1/;
	13
	14	/ {
	15	model = "fsl,mpc8379emds";
	16	compatible = "fsl,mpc8379emds","fsl,mpc837xmds";
	17	#address-cells = <1>;
	18	#size-cells = <1>;
	19
	20	aliases {
	21	ethernet0 = &enet0;
	22	ethernet1 = &enet1;
	23	serial0 = &serial0;
	24	serial1 = &serial1;
	25	pci0 = &pci0;
	26	};
	27
	28	cpus {
	29	#address-cells = <1>;
	30	#size-cells = <0>;
	31
	32	PowerPC,8379@0 {
	33	device_type = "cpu";
cda13dd1 PG	34	reg = <0x0>;
	35	d-cache-line-size = <32>;
	36	i-cache-line-size = <32>;
	37	d-cache-size = <32768>;
	38	i-cache-size = <32768>;
5761bc5d LY	39	timebase-frequency = <0>;
	40	bus-frequency = <0>;
	41	clock-frequency = <0>;
	42	};
	43	};
	44
	45	memory {
	46	device_type = "memory";
	47	reg = <0x00000000 0x20000000>; // 512MB at 0
	48	};
	49
d7f46190 LY	50	localbus@e0005000 {
	51	#address-cells = <2>;
	52	#size-cells = <1>;
	53	compatible = "fsl,mpc8379-elbc", "fsl,elbc", "simple-bus";
	54	reg = <0xe0005000 0x1000>;
	55	interrupts = <77 0x8>;
	56	interrupt-parent = <&ipic>;
	57
	58	// booting from NOR flash
	59	ranges = <0 0x0 0xfe000000 0x02000000
	60	1 0x0 0xf8000000 0x00008000
	61	3 0x0 0xe0600000 0x00008000>;
	62
	63	flash@0,0 {
	64	#address-cells = <1>;
	65	#size-cells = <1>;
	66	compatible = "cfi-flash";
	67	reg = <0 0x0 0x2000000>;
	68	bank-width = <2>;
	69	device-width = <1>;
	70
	71	u-boot@0 {
	72	reg = <0x0 0x100000>;
	73	read-only;
	74	};
	75
	76	fs@100000 {
	77	reg = <0x100000 0x800000>;
	78	};
	79
	80	kernel@1d00000 {
	81	reg = <0x1d00000 0x200000>;
	82	};
	83
	84	dtb@1f00000 {
	85	reg = <0x1f00000 0x100000>;
	86	};
	87	};
	88
	89	bcsr@1,0 {
	90	reg = <1 0x0 0x8000>;
	91	compatible = "fsl,mpc837xmds-bcsr";
	92	};
	93
	94	nand@3,0 {
	95	#address-cells = <1>;
	96	#size-cells = <1>;
	97	compatible = "fsl,mpc8379-fcm-nand",
	98	"fsl,elbc-fcm-nand";
	99	reg = <3 0x0 0x8000>;
	100
	101	u-boot@0 {
	102	reg = <0x0 0x100000>;
	103	read-only;
	104	};
	105
	106	kernel@100000 {
	107	reg = <0x100000 0x300000>;
	108	};
	109
	110	fs@400000 {
	111	reg = <0x400000 0x1c00000>;
	112	};
	113	};
114	};
115
5761bc5d LY	116	soc@e0000000 {
	117	#address-cells = <1>;
	118	#size-cells = <1>;
	119	device_type = "soc";
	120	ranges = <0x0 0xe0000000 0x00100000>;
	121	reg = <0xe0000000 0x00000200>;
	122	bus-frequency = <0>;
	123
	124	wdt@200 {
	125	compatible = "mpc83xx_wdt";
	126	reg = <0x200 0x100>;
	127	};
	128
	129	i2c@3000 {
	130	#address-cells = <1>;
	131	#size-cells = <0>;
	132	cell-index = <0>;
	133	compatible = "fsl-i2c";
	134	reg = <0x3000 0x100>;
cda13dd1 PG	135	interrupts = <14 0x8>;
cda13dd1 PG	136	interrupt-parent = <&ipic>;
5761bc5d LY	137	dfsrr;
	138	};
	139
	140	i2c@3100 {
	141	#address-cells = <1>;
	142	#size-cells = <0>;
	143	cell-index = <1>;
	144	compatible = "fsl-i2c";
	145	reg = <0x3100 0x100>;
cda13dd1 PG	146	interrupts = <15 0x8>;
cda13dd1 PG	147	interrupt-parent = <&ipic>;
5761bc5d LY	148	dfsrr;
	149	};
	150
	151	spi@7000 {
f3a2b29d AV	152	cell-index = <0>;
f3a2b29d AV	153	compatible = "fsl,spi";
5761bc5d	154	reg = <0x7000 0x1000>;
cda13dd1 PG	155	interrupts = <16 0x8>;
cda13dd1 PG	156	interrupt-parent = <&ipic>;
5761bc5d LY	157	mode = "cpu";
	158	};
	159
dee80553 KG	160	dma@82a8 {
	161	#address-cells = <1>;
	162	#size-cells = <1>;
	163	compatible = "fsl,mpc8379-dma", "fsl,elo-dma";
	164	reg = <0x82a8 4>;
	165	ranges = <0 0x8100 0x1a8>;
	166	interrupt-parent = <&ipic>;
	167	interrupts = <71 8>;
	168	cell-index = <0>;
	169	dma-channel@0 {
	170	compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
	171	reg = <0 0x80>;
	172	interrupt-parent = <&ipic>;
	173	interrupts = <71 8>;
	174	};
	175	dma-channel@80 {
	176	compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
	177	reg = <0x80 0x80>;
	178	interrupt-parent = <&ipic>;
	179	interrupts = <71 8>;
	180	};
	181	dma-channel@100 {
	182	compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
	183	reg = <0x100 0x80>;
	184	interrupt-parent = <&ipic>;
	185	interrupts = <71 8>;
	186	};
	187	dma-channel@180 {
	188	compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
	189	reg = <0x180 0x28>;
	190	interrupt-parent = <&ipic>;
	191	interrupts = <71 8>;
	192	};
	193	};
	194
5761bc5d LY	195	usb@23000 {
	196	compatible = "fsl-usb2-dr";
	197	reg = <0x23000 0x1000>;
	198	#address-cells = <1>;
	199	#size-cells = <0>;
cda13dd1 PG	200	interrupt-parent = <&ipic>;
cda13dd1 PG	201	interrupts = <38 0x8>;
28b95885 LY	202	dr_mode = "host";
28b95885 LY	203	phy_type = "ulpi";
5761bc5d LY	204	};
	205
	206	mdio@24520 {
	207	#address-cells = <1>;
	208	#size-cells = <0>;
	209	compatible = "fsl,gianfar-mdio";
	210	reg = <0x24520 0x20>;
	211	phy2: ethernet-phy@2 {
cda13dd1 PG	212	interrupt-parent = <&ipic>;
	213	interrupts = <17 0x8>;
	214	reg = <0x2>;
5761bc5d LY	215	device_type = "ethernet-phy";
	216	};
	217	phy3: ethernet-phy@3 {
cda13dd1 PG	218	interrupt-parent = <&ipic>;
	219	interrupts = <18 0x8>;
	220	reg = <0x3>;
5761bc5d LY	221	device_type = "ethernet-phy";
	222	};
	223	};
	224
	225	enet0: ethernet@24000 {
	226	cell-index = <0>;
	227	device_type = "network";
	228	model = "eTSEC";
	229	compatible = "gianfar";
	230	reg = <0x24000 0x1000>;
	231	local-mac-address = [ 00 00 00 00 00 00 ];
cda13dd1	232	interrupts = <32 0x8 33 0x8 34 0x8>;
5761bc5d	233	phy-connection-type = "mii";
cda13dd1 PG	234	interrupt-parent = <&ipic>;
cda13dd1 PG	235	phy-handle = <&phy2>;
5761bc5d LY	236	};
	237
	238	enet1: ethernet@25000 {
	239	cell-index = <1>;
	240	device_type = "network";
	241	model = "eTSEC";
	242	compatible = "gianfar";
	243	reg = <0x25000 0x1000>;
	244	local-mac-address = [ 00 00 00 00 00 00 ];
cda13dd1	245	interrupts = <35 0x8 36 0x8 37 0x8>;
5761bc5d	246	phy-connection-type = "mii";
cda13dd1 PG	247	interrupt-parent = <&ipic>;
cda13dd1 PG	248	phy-handle = <&phy3>;
5761bc5d LY	249	};
	250
	251	serial0: serial@4500 {
	252	cell-index = <0>;
	253	device_type = "serial";
	254	compatible = "ns16550";
	255	reg = <0x4500 0x100>;
	256	clock-frequency = <0>;
cda13dd1 PG	257	interrupts = <9 0x8>;
cda13dd1 PG	258	interrupt-parent = <&ipic>;
5761bc5d LY	259	};
	260
	261	serial1: serial@4600 {
	262	cell-index = <1>;
	263	device_type = "serial";
	264	compatible = "ns16550";
	265	reg = <0x4600 0x100>;
	266	clock-frequency = <0>;
cda13dd1 PG	267	interrupts = <10 0x8>;
cda13dd1 PG	268	interrupt-parent = <&ipic>;
5761bc5d LY	269	};
	270
	271	crypto@30000 {
3fd44736 KP	272	compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
3fd44736 KP	273	"fsl,sec2.1", "fsl,sec2.0";
5761bc5d	274	reg = <0x30000 0x10000>;
cda13dd1 PG	275	interrupts = <11 0x8>;
cda13dd1 PG	276	interrupt-parent = <&ipic>;
3fd44736 KP	277	fsl,num-channels = <4>;
	278	fsl,channel-fifo-len = <24>;
	279	fsl,exec-units-mask = <0x9fe>;
	280	fsl,descriptor-types-mask = <0x3ab0ebf>;
5761bc5d LY	281	};
	282
	283	sdhc@2e000 {
	284	model = "eSDHC";
	285	compatible = "fsl,esdhc";
	286	reg = <0x2e000 0x1000>;
cda13dd1 PG	287	interrupts = <42 0x8>;
cda13dd1 PG	288	interrupt-parent = <&ipic>;
5761bc5d LY	289	};
	290
	291	sata@18000 {
96ce1b6d	292	compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
5761bc5d	293	reg = <0x18000 0x1000>;
cda13dd1 PG	294	interrupts = <44 0x8>;
cda13dd1 PG	295	interrupt-parent = <&ipic>;
5761bc5d LY	296	};
	297
	298	sata@19000 {
96ce1b6d	299	compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
5761bc5d	300	reg = <0x19000 0x1000>;
cda13dd1 PG	301	interrupts = <45 0x8>;
cda13dd1 PG	302	interrupt-parent = <&ipic>;
5761bc5d LY	303	};
	304
	305	sata@1a000 {
96ce1b6d	306	compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
5761bc5d	307	reg = <0x1a000 0x1000>;
cda13dd1 PG	308	interrupts = <46 0x8>;
cda13dd1 PG	309	interrupt-parent = <&ipic>;
5761bc5d LY	310	};
	311
	312	sata@1b000 {
96ce1b6d	313	compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
5761bc5d	314	reg = <0x1b000 0x1000>;
cda13dd1 PG	315	interrupts = <47 0x8>;
cda13dd1 PG	316	interrupt-parent = <&ipic>;
5761bc5d LY	317	};
	318
	319	/* IPIC
	320	* interrupts cell = <intr #, sense>
	321	* sense values match linux IORESOURCE_IRQ_* defines:
	322	* sense == 8: Level, low assertion
	323	* sense == 2: Edge, high-to-low change
	324	*/
	325	ipic: pic@700 {
	326	compatible = "fsl,ipic";
	327	interrupt-controller;
	328	#address-cells = <0>;
	329	#interrupt-cells = <2>;
	330	reg = <0x700 0x100>;
	331	};
	332	};
	333
	334	pci0: pci@e0008500 {
	335	cell-index = <0>;
	336	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
	337	interrupt-map = <
	338
	339	/* IDSEL 0x11 */
cda13dd1 PG	340	0x8800 0x0 0x0 0x1 &ipic 20 0x8
	341	0x8800 0x0 0x0 0x2 &ipic 21 0x8
	342	0x8800 0x0 0x0 0x3 &ipic 22 0x8
	343	0x8800 0x0 0x0 0x4 &ipic 23 0x8
5761bc5d LY	344
5761bc5d LY	345	/* IDSEL 0x12 */
cda13dd1 PG	346	0x9000 0x0 0x0 0x1 &ipic 22 0x8
	347	0x9000 0x0 0x0 0x2 &ipic 23 0x8
	348	0x9000 0x0 0x0 0x3 &ipic 20 0x8
	349	0x9000 0x0 0x0 0x4 &ipic 21 0x8
5761bc5d LY	350
5761bc5d LY	351	/* IDSEL 0x13 */
cda13dd1 PG	352	0x9800 0x0 0x0 0x1 &ipic 23 0x8
	353	0x9800 0x0 0x0 0x2 &ipic 20 0x8
	354	0x9800 0x0 0x0 0x3 &ipic 21 0x8
	355	0x9800 0x0 0x0 0x4 &ipic 22 0x8
5761bc5d LY	356
5761bc5d LY	357	/* IDSEL 0x15 */
cda13dd1 PG	358	0xa800 0x0 0x0 0x1 &ipic 20 0x8
	359	0xa800 0x0 0x0 0x2 &ipic 21 0x8
	360	0xa800 0x0 0x0 0x3 &ipic 22 0x8
	361	0xa800 0x0 0x0 0x4 &ipic 23 0x8
5761bc5d LY	362
5761bc5d LY	363	/* IDSEL 0x16 */
cda13dd1 PG	364	0xb000 0x0 0x0 0x1 &ipic 23 0x8
	365	0xb000 0x0 0x0 0x2 &ipic 20 0x8
	366	0xb000 0x0 0x0 0x3 &ipic 21 0x8
	367	0xb000 0x0 0x0 0x4 &ipic 22 0x8
5761bc5d LY	368
5761bc5d LY	369	/* IDSEL 0x17 */
cda13dd1 PG	370	0xb800 0x0 0x0 0x1 &ipic 22 0x8
	371	0xb800 0x0 0x0 0x2 &ipic 23 0x8
	372	0xb800 0x0 0x0 0x3 &ipic 20 0x8
	373	0xb800 0x0 0x0 0x4 &ipic 21 0x8
5761bc5d LY	374
5761bc5d LY	375	/* IDSEL 0x18 */
cda13dd1 PG	376	0xc000 0x0 0x0 0x1 &ipic 21 0x8
	377	0xc000 0x0 0x0 0x2 &ipic 22 0x8
	378	0xc000 0x0 0x0 0x3 &ipic 23 0x8
	379	0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
	380	interrupt-parent = <&ipic>;
	381	interrupts = <66 0x8>;
	382	bus-range = <0x0 0x0>;
5761bc5d LY	383	ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
	384	0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
	385	0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
	386	clock-frequency = <0>;
	387	#interrupt-cells = <1>;
	388	#size-cells = <2>;
	389	#address-cells = <3>;
	390	reg = <0xe0008500 0x100>;
	391	compatible = "fsl,mpc8349-pci";
	392	device_type = "pci";
	393	};
	394	};