[deliverable/linux.git] / arch / powerpc / boot / dts / mpc8536ds.dts

/*
 * MPC8536 DS Device Tree Source
 *
 * Copyright 2008 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/dts-v1/;

/ {
	model = "fsl,mpc8536ds";
	compatible = "fsl,mpc8536ds";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
		pci1 = &pci1;
		pci2 = &pci2;
		pci3 = &pci3;
	};

	cpus {
		#cpus = <1>;
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8536@0 {
			device_type = "cpu";
			reg = <0>;
			next-level-cache = <&L2>;
		};
	};

	memory {
		device_type = "memory";
		reg = <00000000 00000000>;	// Filled by U-Boot
	};

	soc@ffe00000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		compatible = "simple-bus";
		ranges = <0x0 0xffe00000 0x100000>;
		reg = <0xffe00000 0x1000>;
		bus-frequency = <0>;		// Filled out by uboot.

		memory-controller@2000 {
			compatible = "fsl,mpc8536-memory-controller";
			reg = <0x2000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <18 0x2>;
		};

		L2: l2-cache-controller@20000 {
			compatible = "fsl,mpc8536-l2-cache-controller";
			reg = <0x20000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <16 0x2>;
		};

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <43 0x2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <43 0x2>;
			interrupt-parent = <&mpic>;
			dfsrr;
			rtc@68 {
				compatible = "dallas,ds3232";
				reg = <0x68>;
			};
		};

		dma@21300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8536-dma", "fsl,eloplus-dma";
			reg = <0x21300 4>;
			ranges = <0 0x21100 0x200>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,mpc8536-dma-channel",
					     "fsl,eloplus-dma-channel";
				reg = <0x0 0x80>;
				cell-index = <0>;
				interrupt-parent = <&mpic>;
				interrupts = <14 0x2>;
			};
			dma-channel@80 {
				compatible = "fsl,mpc8536-dma-channel",
					     "fsl,eloplus-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupt-parent = <&mpic>;
				interrupts = <15 0x2>;
			};
			dma-channel@100 {
				compatible = "fsl,mpc8536-dma-channel",
					     "fsl,eloplus-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupt-parent = <&mpic>;
				interrupts = <16 0x2>;
			};
			dma-channel@180 {
				compatible = "fsl,mpc8536-dma-channel",
					     "fsl,eloplus-dma-channel";
				reg = <0x180 0x80>;
				cell-index = <3>;
				interrupt-parent = <&mpic>;
				interrupts = <17 0x2>;
			};
		};

		mdio@24520 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,gianfar-mdio";
			reg = <0x24520 0x20>;

			phy0: ethernet-phy@0 {
				interrupt-parent = <&mpic>;
				interrupts = <10 0x1>;
				reg = <0>;
				device_type = "ethernet-phy";
			};
			phy1: ethernet-phy@1 {
				interrupt-parent = <&mpic>;
				interrupts = <10 0x1>;
				reg = <1>;
				device_type = "ethernet-phy";
			};
		};

		usb@22000 {
			compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
			reg = <0x22000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupt-parent = <&mpic>;
			interrupts = <28 0x2>;
			phy_type = "ulpi";
		};

		usb@23000 {
			compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
			reg = <0x23000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupt-parent = <&mpic>;
			interrupts = <46 0x2>;
			phy_type = "ulpi";
		};

		enet0: ethernet@24000 {
			cell-index = <0>;
			device_type = "network";
			model = "TSEC";
			compatible = "gianfar";
			reg = <0x24000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <29 2 30 2 34 2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy1>;
			phy-connection-type = "rgmii-id";
		};

		enet1: ethernet@26000 {
			cell-index = <1>;
			device_type = "network";
			model = "TSEC";
			compatible = "gianfar";
			reg = <0x26000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <31 2 32 2 33 2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy0>;
			phy-connection-type = "rgmii-id";
		};

		usb@2b000 {
			compatible = "fsl,mpc8536-usb2-dr", "fsl-usb2-dr";
			reg = <0x2b000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupt-parent = <&mpic>;
			interrupts = <60 0x2>;
			dr_mode = "peripheral";
			phy_type = "ulpi";
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4500 0x100>;
			clock-frequency = <0>;
			interrupts = <42 0x2>;
			interrupt-parent = <&mpic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4600 0x100>;
			clock-frequency = <0>;
			interrupts = <42 0x2>;
			interrupt-parent = <&mpic>;
		};

		crypto@30000 {
			compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
				     "fsl,sec2.1", "fsl,sec2.0";
			reg = <0x30000 0x10000>;
			interrupts = <45 2 58 2>;
			interrupt-parent = <&mpic>;
			fsl,num-channels = <4>;
			fsl,channel-fifo-len = <24>;
			fsl,exec-units-mask = <0x9fe>;
			fsl,descriptor-types-mask = <0x3ab0ebf>;
		};

		sata@18000 {
			compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
			reg = <0x18000 0x1000>;
			cell-index = <1>;
			interrupts = <74 0x2>;
			interrupt-parent = <&mpic>;
		};

		sata@19000 {
			compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
			reg = <0x19000 0x1000>;
			cell-index = <2>;
			interrupts = <41 0x2>;
			interrupt-parent = <&mpic>;
		};

		global-utilities@e0000 {	//global utilities block
			compatible = "fsl,mpc8548-guts";
			reg = <0xe0000 0x1000>;
			fsl,has-rstcr;
		};

		mpic: pic@40000 {
			clock-frequency = <0>;
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x40000 0x40000>;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
			big-endian;
		};

		msi@41600 {
			compatible = "fsl,mpc8536-msi", "fsl,mpic-msi";
			reg = <0x41600 0x80>;
			msi-available-ranges = <0 0x100>;
			interrupts = <
				0xe0 0
				0xe1 0
				0xe2 0
				0xe3 0
				0xe4 0
				0xe5 0
				0xe6 0
				0xe7 0>;
			interrupt-parent = <&mpic>;
		};
	};

	pci0: pci@ffe08000 {
		cell-index = <0>;
		compatible = "fsl,mpc8540-pci";
		device_type = "pci";
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <

			/* IDSEL 0x11 J17 Slot 1 */
			0x8800 0 0 1 &mpic 1 1
			0x8800 0 0 2 &mpic 2 1
			0x8800 0 0 3 &mpic 3 1
			0x8800 0 0 4 &mpic 4 1>;

		interrupt-parent = <&mpic>;
		interrupts = <24 0x2>;
		bus-range = <0 0xff>;
		ranges = <0x02000000 0 0x80000000 0x80000000 0 0x10000000
			  0x01000000 0 0x00000000 0xffc00000 0 0x00010000>;
		clock-frequency = <66666666>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xffe08000 0x1000>;
	};

	pci1: pcie@ffe09000 {
		cell-index = <1>;
		compatible = "fsl,mpc8548-pcie";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xffe09000 0x1000>;
		bus-range = <0 0xff>;
		ranges = <0x02000000 0 0x98000000 0x98000000 0 0x08000000
			  0x01000000 0 0x00000000 0xffc20000 0 0x00010000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <25 0x2>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <
			/* IDSEL 0x0 */
			0000 0 0 1 &mpic 4 1
			0000 0 0 2 &mpic 5 1
			0000 0 0 3 &mpic 6 1
			0000 0 0 4 &mpic 7 1
			>;
		pcie@0 {
			reg = <0 0 0 0 0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x02000000 0 0x98000000
				  0x02000000 0 0x98000000
				  0 0x08000000

				  0x01000000 0 0x00000000
				  0x01000000 0 0x00000000
				  0 0x00010000>;
		};
	};

	pci2: pcie@ffe0a000 {
		cell-index = <2>;
		compatible = "fsl,mpc8548-pcie";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xffe0a000 0x1000>;
		bus-range = <0 0xff>;
		ranges = <0x02000000 0 0x90000000 0x90000000 0 0x08000000
			  0x01000000 0 0x00000000 0xffc10000 0 0x00010000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <26 0x2>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <
			/* IDSEL 0x0 */
			0000 0 0 1 &mpic 0 1
			0000 0 0 2 &mpic 1 1
			0000 0 0 3 &mpic 2 1
			0000 0 0 4 &mpic 3 1
			>;
		pcie@0 {
			reg = <0 0 0 0 0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x02000000 0 0x90000000
				  0x02000000 0 0x90000000
				  0 0x08000000

				  0x01000000 0 0x00000000
				  0x01000000 0 0x00000000
				  0 0x00010000>;
		};
	};

	pci3: pcie@ffe0b000 {
		cell-index = <3>;
		compatible = "fsl,mpc8548-pcie";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xffe0b000 0x1000>;
		bus-range = <0 0xff>;
		ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000
			  0x01000000 0 0x00000000 0xffc30000 0 0x00010000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <27 0x2>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <
			/* IDSEL 0x0 */
			0000 0 0 1 &mpic 8 1
			0000 0 0 2 &mpic 9 1
			0000 0 0 3 &mpic 10 1
			0000 0 0 4 &mpic 11 1
			>;

		pcie@0 {
			reg = <0 0 0 0 0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x02000000 0 0xa0000000
				  0x02000000 0 0xa0000000
				  0 0x20000000

				  0x01000000 0 0x00000000
				  0x01000000 0 0x00000000
				  0 0x00100000>;
		};
	};
};
Commit	Line	Data
2f3804ed KG	1	/*
	2	* MPC8536 DS Device Tree Source
	3	*
	4	* Copyright 2008 Freescale Semiconductor, Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*/
	11
	12	/dts-v1/;
	13
	14	/ {
	15	model = "fsl,mpc8536ds";
	16	compatible = "fsl,mpc8536ds";
	17	#address-cells = <1>;
	18	#size-cells = <1>;
	19
	20	aliases {
	21	ethernet0 = &enet0;
	22	ethernet1 = &enet1;
	23	serial0 = &serial0;
	24	serial1 = &serial1;
	25	pci0 = &pci0;
	26	pci1 = &pci1;
	27	pci2 = &pci2;
	28	pci3 = &pci3;
	29	};
	30
	31	cpus {
	32	#cpus = <1>;
	33	#address-cells = <1>;
	34	#size-cells = <0>;
	35
	36	PowerPC,8536@0 {
	37	device_type = "cpu";
	38	reg = <0>;
	39	next-level-cache = <&L2>;
	40	};
	41	};
	42
	43	memory {
	44	device_type = "memory";
	45	reg = <00000000 00000000>; // Filled by U-Boot
	46	};
	47
	48	soc@ffe00000 {
	49	#address-cells = <1>;
	50	#size-cells = <1>;
	51	device_type = "soc";
cf0d19fb	52	compatible = "simple-bus";
2f3804ed KG	53	ranges = <0x0 0xffe00000 0x100000>;
	54	reg = <0xffe00000 0x1000>;
	55	bus-frequency = <0>; // Filled out by uboot.
	56
	57	memory-controller@2000 {
	58	compatible = "fsl,mpc8536-memory-controller";
	59	reg = <0x2000 0x1000>;
	60	interrupt-parent = <&mpic>;
	61	interrupts = <18 0x2>;
	62	};
	63
	64	L2: l2-cache-controller@20000 {
	65	compatible = "fsl,mpc8536-l2-cache-controller";
	66	reg = <0x20000 0x1000>;
	67	interrupt-parent = <&mpic>;
	68	interrupts = <16 0x2>;
	69	};
	70
	71	i2c@3000 {
	72	#address-cells = <1>;
	73	#size-cells = <0>;
	74	cell-index = <0>;
	75	compatible = "fsl-i2c";
	76	reg = <0x3000 0x100>;
	77	interrupts = <43 0x2>;
	78	interrupt-parent = <&mpic>;
	79	dfsrr;
	80	};
	81
	82	i2c@3100 {
	83	#address-cells = <1>;
	84	#size-cells = <0>;
	85	cell-index = <1>;
	86	compatible = "fsl-i2c";
	87	reg = <0x3100 0x100>;
	88	interrupts = <43 0x2>;
	89	interrupt-parent = <&mpic>;
	90	dfsrr;
	91	rtc@68 {
	92	compatible = "dallas,ds3232";
	93	reg = <0x68>;
	94	};
	95	};
	96
	97	dma@21300 {
	98	#address-cells = <1>;
	99	#size-cells = <1>;
	100	compatible = "fsl,mpc8536-dma", "fsl,eloplus-dma";
	101	reg = <0x21300 4>;
	102	ranges = <0 0x21100 0x200>;
	103	cell-index = <0>;
	104	dma-channel@0 {
	105	compatible = "fsl,mpc8536-dma-channel",
	106	"fsl,eloplus-dma-channel";
	107	reg = <0x0 0x80>;
	108	cell-index = <0>;
	109	interrupt-parent = <&mpic>;
	110	interrupts = <14 0x2>;
	111	};
	112	dma-channel@80 {
	113	compatible = "fsl,mpc8536-dma-channel",
	114	"fsl,eloplus-dma-channel";
	115	reg = <0x80 0x80>;
	116	cell-index = <1>;
117	interrupt-parent = <&mpic>;
118	interrupts = <15 0x2>;
119	};
120	dma-channel@100 {
121	compatible = "fsl,mpc8536-dma-channel",
122	"fsl,eloplus-dma-channel";
123	reg = <0x100 0x80>;
124	cell-index = <2>;
125	interrupt-parent = <&mpic>;
126	interrupts = <16 0x2>;
127	};
128	dma-channel@180 {
129	compatible = "fsl,mpc8536-dma-channel",
130	"fsl,eloplus-dma-channel";
131	reg = <0x180 0x80>;
132	cell-index = <3>;
133	interrupt-parent = <&mpic>;
134	interrupts = <17 0x2>;
135	};
136	};
137
138	mdio@24520 {
139	#address-cells = <1>;
140	#size-cells = <0>;
141	compatible = "fsl,gianfar-mdio";
142	reg = <0x24520 0x20>;
143
144	phy0: ethernet-phy@0 {
145	interrupt-parent = <&mpic>;
146	interrupts = <10 0x1>;
147	reg = <0>;
148	device_type = "ethernet-phy";
149	};
150	phy1: ethernet-phy@1 {
151	interrupt-parent = <&mpic>;
152	interrupts = <10 0x1>;
153	reg = <1>;
154	device_type = "ethernet-phy";
155	};
156	};
157
158	usb@22000 {
159	compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
160	reg = <0x22000 0x1000>;
161	#address-cells = <1>;
162	#size-cells = <0>;
163	interrupt-parent = <&mpic>;
164	interrupts = <28 0x2>;
165	phy_type = "ulpi";
166	};
167
168	usb@23000 {
169	compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
170	reg = <0x23000 0x1000>;
171	#address-cells = <1>;
172	#size-cells = <0>;
173	interrupt-parent = <&mpic>;
174	interrupts = <46 0x2>;
175	phy_type = "ulpi";
176	};
177
178	enet0: ethernet@24000 {
179	cell-index = <0>;
180	device_type = "network";
181	model = "TSEC";
182	compatible = "gianfar";
183	reg = <0x24000 0x1000>;
184	local-mac-address = [ 00 00 00 00 00 00 ];
185	interrupts = <29 2 30 2 34 2>;
186	interrupt-parent = <&mpic>;
187	phy-handle = <&phy1>;
188	phy-connection-type = "rgmii-id";
189	};
190
191	enet1: ethernet@26000 {
192	cell-index = <1>;
193	device_type = "network";
194	model = "TSEC";
195	compatible = "gianfar";
196	reg = <0x26000 0x1000>;
197	local-mac-address = [ 00 00 00 00 00 00 ];
198	interrupts = <31 2 32 2 33 2>;
199	interrupt-parent = <&mpic>;
200	phy-handle = <&phy0>;
201	phy-connection-type = "rgmii-id";
202	};
203
204	usb@2b000 {
205	compatible = "fsl,mpc8536-usb2-dr", "fsl-usb2-dr";
206	reg = <0x2b000 0x1000>;
207	#address-cells = <1>;
208	#size-cells = <0>;
209	interrupt-parent = <&mpic>;
210	interrupts = <60 0x2>;
211	dr_mode = "peripheral";
212	phy_type = "ulpi";
213	};
214
215	serial0: serial@4500 {
216	cell-index = <0>;
217	device_type = "serial";
218	compatible = "ns16550";
219	reg = <0x4500 0x100>;
220	clock-frequency = <0>;
221	interrupts = <42 0x2>;
222	interrupt-parent = <&mpic>;
223	};
224
225	serial1: serial@4600 {
226	cell-index = <1>;
227	device_type = "serial";
228	compatible = "ns16550";
229	reg = <0x4600 0x100>;
230	clock-frequency = <0>;
231	interrupts = <42 0x2>;
232	interrupt-parent = <&mpic>;
233	};
234
3fd44736 KP	235	crypto@30000 {
	236	compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
	237	"fsl,sec2.1", "fsl,sec2.0";
	238	reg = <0x30000 0x10000>;
	239	interrupts = <45 2 58 2>;
	240	interrupt-parent = <&mpic>;
	241	fsl,num-channels = <4>;
	242	fsl,channel-fifo-len = <24>;
	243	fsl,exec-units-mask = <0x9fe>;
	244	fsl,descriptor-types-mask = <0x3ab0ebf>;
	245	};
	246
2f3804ed KG	247	sata@18000 {
	248	compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
	249	reg = <0x18000 0x1000>;
	250	cell-index = <1>;
	251	interrupts = <74 0x2>;
	252	interrupt-parent = <&mpic>;
	253	};
	254
	255	sata@19000 {
	256	compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
	257	reg = <0x19000 0x1000>;
	258	cell-index = <2>;
	259	interrupts = <41 0x2>;
	260	interrupt-parent = <&mpic>;
	261	};
	262
	263	global-utilities@e0000 { //global utilities block
	264	compatible = "fsl,mpc8548-guts";
	265	reg = <0xe0000 0x1000>;
	266	fsl,has-rstcr;
	267	};
	268
	269	mpic: pic@40000 {
	270	clock-frequency = <0>;
	271	interrupt-controller;
	272	#address-cells = <0>;
	273	#interrupt-cells = <2>;
	274	reg = <0x40000 0x40000>;
	275	compatible = "chrp,open-pic";
	276	device_type = "open-pic";
	277	big-endian;
	278	};
	279
	280	msi@41600 {
	281	compatible = "fsl,mpc8536-msi", "fsl,mpic-msi";
	282	reg = <0x41600 0x80>;
	283	msi-available-ranges = <0 0x100>;
	284	interrupts = <
	285	0xe0 0
	286	0xe1 0
	287	0xe2 0
	288	0xe3 0
	289	0xe4 0
	290	0xe5 0
	291	0xe6 0
	292	0xe7 0>;
	293	interrupt-parent = <&mpic>;
	294	};
	295	};
	296
	297	pci0: pci@ffe08000 {
	298	cell-index = <0>;
	299	compatible = "fsl,mpc8540-pci";
	300	device_type = "pci";
	301	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
	302	interrupt-map = <
	303
	304	/* IDSEL 0x11 J17 Slot 1 */
	305	0x8800 0 0 1 &mpic 1 1
	306	0x8800 0 0 2 &mpic 2 1
	307	0x8800 0 0 3 &mpic 3 1
	308	0x8800 0 0 4 &mpic 4 1>;
	309
	310	interrupt-parent = <&mpic>;
311	interrupts = <24 0x2>;
312	bus-range = <0 0xff>;
313	ranges = <0x02000000 0 0x80000000 0x80000000 0 0x10000000
314	0x01000000 0 0x00000000 0xffc00000 0 0x00010000>;
315	clock-frequency = <66666666>;
316	#interrupt-cells = <1>;
317	#size-cells = <2>;
318	#address-cells = <3>;
319	reg = <0xffe08000 0x1000>;
320	};
321
322	pci1: pcie@ffe09000 {
323	cell-index = <1>;
324	compatible = "fsl,mpc8548-pcie";
325	device_type = "pci";
326	#interrupt-cells = <1>;
327	#size-cells = <2>;
328	#address-cells = <3>;
329	reg = <0xffe09000 0x1000>;
330	bus-range = <0 0xff>;
331	ranges = <0x02000000 0 0x98000000 0x98000000 0 0x08000000
332	0x01000000 0 0x00000000 0xffc20000 0 0x00010000>;
333	clock-frequency = <33333333>;
334	interrupt-parent = <&mpic>;
335	interrupts = <25 0x2>;
336	interrupt-map-mask = <0xf800 0 0 7>;
337	interrupt-map = <
338	/* IDSEL 0x0 */
339	0000 0 0 1 &mpic 4 1
340	0000 0 0 2 &mpic 5 1
341	0000 0 0 3 &mpic 6 1
342	0000 0 0 4 &mpic 7 1
343	>;
344	pcie@0 {
345	reg = <0 0 0 0 0>;
346	#size-cells = <2>;
347	#address-cells = <3>;
348	device_type = "pci";
349	ranges = <0x02000000 0 0x98000000
350	0x02000000 0 0x98000000
351	0 0x08000000
352
353	0x01000000 0 0x00000000
354	0x01000000 0 0x00000000
355	0 0x00010000>;
356	};
357	};
358
359	pci2: pcie@ffe0a000 {
360	cell-index = <2>;
361	compatible = "fsl,mpc8548-pcie";
362	device_type = "pci";
363	#interrupt-cells = <1>;
364	#size-cells = <2>;
365	#address-cells = <3>;
366	reg = <0xffe0a000 0x1000>;
367	bus-range = <0 0xff>;
368	ranges = <0x02000000 0 0x90000000 0x90000000 0 0x08000000
369	0x01000000 0 0x00000000 0xffc10000 0 0x00010000>;
370	clock-frequency = <33333333>;
371	interrupt-parent = <&mpic>;
372	interrupts = <26 0x2>;
373	interrupt-map-mask = <0xf800 0 0 7>;
374	interrupt-map = <
375	/* IDSEL 0x0 */
376	0000 0 0 1 &mpic 0 1
377	0000 0 0 2 &mpic 1 1
378	0000 0 0 3 &mpic 2 1
379	0000 0 0 4 &mpic 3 1
380	>;
381	pcie@0 {
382	reg = <0 0 0 0 0>;
383	#size-cells = <2>;
384	#address-cells = <3>;
385	device_type = "pci";
386	ranges = <0x02000000 0 0x90000000
387	0x02000000 0 0x90000000
388	0 0x08000000
389
390	0x01000000 0 0x00000000
391	0x01000000 0 0x00000000
392	0 0x00010000>;
393	};
394	};
395
396	pci3: pcie@ffe0b000 {
397	cell-index = <3>;
398	compatible = "fsl,mpc8548-pcie";
399	device_type = "pci";
400	#interrupt-cells = <1>;
401	#size-cells = <2>;
402	#address-cells = <3>;
403	reg = <0xffe0b000 0x1000>;
404	bus-range = <0 0xff>;
405	ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000
406	0x01000000 0 0x00000000 0xffc30000 0 0x00010000>;
407	clock-frequency = <33333333>;
408	interrupt-parent = <&mpic>;
409	interrupts = <27 0x2>;
410	interrupt-map-mask = <0xf800 0 0 7>;
411	interrupt-map = <
412	/* IDSEL 0x0 */
413	0000 0 0 1 &mpic 8 1
414	0000 0 0 2 &mpic 9 1
415	0000 0 0 3 &mpic 10 1
416	0000 0 0 4 &mpic 11 1
417	>;
418
419	pcie@0 {
420	reg = <0 0 0 0 0>;
421	#size-cells = <2>;
422	#address-cells = <3>;
423	device_type = "pci";
424	ranges = <0x02000000 0 0xa0000000
425	0x02000000 0 0xa0000000
426	0 0x20000000
427
428	0x01000000 0 0x00000000
429	0x01000000 0 0x00000000
430	0 0x00100000>;
431	};
432	};
433	};