[deliverable/linux.git] / arch / powerpc / boot / dts / mpc8540ads.dts

/*
 * MPC8540 ADS Device Tree Source
 *
 * Copyright 2006, 2008 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/dts-v1/;

/ {
	model = "MPC8540ADS";
	compatible = "MPC8540ADS", "MPC85xxADS";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		ethernet2 = &enet2;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8540@0 {
			device_type = "cpu";
			reg = <0x0>;
			d-cache-line-size = <32>;	// 32 bytes
			i-cache-line-size = <32>;	// 32 bytes
			d-cache-size = <0x8000>;		// L1, 32K
			i-cache-size = <0x8000>;		// L1, 32K
			timebase-frequency = <0>;	//  33 MHz, from uboot
			bus-frequency = <0>;	// 166 MHz
			clock-frequency = <0>;	// 825 MHz, from uboot
			next-level-cache = <&L2>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x8000000>;	// 128M at 0x0
	};

	soc8540@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		compatible = "simple-bus";
		ranges = <0x0 0xe0000000 0x100000>;
		bus-frequency = <0>;

		ecm-law@0 {
			compatible = "fsl,ecm-law";
			reg = <0x0 0x1000>;
			fsl,num-laws = <8>;
		};

		ecm@1000 {
			compatible = "fsl,mpc8540-ecm", "fsl,ecm";
			reg = <0x1000 0x1000>;
			interrupts = <17 2>;
			interrupt-parent = <&mpic>;
		};

		memory-controller@2000 {
			compatible = "fsl,8540-memory-controller";
			reg = <0x2000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <18 2>;
		};

		L2: l2-cache-controller@20000 {
			compatible = "fsl,8540-l2-cache-controller";
			reg = <0x20000 0x1000>;
			cache-line-size = <32>;	// 32 bytes
			cache-size = <0x40000>;	// L2, 256K
			interrupt-parent = <&mpic>;
			interrupts = <16 2>;
		};

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		dma@21300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
			reg = <0x21300 0x4>;
			ranges = <0x0 0x21100 0x200>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,mpc8540-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x0 0x80>;
				cell-index = <0>;
				interrupt-parent = <&mpic>;
				interrupts = <20 2>;
			};
			dma-channel@80 {
				compatible = "fsl,mpc8540-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupt-parent = <&mpic>;
				interrupts = <21 2>;
			};
			dma-channel@100 {
				compatible = "fsl,mpc8540-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupt-parent = <&mpic>;
				interrupts = <22 2>;
			};
			dma-channel@180 {
				compatible = "fsl,mpc8540-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x180 0x80>;
				cell-index = <3>;
				interrupt-parent = <&mpic>;
				interrupts = <23 2>;
			};
		};

		enet0: ethernet@24000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <0>;
			device_type = "network";
			model = "TSEC";
			compatible = "gianfar";
			reg = <0x24000 0x1000>;
			ranges = <0x0 0x24000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <29 2 30 2 34 2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi0>;
			phy-handle = <&phy0>;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-mdio";
				reg = <0x520 0x20>;

				phy0: ethernet-phy@0 {
					interrupt-parent = <&mpic>;
					interrupts = <5 1>;
					reg = <0x0>;
					device_type = "ethernet-phy";
				};
				phy1: ethernet-phy@1 {
					interrupt-parent = <&mpic>;
					interrupts = <5 1>;
					reg = <0x1>;
					device_type = "ethernet-phy";
				};
				phy3: ethernet-phy@3 {
					interrupt-parent = <&mpic>;
					interrupts = <7 1>;
					reg = <0x3>;
					device_type = "ethernet-phy";
				};
				tbi0: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		enet1: ethernet@25000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <1>;
			device_type = "network";
			model = "TSEC";
			compatible = "gianfar";
			reg = <0x25000 0x1000>;
			ranges = <0x0 0x25000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <35 2 36 2 40 2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi1>;
			phy-handle = <&phy1>;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-tbi";
				reg = <0x520 0x20>;

				tbi1: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		enet2: ethernet@26000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <2>;
			device_type = "network";
			model = "FEC";
			compatible = "gianfar";
			reg = <0x26000 0x1000>;
			ranges = <0x0 0x26000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <41 2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi2>;
			phy-handle = <&phy3>;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-tbi";
				reg = <0x520 0x20>;

				tbi2: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4500 0x100>; 	// reg base, size
			clock-frequency = <0>; 	// should we fill in in uboot?
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4600 0x100>;	// reg base, size
			clock-frequency = <0>; 	// should we fill in in uboot?
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};
		mpic: pic@40000 {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x40000 0x40000>;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
		};
	};

	pci0: pci@e0008000 {
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <

			/* IDSEL 0x02 */
			0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
			0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
			0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
			0x1000 0x0 0x0 0x4 &mpic 0x4 0x1

			/* IDSEL 0x03 */
			0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
			0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
			0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
			0x1800 0x0 0x0 0x4 &mpic 0x3 0x1

			/* IDSEL 0x04 */
			0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
			0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
			0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
			0x2000 0x0 0x0 0x4 &mpic 0x2 0x1

			/* IDSEL 0x05 */
			0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
			0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
			0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
			0x2800 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x0c */
			0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
			0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
			0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
			0x6000 0x0 0x0 0x4 &mpic 0x4 0x1

			/* IDSEL 0x0d */
			0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
			0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
			0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
			0x6800 0x0 0x0 0x4 &mpic 0x3 0x1

			/* IDSEL 0x0e */
			0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
			0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
			0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
			0x7000 0x0 0x0 0x4 &mpic 0x2 0x1

			/* IDSEL 0x0f */
			0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
			0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
			0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
			0x7800 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x12 */
			0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
			0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
			0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
			0x9000 0x0 0x0 0x4 &mpic 0x4 0x1

			/* IDSEL 0x13 */
			0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
			0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
			0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
			0x9800 0x0 0x0 0x4 &mpic 0x3 0x1

			/* IDSEL 0x14 */
			0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
			0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
			0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
			0xa000 0x0 0x0 0x4 &mpic 0x2 0x1

			/* IDSEL 0x15 */
			0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
			0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
			0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
			0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;
		interrupt-parent = <&mpic>;
		interrupts = <24 2>;
		bus-range = <0 0>;
		ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
			  0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
		clock-frequency = <66666666>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0008000 0x1000>;
		compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
		device_type = "pci";
	};
};
Commit	Line	Data
2654d638 AF	1	/*
	2	* MPC8540 ADS Device Tree Source
	3	*
32f960e9	4	* Copyright 2006, 2008 Freescale Semiconductor Inc.
2654d638 AF	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*/
	11
32f960e9	12	/dts-v1/;
2654d638 AF	13
	14	/ {
	15	model = "MPC8540ADS";
52094879	16	compatible = "MPC8540ADS", "MPC85xxADS";
2654d638 AF	17	#address-cells = <1>;
2654d638 AF	18	#size-cells = <1>;
2654d638	19
ea082fa9 KG	20	aliases {
	21	ethernet0 = &enet0;
	22	ethernet1 = &enet1;
	23	ethernet2 = &enet2;
	24	serial0 = &serial0;
	25	serial1 = &serial1;
	26	pci0 = &pci0;
	27	};
	28
2654d638	29	cpus {
2654d638 AF	30	#address-cells = <1>;
2654d638 AF	31	#size-cells = <0>;
2654d638 AF	32
	33	PowerPC,8540@0 {
	34	device_type = "cpu";
32f960e9 KG	35	reg = <0x0>;
	36	d-cache-line-size = <32>; // 32 bytes
	37	i-cache-line-size = <32>; // 32 bytes
	38	d-cache-size = <0x8000>; // L1, 32K
	39	i-cache-size = <0x8000>; // L1, 32K
2654d638 AF	40	timebase-frequency = <0>; // 33 MHz, from uboot
	41	bus-frequency = <0>; // 166 MHz
	42	clock-frequency = <0>; // 825 MHz, from uboot
c054065b	43	next-level-cache = <&L2>;
2654d638 AF	44	};
	45	};
	46
	47	memory {
	48	device_type = "memory";
32f960e9	49	reg = <0x0 0x8000000>; // 128M at 0x0
2654d638 AF	50	};
	51
	52	soc8540@e0000000 {
	53	#address-cells = <1>;
	54	#size-cells = <1>;
2654d638	55	device_type = "soc";
cf0d19fb	56	compatible = "simple-bus";
32f960e9	57	ranges = <0x0 0xe0000000 0x100000>;
2654d638 AF	58	bus-frequency = <0>;
2654d638 AF	59
e1a22897 KG	60	ecm-law@0 {
	61	compatible = "fsl,ecm-law";
	62	reg = <0x0 0x1000>;
	63	fsl,num-laws = <8>;
	64	};
	65
	66	ecm@1000 {
	67	compatible = "fsl,mpc8540-ecm", "fsl,ecm";
	68	reg = <0x1000 0x1000>;
	69	interrupts = <17 2>;
	70	interrupt-parent = <&mpic>;
	71	};
	72
50cf6707 DJ	73	memory-controller@2000 {
50cf6707 DJ	74	compatible = "fsl,8540-memory-controller";
32f960e9	75	reg = <0x2000 0x1000>;
50cf6707	76	interrupt-parent = <&mpic>;
32f960e9	77	interrupts = <18 2>;
50cf6707 DJ	78	};
50cf6707 DJ	79
c054065b	80	L2: l2-cache-controller@20000 {
50cf6707	81	compatible = "fsl,8540-l2-cache-controller";
32f960e9 KG	82	reg = <0x20000 0x1000>;
	83	cache-line-size = <32>; // 32 bytes
	84	cache-size = <0x40000>; // L2, 256K
50cf6707	85	interrupt-parent = <&mpic>;
32f960e9	86	interrupts = <16 2>;
50cf6707 DJ	87	};
50cf6707 DJ	88
2654d638	89	i2c@3000 {
ec9686c4 KG	90	#address-cells = <1>;
	91	#size-cells = <0>;
	92	cell-index = <0>;
2654d638	93	compatible = "fsl-i2c";
32f960e9 KG	94	reg = <0x3000 0x100>;
32f960e9 KG	95	interrupts = <43 2>;
52094879	96	interrupt-parent = <&mpic>;
2654d638 AF	97	dfsrr;
	98	};
	99
dee80553 KG	100	dma@21300 {
	101	#address-cells = <1>;
	102	#size-cells = <1>;
	103	compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
	104	reg = <0x21300 0x4>;
	105	ranges = <0x0 0x21100 0x200>;
	106	cell-index = <0>;
	107	dma-channel@0 {
	108	compatible = "fsl,mpc8540-dma-channel",
	109	"fsl,eloplus-dma-channel";
	110	reg = <0x0 0x80>;
	111	cell-index = <0>;
	112	interrupt-parent = <&mpic>;
	113	interrupts = <20 2>;
	114	};
	115	dma-channel@80 {
	116	compatible = "fsl,mpc8540-dma-channel",
	117	"fsl,eloplus-dma-channel";
	118	reg = <0x80 0x80>;
	119	cell-index = <1>;
	120	interrupt-parent = <&mpic>;
	121	interrupts = <21 2>;
	122	};
	123	dma-channel@100 {
	124	compatible = "fsl,mpc8540-dma-channel",
	125	"fsl,eloplus-dma-channel";
	126	reg = <0x100 0x80>;
	127	cell-index = <2>;
	128	interrupt-parent = <&mpic>;
	129	interrupts = <22 2>;
	130	};
	131	dma-channel@180 {
	132	compatible = "fsl,mpc8540-dma-channel",
	133	"fsl,eloplus-dma-channel";
	134	reg = <0x180 0x80>;
	135	cell-index = <3>;
	136	interrupt-parent = <&mpic>;
	137	interrupts = <23 2>;
	138	};
	139	};
	140
e77b28eb	141	enet0: ethernet@24000 {
84ba4a58 AV	142	#address-cells = <1>;
84ba4a58 AV	143	#size-cells = <1>;
e77b28eb	144	cell-index = <0>;
2654d638 AF	145	device_type = "network";
	146	model = "TSEC";
	147	compatible = "gianfar";
32f960e9	148	reg = <0x24000 0x1000>;
84ba4a58	149	ranges = <0x0 0x24000 0x1000>;
eae98266	150	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	151	interrupts = <29 2 30 2 34 2>;
52094879	152	interrupt-parent = <&mpic>;
b31a1d8b	153	tbi-handle = <&tbi0>;
52094879	154	phy-handle = <&phy0>;
84ba4a58 AV	155
	156	mdio@520 {
	157	#address-cells = <1>;
	158	#size-cells = <0>;
	159	compatible = "fsl,gianfar-mdio";
	160	reg = <0x520 0x20>;
	161
	162	phy0: ethernet-phy@0 {
	163	interrupt-parent = <&mpic>;
	164	interrupts = <5 1>;
	165	reg = <0x0>;
	166	device_type = "ethernet-phy";
	167	};
	168	phy1: ethernet-phy@1 {
	169	interrupt-parent = <&mpic>;
	170	interrupts = <5 1>;
	171	reg = <0x1>;
	172	device_type = "ethernet-phy";
	173	};
	174	phy3: ethernet-phy@3 {
	175	interrupt-parent = <&mpic>;
	176	interrupts = <7 1>;
	177	reg = <0x3>;
	178	device_type = "ethernet-phy";
	179	};
	180	tbi0: tbi-phy@11 {
	181	reg = <0x11>;
	182	device_type = "tbi-phy";
	183	};
	184	};
2654d638 AF	185	};
2654d638 AF	186
e77b28eb	187	enet1: ethernet@25000 {
84ba4a58 AV	188	#address-cells = <1>;
84ba4a58 AV	189	#size-cells = <1>;
e77b28eb	190	cell-index = <1>;
2654d638 AF	191	device_type = "network";
	192	model = "TSEC";
	193	compatible = "gianfar";
32f960e9	194	reg = <0x25000 0x1000>;
84ba4a58	195	ranges = <0x0 0x25000 0x1000>;
eae98266	196	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	197	interrupts = <35 2 36 2 40 2>;
52094879	198	interrupt-parent = <&mpic>;
b31a1d8b	199	tbi-handle = <&tbi1>;
52094879	200	phy-handle = <&phy1>;
84ba4a58 AV	201
	202	mdio@520 {
	203	#address-cells = <1>;
	204	#size-cells = <0>;
	205	compatible = "fsl,gianfar-tbi";
	206	reg = <0x520 0x20>;
	207
	208	tbi1: tbi-phy@11 {
	209	reg = <0x11>;
	210	device_type = "tbi-phy";
	211	};
	212	};
2654d638 AF	213	};
2654d638 AF	214
e77b28eb	215	enet2: ethernet@26000 {
84ba4a58 AV	216	#address-cells = <1>;
84ba4a58 AV	217	#size-cells = <1>;
e77b28eb	218	cell-index = <2>;
2654d638	219	device_type = "network";
aa74a30b	220	model = "FEC";
2654d638	221	compatible = "gianfar";
32f960e9	222	reg = <0x26000 0x1000>;
84ba4a58	223	ranges = <0x0 0x26000 0x1000>;
eae98266	224	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	225	interrupts = <41 2>;
52094879	226	interrupt-parent = <&mpic>;
b31a1d8b	227	tbi-handle = <&tbi2>;
52094879	228	phy-handle = <&phy3>;
84ba4a58 AV	229
	230	mdio@520 {
	231	#address-cells = <1>;
	232	#size-cells = <0>;
	233	compatible = "fsl,gianfar-tbi";
	234	reg = <0x520 0x20>;
	235
	236	tbi2: tbi-phy@11 {
	237	reg = <0x11>;
	238	device_type = "tbi-phy";
	239	};
	240	};
2654d638 AF	241	};
2654d638 AF	242
ea082fa9 KG	243	serial0: serial@4500 {
ea082fa9 KG	244	cell-index = <0>;
2654d638 AF	245	device_type = "serial";
2654d638 AF	246	compatible = "ns16550";
32f960e9	247	reg = <0x4500 0x100>; // reg base, size
2654d638	248	clock-frequency = <0>; // should we fill in in uboot?
32f960e9	249	interrupts = <42 2>;
52094879	250	interrupt-parent = <&mpic>;
2654d638 AF	251	};
2654d638 AF	252
ea082fa9 KG	253	serial1: serial@4600 {
ea082fa9 KG	254	cell-index = <1>;
2654d638 AF	255	device_type = "serial";
2654d638 AF	256	compatible = "ns16550";
32f960e9	257	reg = <0x4600 0x100>; // reg base, size
2654d638	258	clock-frequency = <0>; // should we fill in in uboot?
32f960e9	259	interrupts = <42 2>;
52094879	260	interrupt-parent = <&mpic>;
2654d638	261	};
1b3c5cda	262	mpic: pic@40000 {
1b3c5cda KG	263	interrupt-controller;
	264	#address-cells = <0>;
	265	#interrupt-cells = <2>;
32f960e9	266	reg = <0x40000 0x40000>;
1b3c5cda KG	267	compatible = "chrp,open-pic";
1b3c5cda KG	268	device_type = "open-pic";
1b3c5cda KG	269	};
1b3c5cda KG	270	};
2654d638	271
ea082fa9	272	pci0: pci@e0008000 {
32f960e9	273	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
1b3c5cda	274	interrupt-map = <
2654d638	275
1b3c5cda	276	/* IDSEL 0x02 */
32f960e9 KG	277	0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
	278	0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
	279	0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
	280	0x1000 0x0 0x0 0x4 &mpic 0x4 0x1
2654d638	281
1b3c5cda	282	/* IDSEL 0x03 */
32f960e9 KG	283	0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
	284	0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
	285	0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
	286	0x1800 0x0 0x0 0x4 &mpic 0x3 0x1
2654d638	287
1b3c5cda	288	/* IDSEL 0x04 */
32f960e9 KG	289	0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
	290	0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
	291	0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
	292	0x2000 0x0 0x0 0x4 &mpic 0x2 0x1
2654d638	293
1b3c5cda	294	/* IDSEL 0x05 */
32f960e9 KG	295	0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
	296	0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
	297	0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
	298	0x2800 0x0 0x0 0x4 &mpic 0x1 0x1
2654d638	299
1b3c5cda	300	/* IDSEL 0x0c */
32f960e9 KG	301	0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
	302	0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
	303	0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
	304	0x6000 0x0 0x0 0x4 &mpic 0x4 0x1
2654d638	305
1b3c5cda	306	/* IDSEL 0x0d */
32f960e9 KG	307	0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
	308	0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
	309	0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
	310	0x6800 0x0 0x0 0x4 &mpic 0x3 0x1
2654d638	311
1b3c5cda	312	/* IDSEL 0x0e */
32f960e9 KG	313	0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
	314	0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
	315	0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
	316	0x7000 0x0 0x0 0x4 &mpic 0x2 0x1
2654d638	317
1b3c5cda	318	/* IDSEL 0x0f */
32f960e9 KG	319	0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
	320	0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
	321	0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
	322	0x7800 0x0 0x0 0x4 &mpic 0x1 0x1
2654d638	323
1b3c5cda	324	/* IDSEL 0x12 */
32f960e9 KG	325	0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
	326	0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
	327	0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
	328	0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
2654d638	329
1b3c5cda	330	/* IDSEL 0x13 */
32f960e9 KG	331	0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
	332	0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
	333	0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
	334	0x9800 0x0 0x0 0x4 &mpic 0x3 0x1
2654d638	335
1b3c5cda	336	/* IDSEL 0x14 */
32f960e9 KG	337	0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
	338	0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
	339	0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
	340	0xa000 0x0 0x0 0x4 &mpic 0x2 0x1
2654d638	341
1b3c5cda	342	/* IDSEL 0x15 */
32f960e9 KG	343	0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
	344	0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
	345	0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
	346	0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;
1b3c5cda	347	interrupt-parent = <&mpic>;
32f960e9	348	interrupts = <24 2>;
1b3c5cda	349	bus-range = <0 0>;
32f960e9 KG	350	ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
	351	0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
	352	clock-frequency = <66666666>;
1b3c5cda KG	353	#interrupt-cells = <1>;
	354	#size-cells = <2>;
	355	#address-cells = <3>;
32f960e9	356	reg = <0xe0008000 0x1000>;
1b3c5cda KG	357	compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
1b3c5cda KG	358	device_type = "pci";
2654d638 AF	359	};
2654d638 AF	360	};