projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 2654d638 AF |
1 | /* |
| 2 | * MPC8541 CDS Device Tree Source | |
| 3 | * | |
| 4 | * Copyright 2006 Freescale Semiconductor Inc. | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or modify it | |
| 7 | * under the terms of the GNU General Public License as published by the | |
| 8 | * Free Software Foundation; either version 2 of the License, or (at your | |
| 9 | * option) any later version. | |
| 10 | */ | |
| 11 | ||
| 12 | ||
| 13 | / { | |
| 14 | model = "MPC8541CDS"; | |
| 52094879 | 15 | compatible = "MPC8541CDS", "MPC85xxCDS"; |
| 2654d638 AF |
16 | #address-cells = <1>; |
| 17 | #size-cells = <1>; | |
| 2654d638 AF |
18 | |
| 19 | cpus { | |
| 2654d638 AF |
20 | #address-cells = <1>; |
| 21 | #size-cells = <0>; | |
| 2654d638 AF |
22 | |
| 23 | PowerPC,8541@0 { | |
| 24 | device_type = "cpu"; | |
| 25 | reg = <0>; | |
| 26 | d-cache-line-size = <20>; // 32 bytes | |
| 27 | i-cache-line-size = <20>; // 32 bytes | |
| 28 | d-cache-size = <8000>; // L1, 32K | |
| 29 | i-cache-size = <8000>; // L1, 32K | |
| 30 | timebase-frequency = <0>; // 33 MHz, from uboot | |
| 31 | bus-frequency = <0>; // 166 MHz | |
| 32 | clock-frequency = <0>; // 825 MHz, from uboot | |
| 33 | 32-bit; | |
| 2654d638 AF |
34 | }; |
| 35 | }; | |
| 36 | ||
| 37 | memory { | |
| 38 | device_type = "memory"; | |
| 2654d638 AF |
39 | reg = <00000000 08000000>; // 128M at 0x0 |
| 40 | }; | |
| 41 | ||
| 42 | soc8541@e0000000 { | |
| 43 | #address-cells = <1>; | |
| 44 | #size-cells = <1>; | |
| 45 | #interrupt-cells = <2>; | |
| 46 | device_type = "soc"; | |
| 47 | ranges = <0 e0000000 00100000>; | |
| 48 | reg = <e0000000 00100000>; // CCSRBAR 1M | |
| 49 | bus-frequency = <0>; | |
| 50 | ||
| 51 | i2c@3000 { | |
| 52 | device_type = "i2c"; | |
| 53 | compatible = "fsl-i2c"; | |
| 54 | reg = <3000 100>; | |
| 55 | interrupts = <1b 2>; | |
| 52094879 | 56 | interrupt-parent = <&mpic>; |
| 2654d638 AF |
57 | dfsrr; |
| 58 | }; | |
| 59 | ||
| 60 | mdio@24520 { | |
| 61 | #address-cells = <1>; | |
| 62 | #size-cells = <0>; | |
| 63 | device_type = "mdio"; | |
| 64 | compatible = "gianfar"; | |
| 65 | reg = <24520 20>; | |
| 52094879 KG |
66 | phy0: ethernet-phy@0 { |
| 67 | interrupt-parent = <&mpic>; | |
| 2654d638 AF |
68 | interrupts = <35 0>; |
| 69 | reg = <0>; | |
| 70 | device_type = "ethernet-phy"; | |
| 71 | }; | |
| 52094879 KG |
72 | phy1: ethernet-phy@1 { |
| 73 | interrupt-parent = <&mpic>; | |
| 2654d638 AF |
74 | interrupts = <35 0>; |
| 75 | reg = <1>; | |
| 76 | device_type = "ethernet-phy"; | |
| 77 | }; | |
| 78 | }; | |
| 79 | ||
| 80 | ethernet@24000 { | |
| 81 | #address-cells = <1>; | |
| 82 | #size-cells = <0>; | |
| 83 | device_type = "network"; | |
| 84 | model = "TSEC"; | |
| 85 | compatible = "gianfar"; | |
| 86 | reg = <24000 1000>; | |
| 87 | local-mac-address = [ 00 E0 0C 00 73 00 ]; | |
| 88 | interrupts = <d 2 e 2 12 2>; | |
| 52094879 KG |
89 | interrupt-parent = <&mpic>; |
| 90 | phy-handle = <&phy0>; | |
| 2654d638 AF |
91 | }; |
| 92 | ||
| 93 | ethernet@25000 { | |
| 94 | #address-cells = <1>; | |
| 95 | #size-cells = <0>; | |
| 96 | device_type = "network"; | |
| 97 | model = "TSEC"; | |
| 98 | compatible = "gianfar"; | |
| 99 | reg = <25000 1000>; | |
| 100 | local-mac-address = [ 00 E0 0C 00 73 01 ]; | |
| 101 | interrupts = <13 2 14 2 18 2>; | |
| 52094879 KG |
102 | interrupt-parent = <&mpic>; |
| 103 | phy-handle = <&phy1>; | |
| 2654d638 AF |
104 | }; |
| 105 | ||
| 106 | serial@4500 { | |
| 107 | device_type = "serial"; | |
| 108 | compatible = "ns16550"; | |
| 109 | reg = <4500 100>; // reg base, size | |
| 110 | clock-frequency = <0>; // should we fill in in uboot? | |
| 111 | interrupts = <1a 2>; | |
| 52094879 | 112 | interrupt-parent = <&mpic>; |
| 2654d638 AF |
113 | }; |
| 114 | ||
| 115 | serial@4600 { | |
| 116 | device_type = "serial"; | |
| 117 | compatible = "ns16550"; | |
| 118 | reg = <4600 100>; // reg base, size | |
| 119 | clock-frequency = <0>; // should we fill in in uboot? | |
| 120 | interrupts = <1a 2>; | |
| 52094879 | 121 | interrupt-parent = <&mpic>; |
| 2654d638 AF |
122 | }; |
| 123 | ||
| 52094879 | 124 | pci1: pci@8000 { |
| 2654d638 AF |
125 | interrupt-map-mask = <1f800 0 0 7>; |
| 126 | interrupt-map = < | |
| 127 | ||
| 128 | /* IDSEL 0x10 */ | |
| 52094879 KG |
129 | 08000 0 0 1 &mpic 30 1 |
| 130 | 08000 0 0 2 &mpic 31 1 | |
| 131 | 08000 0 0 3 &mpic 32 1 | |
| 132 | 08000 0 0 4 &mpic 33 1 | |
| 2654d638 AF |
133 | |
| 134 | /* IDSEL 0x11 */ | |
| 52094879 KG |
135 | 08800 0 0 1 &mpic 30 1 |
| 136 | 08800 0 0 2 &mpic 31 1 | |
| 137 | 08800 0 0 3 &mpic 32 1 | |
| 138 | 08800 0 0 4 &mpic 33 1 | |
| 2654d638 AF |
139 | |
| 140 | /* IDSEL 0x12 (Slot 1) */ | |
| 52094879 KG |
141 | 09000 0 0 1 &mpic 30 1 |
| 142 | 09000 0 0 2 &mpic 31 1 | |
| 143 | 09000 0 0 3 &mpic 32 1 | |
| 144 | 09000 0 0 4 &mpic 33 1 | |
| 2654d638 AF |
145 | |
| 146 | /* IDSEL 0x13 (Slot 2) */ | |
| 52094879 KG |
147 | 09800 0 0 1 &mpic 31 1 |
| 148 | 09800 0 0 2 &mpic 32 1 | |
| 149 | 09800 0 0 3 &mpic 33 1 | |
| 150 | 09800 0 0 4 &mpic 30 1 | |
| 2654d638 AF |
151 | |
| 152 | /* IDSEL 0x14 (Slot 3) */ | |
| 52094879 KG |
153 | 0a000 0 0 1 &mpic 32 1 |
| 154 | 0a000 0 0 2 &mpic 33 1 | |
| 155 | 0a000 0 0 3 &mpic 30 1 | |
| 156 | 0a000 0 0 4 &mpic 31 1 | |
| 2654d638 AF |
157 | |
| 158 | /* IDSEL 0x15 (Slot 4) */ | |
| 52094879 KG |
159 | 0a800 0 0 1 &mpic 33 1 |
| 160 | 0a800 0 0 2 &mpic 30 1 | |
| 161 | 0a800 0 0 3 &mpic 31 1 | |
| 162 | 0a800 0 0 4 &mpic 32 1 | |
| 2654d638 AF |
163 | |
| 164 | /* Bus 1 (Tundra Bridge) */ | |
| 165 | /* IDSEL 0x12 (ISA bridge) */ | |
| 52094879 KG |
166 | 19000 0 0 1 &mpic 30 1 |
| 167 | 19000 0 0 2 &mpic 31 1 | |
| 168 | 19000 0 0 3 &mpic 32 1 | |
| 169 | 19000 0 0 4 &mpic 33 1>; | |
| 170 | interrupt-parent = <&mpic>; | |
| 2654d638 AF |
171 | interrupts = <08 2>; |
| 172 | bus-range = <0 0>; | |
| 173 | ranges = <02000000 0 80000000 80000000 0 20000000 | |
| 174 | 01000000 0 00000000 e2000000 0 00100000>; | |
| 175 | clock-frequency = <3f940aa>; | |
| 176 | #interrupt-cells = <1>; | |
| 177 | #size-cells = <2>; | |
| 178 | #address-cells = <3>; | |
| 179 | reg = <8000 1000>; | |
| 180 | compatible = "85xx"; | |
| 181 | device_type = "pci"; | |
| 182 | ||
| 183 | i8259@19000 { | |
| 184 | clock-frequency = <0>; | |
| 185 | interrupt-controller; | |
| 186 | device_type = "interrupt-controller"; | |
| 187 | reg = <19000 0 0 0 1>; | |
| 188 | #address-cells = <0>; | |
| 189 | #interrupt-cells = <2>; | |
| 190 | built-in; | |
| 191 | compatible = "chrp,iic"; | |
| 192 | big-endian; | |
| 193 | interrupts = <1>; | |
| 52094879 | 194 | interrupt-parent = <&pci1>; |
| 2654d638 AF |
195 | }; |
| 196 | }; | |
| 197 | ||
| 198 | pci@9000 { | |
| 2654d638 AF |
199 | interrupt-map-mask = <f800 0 0 7>; |
| 200 | interrupt-map = < | |
| 201 | ||
| 202 | /* IDSEL 0x15 */ | |
| 52094879 KG |
203 | a800 0 0 1 &mpic 3b 1 |
| 204 | a800 0 0 2 &mpic 3b 1 | |
| 205 | a800 0 0 3 &mpic 3b 1 | |
| 206 | a800 0 0 4 &mpic 3b 1>; | |
| 207 | interrupt-parent = <&mpic>; | |
| 2654d638 AF |
208 | interrupts = <09 2>; |
| 209 | bus-range = <0 0>; | |
| 210 | ranges = <02000000 0 a0000000 a0000000 0 20000000 | |
| 211 | 01000000 0 00000000 e3000000 0 00100000>; | |
| 212 | clock-frequency = <3f940aa>; | |
| 213 | #interrupt-cells = <1>; | |
| 214 | #size-cells = <2>; | |
| 215 | #address-cells = <3>; | |
| 216 | reg = <9000 1000>; | |
| 217 | compatible = "85xx"; | |
| 218 | device_type = "pci"; | |
| 219 | }; | |
| 220 | ||
| 52094879 | 221 | mpic: pic@40000 { |
| 2654d638 AF |
222 | clock-frequency = <0>; |
| 223 | interrupt-controller; | |
| 224 | #address-cells = <0>; | |
| 225 | #interrupt-cells = <2>; | |
| 226 | reg = <40000 40000>; | |
| 227 | built-in; | |
| 228 | compatible = "chrp,open-pic"; | |
| 229 | device_type = "open-pic"; | |
| 230 | big-endian; | |
| 231 | }; | |
| 232 | }; | |
| 233 | }; |