[deliverable/linux.git] / arch / powerpc / boot / dts / mpc8541cds.dts

/*
 * MPC8541 CDS Device Tree Source
 *
 * Copyright 2006, 2008 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/dts-v1/;

/ {
	model = "MPC8541CDS";
	compatible = "MPC8541CDS", "MPC85xxCDS";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
		pci1 = &pci1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8541@0 {
			device_type = "cpu";
			reg = <0x0>;
			d-cache-line-size = <32>;	// 32 bytes
			i-cache-line-size = <32>;	// 32 bytes
			d-cache-size = <0x8000>;		// L1, 32K
			i-cache-size = <0x8000>;		// L1, 32K
			timebase-frequency = <0>;	//  33 MHz, from uboot
			bus-frequency = <0>;	// 166 MHz
			clock-frequency = <0>;	// 825 MHz, from uboot
			next-level-cache = <&L2>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x8000000>;	// 128M at 0x0
	};

	soc8541@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		compatible = "simple-bus";
		ranges = <0x0 0xe0000000 0x100000>;
		reg = <0xe0000000 0x1000>;	// CCSRBAR 1M
		bus-frequency = <0>;

		memory-controller@2000 {
			compatible = "fsl,8541-memory-controller";
			reg = <0x2000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <18 2>;
		};

		L2: l2-cache-controller@20000 {
			compatible = "fsl,8541-l2-cache-controller";
			reg = <0x20000 0x1000>;
			cache-line-size = <32>;	// 32 bytes
			cache-size = <0x40000>;	// L2, 256K
			interrupt-parent = <&mpic>;
			interrupts = <16 2>;
		};

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		dma@21300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8541-dma", "fsl,eloplus-dma";
			reg = <0x21300 0x4>;
			ranges = <0x0 0x21100 0x200>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,mpc8541-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x0 0x80>;
				cell-index = <0>;
				interrupt-parent = <&mpic>;
				interrupts = <20 2>;
			};
			dma-channel@80 {
				compatible = "fsl,mpc8541-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupt-parent = <&mpic>;
				interrupts = <21 2>;
			};
			dma-channel@100 {
				compatible = "fsl,mpc8541-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupt-parent = <&mpic>;
				interrupts = <22 2>;
			};
			dma-channel@180 {
				compatible = "fsl,mpc8541-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x180 0x80>;
				cell-index = <3>;
				interrupt-parent = <&mpic>;
				interrupts = <23 2>;
			};
		};

		enet0: ethernet@24000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <0>;
			device_type = "network";
			model = "TSEC";
			compatible = "gianfar";
			reg = <0x24000 0x1000>;
			ranges = <0x0 0x24000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <29 2 30 2 34 2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi0>;
			phy-handle = <&phy0>;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-mdio";
				reg = <0x520 0x20>;

				phy0: ethernet-phy@0 {
					interrupt-parent = <&mpic>;
					interrupts = <5 1>;
					reg = <0x0>;
					device_type = "ethernet-phy";
				};
				phy1: ethernet-phy@1 {
					interrupt-parent = <&mpic>;
					interrupts = <5 1>;
					reg = <0x1>;
					device_type = "ethernet-phy";
				};
				tbi0: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		enet1: ethernet@25000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <1>;
			device_type = "network";
			model = "TSEC";
			compatible = "gianfar";
			reg = <0x25000 0x1000>;
			ranges = <0x0 0x25000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <35 2 36 2 40 2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi1>;
			phy-handle = <&phy1>;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-tbi";
				reg = <0x520 0x20>;

				tbi1: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4500 0x100>; 	// reg base, size
			clock-frequency = <0>; 	// should we fill in in uboot?
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4600 0x100>;	// reg base, size
			clock-frequency = <0>; 	// should we fill in in uboot?
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		crypto@30000 {
			compatible = "fsl,sec2.0";
			reg = <0x30000 0x10000>;
			interrupts = <45 2>;
			interrupt-parent = <&mpic>;
			fsl,num-channels = <4>;
			fsl,channel-fifo-len = <24>;
			fsl,exec-units-mask = <0x7e>;
			fsl,descriptor-types-mask = <0x01010ebf>;
		};

		mpic: pic@40000 {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x40000 0x40000>;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
		};

		cpm@919c0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8541-cpm", "fsl,cpm2";
			reg = <0x919c0 0x30>;
			ranges;

			muram@80000 {
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0x80000 0x10000>;

				data@0 {
					compatible = "fsl,cpm-muram-data";
					reg = <0x0 0x2000 0x9000 0x1000>;
				};
			};

			brg@919f0 {
				compatible = "fsl,mpc8541-brg",
				             "fsl,cpm2-brg",
				             "fsl,cpm-brg";
				reg = <0x919f0 0x10 0x915f0 0x10>;
			};

			cpmpic: pic@90c00 {
				interrupt-controller;
				#address-cells = <0>;
				#interrupt-cells = <2>;
				interrupts = <46 2>;
				interrupt-parent = <&mpic>;
				reg = <0x90c00 0x80>;
				compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic";
			};
		};
	};

	pci0: pci@e0008000 {
		interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
		interrupt-map = <

			/* IDSEL 0x10 */
			0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
			0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
			0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
			0x8000 0x0 0x0 0x4 &mpic 0x3 0x1

			/* IDSEL 0x11 */
			0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
			0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
			0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
			0x8800 0x0 0x0 0x4 &mpic 0x3 0x1

			/* IDSEL 0x12 (Slot 1) */
			0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
			0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
			0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
			0x9000 0x0 0x0 0x4 &mpic 0x3 0x1

			/* IDSEL 0x13 (Slot 2) */
			0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
			0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
			0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
			0x9800 0x0 0x0 0x4 &mpic 0x0 0x1

			/* IDSEL 0x14 (Slot 3) */
			0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
			0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
			0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
			0xa000 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x15 (Slot 4) */
			0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
			0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
			0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
			0xa800 0x0 0x0 0x4 &mpic 0x2 0x1

			/* Bus 1 (Tundra Bridge) */
			/* IDSEL 0x12 (ISA bridge) */
			0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
			0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
			0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
			0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
		interrupt-parent = <&mpic>;
		interrupts = <24 2>;
		bus-range = <0 0>;
		ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
			  0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
		clock-frequency = <66666666>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0008000 0x1000>;
		compatible = "fsl,mpc8540-pci";
		device_type = "pci";

		i8259@19000 {
			interrupt-controller;
			device_type = "interrupt-controller";
			reg = <0x19000 0x0 0x0 0x0 0x1>;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			compatible = "chrp,iic";
			interrupts = <1>;
			interrupt-parent = <&pci0>;
		};
	};

	pci1: pci@e0009000 {
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <

			/* IDSEL 0x15 */
			0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
			0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
			0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
			0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
		interrupt-parent = <&mpic>;
		interrupts = <25 2>;
		bus-range = <0 0>;
		ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
			  0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
		clock-frequency = <66666666>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0009000 0x1000>;
		compatible = "fsl,mpc8540-pci";
		device_type = "pci";
	};
};
Commit	Line	Data
2654d638 AF	1	/*
	2	* MPC8541 CDS Device Tree Source
	3	*
32f960e9	4	* Copyright 2006, 2008 Freescale Semiconductor Inc.
2654d638 AF	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*/
	11
32f960e9	12	/dts-v1/;
2654d638 AF	13
	14	/ {
	15	model = "MPC8541CDS";
52094879	16	compatible = "MPC8541CDS", "MPC85xxCDS";
2654d638 AF	17	#address-cells = <1>;
2654d638 AF	18	#size-cells = <1>;
2654d638	19
ea082fa9 KG	20	aliases {
	21	ethernet0 = &enet0;
	22	ethernet1 = &enet1;
	23	serial0 = &serial0;
	24	serial1 = &serial1;
	25	pci0 = &pci0;
	26	pci1 = &pci1;
	27	};
	28
2654d638	29	cpus {
2654d638 AF	30	#address-cells = <1>;
2654d638 AF	31	#size-cells = <0>;
2654d638 AF	32
	33	PowerPC,8541@0 {
	34	device_type = "cpu";
32f960e9 KG	35	reg = <0x0>;
	36	d-cache-line-size = <32>; // 32 bytes
	37	i-cache-line-size = <32>; // 32 bytes
	38	d-cache-size = <0x8000>; // L1, 32K
	39	i-cache-size = <0x8000>; // L1, 32K
2654d638 AF	40	timebase-frequency = <0>; // 33 MHz, from uboot
	41	bus-frequency = <0>; // 166 MHz
	42	clock-frequency = <0>; // 825 MHz, from uboot
c054065b	43	next-level-cache = <&L2>;
2654d638 AF	44	};
	45	};
	46
	47	memory {
	48	device_type = "memory";
32f960e9	49	reg = <0x0 0x8000000>; // 128M at 0x0
2654d638 AF	50	};
	51
	52	soc8541@e0000000 {
	53	#address-cells = <1>;
	54	#size-cells = <1>;
2654d638	55	device_type = "soc";
cf0d19fb	56	compatible = "simple-bus";
32f960e9 KG	57	ranges = <0x0 0xe0000000 0x100000>;
32f960e9 KG	58	reg = <0xe0000000 0x1000>; // CCSRBAR 1M
2654d638 AF	59	bus-frequency = <0>;
2654d638 AF	60
4da421d6 KG	61	memory-controller@2000 {
4da421d6 KG	62	compatible = "fsl,8541-memory-controller";
32f960e9	63	reg = <0x2000 0x1000>;
4da421d6	64	interrupt-parent = <&mpic>;
32f960e9	65	interrupts = <18 2>;
4da421d6 KG	66	};
4da421d6 KG	67
c054065b	68	L2: l2-cache-controller@20000 {
4da421d6	69	compatible = "fsl,8541-l2-cache-controller";
32f960e9 KG	70	reg = <0x20000 0x1000>;
	71	cache-line-size = <32>; // 32 bytes
	72	cache-size = <0x40000>; // L2, 256K
4da421d6	73	interrupt-parent = <&mpic>;
32f960e9	74	interrupts = <16 2>;
4da421d6 KG	75	};
4da421d6 KG	76
2654d638	77	i2c@3000 {
ec9686c4 KG	78	#address-cells = <1>;
	79	#size-cells = <0>;
	80	cell-index = <0>;
2654d638	81	compatible = "fsl-i2c";
32f960e9 KG	82	reg = <0x3000 0x100>;
32f960e9 KG	83	interrupts = <43 2>;
52094879	84	interrupt-parent = <&mpic>;
2654d638 AF	85	dfsrr;
	86	};
	87
dee80553 KG	88	dma@21300 {
	89	#address-cells = <1>;
	90	#size-cells = <1>;
	91	compatible = "fsl,mpc8541-dma", "fsl,eloplus-dma";
	92	reg = <0x21300 0x4>;
	93	ranges = <0x0 0x21100 0x200>;
	94	cell-index = <0>;
	95	dma-channel@0 {
	96	compatible = "fsl,mpc8541-dma-channel",
	97	"fsl,eloplus-dma-channel";
	98	reg = <0x0 0x80>;
	99	cell-index = <0>;
	100	interrupt-parent = <&mpic>;
	101	interrupts = <20 2>;
	102	};
	103	dma-channel@80 {
	104	compatible = "fsl,mpc8541-dma-channel",
	105	"fsl,eloplus-dma-channel";
	106	reg = <0x80 0x80>;
	107	cell-index = <1>;
	108	interrupt-parent = <&mpic>;
	109	interrupts = <21 2>;
	110	};
	111	dma-channel@100 {
	112	compatible = "fsl,mpc8541-dma-channel",
	113	"fsl,eloplus-dma-channel";
	114	reg = <0x100 0x80>;
	115	cell-index = <2>;
	116	interrupt-parent = <&mpic>;
	117	interrupts = <22 2>;
	118	};
	119	dma-channel@180 {
	120	compatible = "fsl,mpc8541-dma-channel",
	121	"fsl,eloplus-dma-channel";
	122	reg = <0x180 0x80>;
	123	cell-index = <3>;
	124	interrupt-parent = <&mpic>;
	125	interrupts = <23 2>;
	126	};
	127	};
	128
e77b28eb	129	enet0: ethernet@24000 {
84ba4a58 AV	130	#address-cells = <1>;
84ba4a58 AV	131	#size-cells = <1>;
e77b28eb	132	cell-index = <0>;
2654d638 AF	133	device_type = "network";
	134	model = "TSEC";
	135	compatible = "gianfar";
32f960e9	136	reg = <0x24000 0x1000>;
84ba4a58	137	ranges = <0x0 0x24000 0x1000>;
eae98266	138	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	139	interrupts = <29 2 30 2 34 2>;
52094879	140	interrupt-parent = <&mpic>;
b31a1d8b	141	tbi-handle = <&tbi0>;
52094879	142	phy-handle = <&phy0>;
84ba4a58 AV	143
	144	mdio@520 {
	145	#address-cells = <1>;
	146	#size-cells = <0>;
	147	compatible = "fsl,gianfar-mdio";
	148	reg = <0x520 0x20>;
	149
	150	phy0: ethernet-phy@0 {
	151	interrupt-parent = <&mpic>;
	152	interrupts = <5 1>;
	153	reg = <0x0>;
	154	device_type = "ethernet-phy";
	155	};
	156	phy1: ethernet-phy@1 {
	157	interrupt-parent = <&mpic>;
	158	interrupts = <5 1>;
	159	reg = <0x1>;
	160	device_type = "ethernet-phy";
	161	};
	162	tbi0: tbi-phy@11 {
	163	reg = <0x11>;
	164	device_type = "tbi-phy";
	165	};
	166	};
2654d638 AF	167	};
2654d638 AF	168
e77b28eb	169	enet1: ethernet@25000 {
84ba4a58 AV	170	#address-cells = <1>;
84ba4a58 AV	171	#size-cells = <1>;
e77b28eb	172	cell-index = <1>;
2654d638 AF	173	device_type = "network";
	174	model = "TSEC";
	175	compatible = "gianfar";
32f960e9	176	reg = <0x25000 0x1000>;
84ba4a58	177	ranges = <0x0 0x25000 0x1000>;
eae98266	178	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	179	interrupts = <35 2 36 2 40 2>;
52094879	180	interrupt-parent = <&mpic>;
b31a1d8b	181	tbi-handle = <&tbi1>;
52094879	182	phy-handle = <&phy1>;
84ba4a58 AV	183
	184	mdio@520 {
	185	#address-cells = <1>;
	186	#size-cells = <0>;
	187	compatible = "fsl,gianfar-tbi";
	188	reg = <0x520 0x20>;
	189
	190	tbi1: tbi-phy@11 {
	191	reg = <0x11>;
	192	device_type = "tbi-phy";
	193	};
	194	};
2654d638 AF	195	};
2654d638 AF	196
ea082fa9 KG	197	serial0: serial@4500 {
ea082fa9 KG	198	cell-index = <0>;
2654d638 AF	199	device_type = "serial";
2654d638 AF	200	compatible = "ns16550";
32f960e9	201	reg = <0x4500 0x100>; // reg base, size
2654d638	202	clock-frequency = <0>; // should we fill in in uboot?
32f960e9	203	interrupts = <42 2>;
52094879	204	interrupt-parent = <&mpic>;
2654d638 AF	205	};
2654d638 AF	206
ea082fa9 KG	207	serial1: serial@4600 {
ea082fa9 KG	208	cell-index = <1>;
2654d638 AF	209	device_type = "serial";
2654d638 AF	210	compatible = "ns16550";
32f960e9	211	reg = <0x4600 0x100>; // reg base, size
2654d638	212	clock-frequency = <0>; // should we fill in in uboot?
32f960e9	213	interrupts = <42 2>;
52094879	214	interrupt-parent = <&mpic>;
2654d638 AF	215	};
2654d638 AF	216
3fd44736 KP	217	crypto@30000 {
	218	compatible = "fsl,sec2.0";
	219	reg = <0x30000 0x10000>;
	220	interrupts = <45 2>;
	221	interrupt-parent = <&mpic>;
	222	fsl,num-channels = <4>;
	223	fsl,channel-fifo-len = <24>;
	224	fsl,exec-units-mask = <0x7e>;
	225	fsl,descriptor-types-mask = <0x01010ebf>;
	226	};
	227
52094879	228	mpic: pic@40000 {
2654d638 AF	229	interrupt-controller;
	230	#address-cells = <0>;
	231	#interrupt-cells = <2>;
32f960e9	232	reg = <0x40000 0x40000>;
2654d638 AF	233	compatible = "chrp,open-pic";
2654d638 AF	234	device_type = "open-pic";
2654d638	235	};
ab9683ca SW	236
	237	cpm@919c0 {
	238	#address-cells = <1>;
	239	#size-cells = <1>;
	240	compatible = "fsl,mpc8541-cpm", "fsl,cpm2";
32f960e9	241	reg = <0x919c0 0x30>;
ab9683ca SW	242	ranges;
	243
	244	muram@80000 {
	245	#address-cells = <1>;
	246	#size-cells = <1>;
32f960e9	247	ranges = <0x0 0x80000 0x10000>;
ab9683ca SW	248
	249	data@0 {
	250	compatible = "fsl,cpm-muram-data";
32f960e9	251	reg = <0x0 0x2000 0x9000 0x1000>;
ab9683ca SW	252	};
	253	};
	254
	255	brg@919f0 {
	256	compatible = "fsl,mpc8541-brg",
	257	"fsl,cpm2-brg",
	258	"fsl,cpm-brg";
32f960e9	259	reg = <0x919f0 0x10 0x915f0 0x10>;
ab9683ca SW	260	};
	261
	262	cpmpic: pic@90c00 {
	263	interrupt-controller;
	264	#address-cells = <0>;
	265	#interrupt-cells = <2>;
32f960e9	266	interrupts = <46 2>;
ab9683ca	267	interrupt-parent = <&mpic>;
32f960e9	268	reg = <0x90c00 0x80>;
ab9683ca SW	269	compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic";
	270	};
	271	};
2654d638	272	};
1b3c5cda	273
ea082fa9	274	pci0: pci@e0008000 {
32f960e9	275	interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
1b3c5cda KG	276	interrupt-map = <
	277
	278	/* IDSEL 0x10 */
32f960e9 KG	279	0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
	280	0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
	281	0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
	282	0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
1b3c5cda KG	283
1b3c5cda KG	284	/* IDSEL 0x11 */
32f960e9 KG	285	0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
	286	0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
	287	0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
	288	0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
1b3c5cda KG	289
1b3c5cda KG	290	/* IDSEL 0x12 (Slot 1) */
32f960e9 KG	291	0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
	292	0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
	293	0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
	294	0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
1b3c5cda KG	295
1b3c5cda KG	296	/* IDSEL 0x13 (Slot 2) */
32f960e9 KG	297	0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
	298	0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
	299	0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
	300	0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
1b3c5cda KG	301
1b3c5cda KG	302	/* IDSEL 0x14 (Slot 3) */
32f960e9 KG	303	0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
	304	0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
	305	0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
	306	0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
1b3c5cda KG	307
1b3c5cda KG	308	/* IDSEL 0x15 (Slot 4) */
32f960e9 KG	309	0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
	310	0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
	311	0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
	312	0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
1b3c5cda KG	313
	314	/* Bus 1 (Tundra Bridge) */
	315	/* IDSEL 0x12 (ISA bridge) */
32f960e9 KG	316	0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
	317	0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
	318	0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
	319	0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
1b3c5cda	320	interrupt-parent = <&mpic>;
32f960e9	321	interrupts = <24 2>;
1b3c5cda	322	bus-range = <0 0>;
32f960e9 KG	323	ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
	324	0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
	325	clock-frequency = <66666666>;
1b3c5cda KG	326	#interrupt-cells = <1>;
	327	#size-cells = <2>;
	328	#address-cells = <3>;
32f960e9	329	reg = <0xe0008000 0x1000>;
1b3c5cda KG	330	compatible = "fsl,mpc8540-pci";
	331	device_type = "pci";
	332
	333	i8259@19000 {
	334	interrupt-controller;
	335	device_type = "interrupt-controller";
32f960e9	336	reg = <0x19000 0x0 0x0 0x0 0x1>;
1b3c5cda KG	337	#address-cells = <0>;
	338	#interrupt-cells = <2>;
	339	compatible = "chrp,iic";
	340	interrupts = <1>;
ea082fa9	341	interrupt-parent = <&pci0>;
1b3c5cda KG	342	};
	343	};
	344
ea082fa9	345	pci1: pci@e0009000 {
32f960e9	346	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
1b3c5cda KG	347	interrupt-map = <
	348
	349	/* IDSEL 0x15 */
32f960e9 KG	350	0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
	351	0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
	352	0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
	353	0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
1b3c5cda	354	interrupt-parent = <&mpic>;
32f960e9	355	interrupts = <25 2>;
1b3c5cda	356	bus-range = <0 0>;
32f960e9 KG	357	ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
	358	0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
	359	clock-frequency = <66666666>;
1b3c5cda KG	360	#interrupt-cells = <1>;
	361	#size-cells = <2>;
	362	#address-cells = <3>;
32f960e9	363	reg = <0xe0009000 0x1000>;
1b3c5cda KG	364	compatible = "fsl,mpc8540-pci";
	365	device_type = "pci";
	366	};
2654d638	367	};