[deliverable/linux.git] / arch / powerpc / boot / dts / mpc8544ds.dts

/*
 * MPC8544 DS Device Tree Source
 *
 * Copyright 2007, 2008 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/dts-v1/;
/ {
	model = "MPC8544DS";
	compatible = "MPC8544DS", "MPC85xxDS";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
		pci1 = &pci1;
		pci2 = &pci2;
		pci3 = &pci3;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8544@0 {
			device_type = "cpu";
			reg = <0x0>;
			d-cache-line-size = <32>;	// 32 bytes
			i-cache-line-size = <32>;	// 32 bytes
			d-cache-size = <0x8000>;		// L1, 32K
			i-cache-size = <0x8000>;		// L1, 32K
			timebase-frequency = <0>;
			bus-frequency = <0>;
			clock-frequency = <0>;
			next-level-cache = <&L2>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x0>;	// Filled by U-Boot
	};

	soc8544@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		compatible = "simple-bus";

		ranges = <0x0 0xe0000000 0x100000>;
		reg = <0xe0000000 0x1000>;	// CCSRBAR 1M
		bus-frequency = <0>;		// Filled out by uboot.

		memory-controller@2000 {
			compatible = "fsl,8544-memory-controller";
			reg = <0x2000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <18 2>;
		};

		L2: l2-cache-controller@20000 {
			compatible = "fsl,8544-l2-cache-controller";
			reg = <0x20000 0x1000>;
			cache-line-size = <32>;	// 32 bytes
			cache-size = <0x40000>;	// L2, 256K
			interrupt-parent = <&mpic>;
			interrupts = <16 2>;
		};

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		mdio@24520 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,gianfar-mdio";
			reg = <0x24520 0x20>;

			phy0: ethernet-phy@0 {
				interrupt-parent = <&mpic>;
				interrupts = <10 1>;
				reg = <0x0>;
				device_type = "ethernet-phy";
			};
			phy1: ethernet-phy@1 {
				interrupt-parent = <&mpic>;
				interrupts = <10 1>;
				reg = <0x1>;
				device_type = "ethernet-phy";
			};
		};

		dma@21300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8544-dma", "fsl,eloplus-dma";
			reg = <0x21300 0x4>;
			ranges = <0x0 0x21100 0x200>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,mpc8544-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x0 0x80>;
				cell-index = <0>;
				interrupt-parent = <&mpic>;
				interrupts = <20 2>;
			};
			dma-channel@80 {
				compatible = "fsl,mpc8544-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupt-parent = <&mpic>;
				interrupts = <21 2>;
			};
			dma-channel@100 {
				compatible = "fsl,mpc8544-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupt-parent = <&mpic>;
				interrupts = <22 2>;
			};
			dma-channel@180 {
				compatible = "fsl,mpc8544-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x180 0x80>;
				cell-index = <3>;
				interrupt-parent = <&mpic>;
				interrupts = <23 2>;
			};
		};

		enet0: ethernet@24000 {
			cell-index = <0>;
			device_type = "network";
			model = "TSEC";
			compatible = "gianfar";
			reg = <0x24000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <29 2 30 2 34 2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy0>;
			phy-connection-type = "rgmii-id";
		};

		enet1: ethernet@26000 {
			cell-index = <1>;
			device_type = "network";
			model = "TSEC";
			compatible = "gianfar";
			reg = <0x26000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <31 2 32 2 33 2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy1>;
			phy-connection-type = "rgmii-id";
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4500 0x100>;
			clock-frequency = <0>;
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4600 0x100>;
			clock-frequency = <0>;
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		global-utilities@e0000 {	//global utilities block
			compatible = "fsl,mpc8548-guts";
			reg = <0xe0000 0x1000>;
			fsl,has-rstcr;
		};

		crypto@30000 {
			compatible = "fsl,sec2.1", "fsl,sec2.0";
			reg = <0x30000 0x10000>;
			interrupts = <45 2>;
			interrupt-parent = <&mpic>;
			fsl,num-channels = <4>;
			fsl,channel-fifo-len = <24>;
			fsl,exec-units-mask = <0xfe>;
			fsl,descriptor-types-mask = <0x12b0ebf>;
		};

		mpic: pic@40000 {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x40000 0x40000>;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
		};

		msi@41600 {
			compatible = "fsl,mpc8544-msi", "fsl,mpic-msi";
			reg = <0x41600 0x80>;
			msi-available-ranges = <0 0x100>;
			interrupts = <
				0xe0 0
				0xe1 0
				0xe2 0
				0xe3 0
				0xe4 0
				0xe5 0
				0xe6 0
				0xe7 0>;
			interrupt-parent = <&mpic>;
		};
	};

	pci0: pci@e0008000 {
		cell-index = <0>;
		compatible = "fsl,mpc8540-pci";
		device_type = "pci";
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <

			/* IDSEL 0x11 J17 Slot 1 */
			0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
			0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
			0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
			0x8800 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x12 J16 Slot 2 */

			0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
			0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
			0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
			0x9000 0x0 0x0 0x4 &mpic 0x1 0x1>;

		interrupt-parent = <&mpic>;
		interrupts = <24 2>;
		bus-range = <0 255>;
		ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
			  0x1000000 0x0 0x0 0xe1000000 0x0 0x10000>;
		clock-frequency = <66666666>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0008000 0x1000>;
	};

	pci1: pcie@e0009000 {
		cell-index = <1>;
		compatible = "fsl,mpc8548-pcie";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0009000 0x1000>;
		bus-range = <0 255>;
		ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
			  0x1000000 0x0 0x0 0xe1010000 0x0 0x10000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <26 2>;
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <
			/* IDSEL 0x0 */
			0000 0x0 0x0 0x1 &mpic 0x4 0x1
			0000 0x0 0x0 0x2 &mpic 0x5 0x1
			0000 0x0 0x0 0x3 &mpic 0x6 0x1
			0000 0x0 0x0 0x4 &mpic 0x7 0x1
			>;
		pcie@0 {
			reg = <0x0 0x0 0x0 0x0 0x0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x2000000 0x0 0x80000000
				  0x2000000 0x0 0x80000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x10000>;
		};
	};

	pci2: pcie@e000a000 {
		cell-index = <2>;
		compatible = "fsl,mpc8548-pcie";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe000a000 0x1000>;
		bus-range = <0 255>;
		ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
			  0x1000000 0x0 0x0 0xe1020000 0x0 0x10000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <25 2>;
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <
			/* IDSEL 0x0 */
			0000 0x0 0x0 0x1 &mpic 0x0 0x1
			0000 0x0 0x0 0x2 &mpic 0x1 0x1
			0000 0x0 0x0 0x3 &mpic 0x2 0x1
			0000 0x0 0x0 0x4 &mpic 0x3 0x1
			>;
		pcie@0 {
			reg = <0x0 0x0 0x0 0x0 0x0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x2000000 0x0 0xa0000000
				  0x2000000 0x0 0xa0000000
				  0x0 0x10000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x10000>;
		};
	};

	pci3: pcie@e000b000 {
		cell-index = <3>;
		compatible = "fsl,mpc8548-pcie";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe000b000 0x1000>;
		bus-range = <0 255>;
		ranges = <0x2000000 0x0 0xb0000000 0xb0000000 0x0 0x100000
			  0x1000000 0x0 0x0 0xb0100000 0x0 0x100000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <27 2>;
		interrupt-map-mask = <0xff00 0x0 0x0 0x1>;
		interrupt-map = <
			// IDSEL 0x1c  USB
			0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
			0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
			0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
			0xe300 0x0 0x0 0x4 &i8259 0xb 0x2

			// IDSEL 0x1d  Audio
			0xe800 0x0 0x0 0x1 &i8259 0x6 0x2

			// IDSEL 0x1e Legacy
			0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
			0xf100 0x0 0x0 0x1 &i8259 0x7 0x2

			// IDSEL 0x1f IDE/SATA
			0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
			0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
		>;

		pcie@0 {
			reg = <0x0 0x0 0x0 0x0 0x0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x2000000 0x0 0xb0000000
				  0x2000000 0x0 0xb0000000
				  0x0 0x100000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x100000>;

			uli1575@0 {
				reg = <0x0 0x0 0x0 0x0 0x0>;
				#size-cells = <2>;
				#address-cells = <3>;
				ranges = <0x2000000 0x0 0xb0000000
					  0x2000000 0x0 0xb0000000
					  0x0 0x100000

					  0x1000000 0x0 0x0
					  0x1000000 0x0 0x0
					  0x0 0x100000>;
				isa@1e {
					device_type = "isa";
					#interrupt-cells = <2>;
					#size-cells = <1>;
					#address-cells = <2>;
					reg = <0xf000 0x0 0x0 0x0 0x0>;
					ranges = <0x1 0x0
						  0x1000000 0x0 0x0
						  0x1000>;
					interrupt-parent = <&i8259>;

					i8259: interrupt-controller@20 {
						reg = <0x1 0x20 0x2
						       0x1 0xa0 0x2
						       0x1 0x4d0 0x2>;
						interrupt-controller;
						device_type = "interrupt-controller";
						#address-cells = <0>;
						#interrupt-cells = <2>;
						compatible = "chrp,iic";
						interrupts = <9 2>;
						interrupt-parent = <&mpic>;
					};

					i8042@60 {
						#size-cells = <0>;
						#address-cells = <1>;
						reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
						interrupts = <1 3 12 3>;
						interrupt-parent = <&i8259>;

						keyboard@0 {
							reg = <0x0>;
							compatible = "pnpPNP,303";
						};

						mouse@1 {
							reg = <0x1>;
							compatible = "pnpPNP,f03";
						};
					};

					rtc@70 {
						compatible = "pnpPNP,b00";
						reg = <0x1 0x70 0x2>;
					};

					gpio@400 {
						reg = <0x1 0x400 0x80>;
					};
				};
			};
		};
	};
};
Commit	Line	Data
d93daf84 JL	1	/*
	2	* MPC8544 DS Device Tree Source
	3	*
32f960e9	4	* Copyright 2007, 2008 Freescale Semiconductor Inc.
d93daf84 JL	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*/
	11
32f960e9	12	/dts-v1/;
d93daf84 JL	13	/ {
	14	model = "MPC8544DS";
	15	compatible = "MPC8544DS", "MPC85xxDS";
	16	#address-cells = <1>;
	17	#size-cells = <1>;
	18
ea082fa9 KG	19	aliases {
	20	ethernet0 = &enet0;
	21	ethernet1 = &enet1;
	22	serial0 = &serial0;
	23	serial1 = &serial1;
	24	pci0 = &pci0;
	25	pci1 = &pci1;
	26	pci2 = &pci2;
	27	pci3 = &pci3;
	28	};
	29
d93daf84	30	cpus {
d93daf84 JL	31	#address-cells = <1>;
	32	#size-cells = <0>;
	33
	34	PowerPC,8544@0 {
	35	device_type = "cpu";
32f960e9 KG	36	reg = <0x0>;
	37	d-cache-line-size = <32>; // 32 bytes
	38	i-cache-line-size = <32>; // 32 bytes
	39	d-cache-size = <0x8000>; // L1, 32K
	40	i-cache-size = <0x8000>; // L1, 32K
d93daf84 JL	41	timebase-frequency = <0>;
	42	bus-frequency = <0>;
	43	clock-frequency = <0>;
c054065b	44	next-level-cache = <&L2>;
d93daf84 JL	45	};
	46	};
	47
	48	memory {
	49	device_type = "memory";
32f960e9	50	reg = <0x0 0x0>; // Filled by U-Boot
d93daf84 JL	51	};
	52
	53	soc8544@e0000000 {
	54	#address-cells = <1>;
	55	#size-cells = <1>;
d93daf84	56	device_type = "soc";
cf0d19fb	57	compatible = "simple-bus";
b66510cb	58
32f960e9 KG	59	ranges = <0x0 0xe0000000 0x100000>;
32f960e9 KG	60	reg = <0xe0000000 0x1000>; // CCSRBAR 1M
d93daf84 JL	61	bus-frequency = <0>; // Filled out by uboot.
d93daf84 JL	62
4da421d6 KG	63	memory-controller@2000 {
4da421d6 KG	64	compatible = "fsl,8544-memory-controller";
32f960e9	65	reg = <0x2000 0x1000>;
4da421d6	66	interrupt-parent = <&mpic>;
32f960e9	67	interrupts = <18 2>;
4da421d6 KG	68	};
4da421d6 KG	69
c054065b	70	L2: l2-cache-controller@20000 {
4da421d6	71	compatible = "fsl,8544-l2-cache-controller";
32f960e9 KG	72	reg = <0x20000 0x1000>;
	73	cache-line-size = <32>; // 32 bytes
	74	cache-size = <0x40000>; // L2, 256K
4da421d6	75	interrupt-parent = <&mpic>;
32f960e9	76	interrupts = <16 2>;
4da421d6 KG	77	};
4da421d6 KG	78
d93daf84	79	i2c@3000 {
ec9686c4 KG	80	#address-cells = <1>;
	81	#size-cells = <0>;
	82	cell-index = <0>;
d93daf84	83	compatible = "fsl-i2c";
32f960e9 KG	84	reg = <0x3000 0x100>;
32f960e9 KG	85	interrupts = <43 2>;
d93daf84 JL	86	interrupt-parent = <&mpic>;
	87	dfsrr;
	88	};
	89
ec9686c4 KG	90	i2c@3100 {
	91	#address-cells = <1>;
	92	#size-cells = <0>;
	93	cell-index = <1>;
	94	compatible = "fsl-i2c";
32f960e9 KG	95	reg = <0x3100 0x100>;
32f960e9 KG	96	interrupts = <43 2>;
ec9686c4 KG	97	interrupt-parent = <&mpic>;
	98	dfsrr;
	99	};
	100
d93daf84 JL	101	mdio@24520 {
	102	#address-cells = <1>;
	103	#size-cells = <0>;
e77b28eb	104	compatible = "fsl,gianfar-mdio";
32f960e9	105	reg = <0x24520 0x20>;
e77b28eb	106
d93daf84 JL	107	phy0: ethernet-phy@0 {
d93daf84 JL	108	interrupt-parent = <&mpic>;
32f960e9 KG	109	interrupts = <10 1>;
32f960e9 KG	110	reg = <0x0>;
d93daf84 JL	111	device_type = "ethernet-phy";
	112	};
	113	phy1: ethernet-phy@1 {
	114	interrupt-parent = <&mpic>;
32f960e9 KG	115	interrupts = <10 1>;
32f960e9 KG	116	reg = <0x1>;
d93daf84 JL	117	device_type = "ethernet-phy";
	118	};
	119	};
	120
1028d4f1 SS	121	dma@21300 {
	122	#address-cells = <1>;
	123	#size-cells = <1>;
	124	compatible = "fsl,mpc8544-dma", "fsl,eloplus-dma";
32f960e9 KG	125	reg = <0x21300 0x4>;
32f960e9 KG	126	ranges = <0x0 0x21100 0x200>;
1028d4f1 SS	127	cell-index = <0>;
	128	dma-channel@0 {
	129	compatible = "fsl,mpc8544-dma-channel",
	130	"fsl,eloplus-dma-channel";
32f960e9	131	reg = <0x0 0x80>;
1028d4f1 SS	132	cell-index = <0>;
1028d4f1 SS	133	interrupt-parent = <&mpic>;
32f960e9	134	interrupts = <20 2>;
1028d4f1 SS	135	};
	136	dma-channel@80 {
	137	compatible = "fsl,mpc8544-dma-channel",
	138	"fsl,eloplus-dma-channel";
32f960e9	139	reg = <0x80 0x80>;
1028d4f1 SS	140	cell-index = <1>;
1028d4f1 SS	141	interrupt-parent = <&mpic>;
32f960e9	142	interrupts = <21 2>;
1028d4f1 SS	143	};
	144	dma-channel@100 {
	145	compatible = "fsl,mpc8544-dma-channel",
	146	"fsl,eloplus-dma-channel";
32f960e9	147	reg = <0x100 0x80>;
1028d4f1 SS	148	cell-index = <2>;
1028d4f1 SS	149	interrupt-parent = <&mpic>;
32f960e9	150	interrupts = <22 2>;
1028d4f1 SS	151	};
	152	dma-channel@180 {
	153	compatible = "fsl,mpc8544-dma-channel",
	154	"fsl,eloplus-dma-channel";
32f960e9	155	reg = <0x180 0x80>;
1028d4f1 SS	156	cell-index = <3>;
1028d4f1 SS	157	interrupt-parent = <&mpic>;
32f960e9	158	interrupts = <23 2>;
1028d4f1 SS	159	};
	160	};
	161
e77b28eb KG	162	enet0: ethernet@24000 {
e77b28eb KG	163	cell-index = <0>;
d93daf84 JL	164	device_type = "network";
	165	model = "TSEC";
	166	compatible = "gianfar";
32f960e9	167	reg = <0x24000 0x1000>;
d93daf84	168	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	169	interrupts = <29 2 30 2 34 2>;
d93daf84 JL	170	interrupt-parent = <&mpic>;
d93daf84 JL	171	phy-handle = <&phy0>;
9a9bcf4e	172	phy-connection-type = "rgmii-id";
d93daf84 JL	173	};
d93daf84 JL	174
e77b28eb KG	175	enet1: ethernet@26000 {
e77b28eb KG	176	cell-index = <1>;
d93daf84 JL	177	device_type = "network";
	178	model = "TSEC";
	179	compatible = "gianfar";
32f960e9	180	reg = <0x26000 0x1000>;
d93daf84	181	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	182	interrupts = <31 2 32 2 33 2>;
d93daf84 JL	183	interrupt-parent = <&mpic>;
d93daf84 JL	184	phy-handle = <&phy1>;
9a9bcf4e	185	phy-connection-type = "rgmii-id";
d93daf84 JL	186	};
d93daf84 JL	187
ea082fa9 KG	188	serial0: serial@4500 {
ea082fa9 KG	189	cell-index = <0>;
d93daf84 JL	190	device_type = "serial";
d93daf84 JL	191	compatible = "ns16550";
32f960e9	192	reg = <0x4500 0x100>;
d93daf84	193	clock-frequency = <0>;
32f960e9	194	interrupts = <42 2>;
d93daf84 JL	195	interrupt-parent = <&mpic>;
	196	};
	197
ea082fa9 KG	198	serial1: serial@4600 {
ea082fa9 KG	199	cell-index = <1>;
d93daf84 JL	200	device_type = "serial";
d93daf84 JL	201	compatible = "ns16550";
32f960e9	202	reg = <0x4600 0x100>;
d93daf84	203	clock-frequency = <0>;
32f960e9	204	interrupts = <42 2>;
d93daf84 JL	205	interrupt-parent = <&mpic>;
	206	};
	207
1b3c5cda KG	208	global-utilities@e0000 { //global utilities block
1b3c5cda KG	209	compatible = "fsl,mpc8548-guts";
32f960e9	210	reg = <0xe0000 0x1000>;
1b3c5cda KG	211	fsl,has-rstcr;
1b3c5cda KG	212	};
f16dab98	213
3fd44736 KP	214	crypto@30000 {
	215	compatible = "fsl,sec2.1", "fsl,sec2.0";
	216	reg = <0x30000 0x10000>;
	217	interrupts = <45 2>;
	218	interrupt-parent = <&mpic>;
	219	fsl,num-channels = <4>;
	220	fsl,channel-fifo-len = <24>;
	221	fsl,exec-units-mask = <0xfe>;
	222	fsl,descriptor-types-mask = <0x12b0ebf>;
	223	};
	224
1b3c5cda	225	mpic: pic@40000 {
1b3c5cda KG	226	interrupt-controller;
	227	#address-cells = <0>;
	228	#interrupt-cells = <2>;
32f960e9	229	reg = <0x40000 0x40000>;
1b3c5cda KG	230	compatible = "chrp,open-pic";
1b3c5cda KG	231	device_type = "open-pic";
1b3c5cda	232	};
741edc49 JJ	233
	234	msi@41600 {
	235	compatible = "fsl,mpc8544-msi", "fsl,mpic-msi";
	236	reg = <0x41600 0x80>;
	237	msi-available-ranges = <0 0x100>;
	238	interrupts = <
	239	0xe0 0
	240	0xe1 0
	241	0xe2 0
	242	0xe3 0
	243	0xe4 0
	244	0xe5 0
	245	0xe6 0
	246	0xe7 0>;
	247	interrupt-parent = <&mpic>;
	248	};
1b3c5cda	249	};
f16dab98	250
ea082fa9 KG	251	pci0: pci@e0008000 {
ea082fa9 KG	252	cell-index = <0>;
1b3c5cda KG	253	compatible = "fsl,mpc8540-pci";
1b3c5cda KG	254	device_type = "pci";
32f960e9	255	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
1b3c5cda KG	256	interrupt-map = <
	257
	258	/* IDSEL 0x11 J17 Slot 1 */
32f960e9 KG	259	0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
	260	0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
	261	0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
	262	0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
1b3c5cda KG	263
	264	/* IDSEL 0x12 J16 Slot 2 */
	265
32f960e9 KG	266	0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
	267	0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
	268	0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
	269	0x9000 0x0 0x0 0x4 &mpic 0x1 0x1>;
1b3c5cda KG	270
1b3c5cda KG	271	interrupt-parent = <&mpic>;
32f960e9 KG	272	interrupts = <24 2>;
	273	bus-range = <0 255>;
	274	ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
	275	0x1000000 0x0 0x0 0xe1000000 0x0 0x10000>;
	276	clock-frequency = <66666666>;
1b3c5cda KG	277	#interrupt-cells = <1>;
	278	#size-cells = <2>;
	279	#address-cells = <3>;
32f960e9	280	reg = <0xe0008000 0x1000>;
1b3c5cda	281	};
f16dab98	282
ea082fa9 KG	283	pci1: pcie@e0009000 {
ea082fa9 KG	284	cell-index = <1>;
1b3c5cda KG	285	compatible = "fsl,mpc8548-pcie";
	286	device_type = "pci";
	287	#interrupt-cells = <1>;
	288	#size-cells = <2>;
	289	#address-cells = <3>;
32f960e9 KG	290	reg = <0xe0009000 0x1000>;
	291	bus-range = <0 255>;
	292	ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
	293	0x1000000 0x0 0x0 0xe1010000 0x0 0x10000>;
	294	clock-frequency = <33333333>;
1b3c5cda	295	interrupt-parent = <&mpic>;
32f960e9 KG	296	interrupts = <26 2>;
32f960e9 KG	297	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
1b3c5cda KG	298	interrupt-map = <
1b3c5cda KG	299	/* IDSEL 0x0 */
32f960e9 KG	300	0000 0x0 0x0 0x1 &mpic 0x4 0x1
	301	0000 0x0 0x0 0x2 &mpic 0x5 0x1
	302	0000 0x0 0x0 0x3 &mpic 0x6 0x1
	303	0000 0x0 0x0 0x4 &mpic 0x7 0x1
1b3c5cda KG	304	>;
1b3c5cda KG	305	pcie@0 {
32f960e9	306	reg = <0x0 0x0 0x0 0x0 0x0>;
f16dab98 RZ	307	#size-cells = <2>;
f16dab98 RZ	308	#address-cells = <3>;
f16dab98	309	device_type = "pci";
32f960e9 KG	310	ranges = <0x2000000 0x0 0x80000000
	311	0x2000000 0x0 0x80000000
	312	0x0 0x20000000
1b3c5cda	313
32f960e9 KG	314	0x1000000 0x0 0x0
	315	0x1000000 0x0 0x0
	316	0x0 0x10000>;
f16dab98	317	};
1b3c5cda	318	};
f16dab98	319
ea082fa9 KG	320	pci2: pcie@e000a000 {
ea082fa9 KG	321	cell-index = <2>;
1b3c5cda KG	322	compatible = "fsl,mpc8548-pcie";
	323	device_type = "pci";
	324	#interrupt-cells = <1>;
	325	#size-cells = <2>;
	326	#address-cells = <3>;
32f960e9 KG	327	reg = <0xe000a000 0x1000>;
	328	bus-range = <0 255>;
	329	ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
	330	0x1000000 0x0 0x0 0xe1020000 0x0 0x10000>;
	331	clock-frequency = <33333333>;
1b3c5cda	332	interrupt-parent = <&mpic>;
32f960e9 KG	333	interrupts = <25 2>;
32f960e9 KG	334	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
1b3c5cda KG	335	interrupt-map = <
1b3c5cda KG	336	/* IDSEL 0x0 */
32f960e9 KG	337	0000 0x0 0x0 0x1 &mpic 0x0 0x1
	338	0000 0x0 0x0 0x2 &mpic 0x1 0x1
	339	0000 0x0 0x0 0x3 &mpic 0x2 0x1
	340	0000 0x0 0x0 0x4 &mpic 0x3 0x1
1b3c5cda KG	341	>;
1b3c5cda KG	342	pcie@0 {
32f960e9	343	reg = <0x0 0x0 0x0 0x0 0x0>;
f16dab98 RZ	344	#size-cells = <2>;
f16dab98 RZ	345	#address-cells = <3>;
1b3c5cda	346	device_type = "pci";
32f960e9 KG	347	ranges = <0x2000000 0x0 0xa0000000
	348	0x2000000 0x0 0xa0000000
	349	0x0 0x10000000
1b3c5cda	350
32f960e9 KG	351	0x1000000 0x0 0x0
	352	0x1000000 0x0 0x0
	353	0x0 0x10000>;
f16dab98	354	};
1b3c5cda	355	};
f16dab98	356
ea082fa9 KG	357	pci3: pcie@e000b000 {
ea082fa9 KG	358	cell-index = <3>;
1b3c5cda KG	359	compatible = "fsl,mpc8548-pcie";
	360	device_type = "pci";
	361	#interrupt-cells = <1>;
	362	#size-cells = <2>;
	363	#address-cells = <3>;
32f960e9 KG	364	reg = <0xe000b000 0x1000>;
	365	bus-range = <0 255>;
	366	ranges = <0x2000000 0x0 0xb0000000 0xb0000000 0x0 0x100000
	367	0x1000000 0x0 0x0 0xb0100000 0x0 0x100000>;
	368	clock-frequency = <33333333>;
1b3c5cda	369	interrupt-parent = <&mpic>;
32f960e9 KG	370	interrupts = <27 2>;
32f960e9 KG	371	interrupt-map-mask = <0xff00 0x0 0x0 0x1>;
1b3c5cda KG	372	interrupt-map = <
1b3c5cda KG	373	// IDSEL 0x1c USB
32f960e9 KG	374	0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
	375	0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
	376	0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
	377	0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
1b3c5cda KG	378
1b3c5cda KG	379	// IDSEL 0x1d Audio
32f960e9	380	0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
1b3c5cda KG	381
1b3c5cda KG	382	// IDSEL 0x1e Legacy
32f960e9 KG	383	0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
32f960e9 KG	384	0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
1b3c5cda KG	385
1b3c5cda KG	386	// IDSEL 0x1f IDE/SATA
32f960e9 KG	387	0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
32f960e9 KG	388	0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
1b3c5cda KG	389	>;
	390
	391	pcie@0 {
32f960e9	392	reg = <0x0 0x0 0x0 0x0 0x0>;
f16dab98 RZ	393	#size-cells = <2>;
f16dab98 RZ	394	#address-cells = <3>;
1b3c5cda	395	device_type = "pci";
32f960e9 KG	396	ranges = <0x2000000 0x0 0xb0000000
	397	0x2000000 0x0 0xb0000000
	398	0x0 0x100000
1b3c5cda	399
32f960e9 KG	400	0x1000000 0x0 0x0
	401	0x1000000 0x0 0x0
	402	0x0 0x100000>;
1b3c5cda	403
f16dab98	404	uli1575@0 {
32f960e9	405	reg = <0x0 0x0 0x0 0x0 0x0>;
f16dab98 RZ	406	#size-cells = <2>;
f16dab98 RZ	407	#address-cells = <3>;
32f960e9 KG	408	ranges = <0x2000000 0x0 0xb0000000
	409	0x2000000 0x0 0xb0000000
	410	0x0 0x100000
1b3c5cda	411
32f960e9 KG	412	0x1000000 0x0 0x0
	413	0x1000000 0x0 0x0
	414	0x0 0x100000>;
1b3c5cda KG	415	isa@1e {
	416	device_type = "isa";
	417	#interrupt-cells = <2>;
	418	#size-cells = <1>;
	419	#address-cells = <2>;
32f960e9 KG	420	reg = <0xf000 0x0 0x0 0x0 0x0>;
	421	ranges = <0x1 0x0
	422	0x1000000 0x0 0x0
	423	0x1000>;
1b3c5cda KG	424	interrupt-parent = <&i8259>;
	425
	426	i8259: interrupt-controller@20 {
32f960e9 KG	427	reg = <0x1 0x20 0x2
	428	0x1 0xa0 0x2
	429	0x1 0x4d0 0x2>;
1b3c5cda KG	430	interrupt-controller;
	431	device_type = "interrupt-controller";
	432	#address-cells = <0>;
f16dab98	433	#interrupt-cells = <2>;
1b3c5cda KG	434	compatible = "chrp,iic";
	435	interrupts = <9 2>;
	436	interrupt-parent = <&mpic>;
	437	};
	438
	439	i8042@60 {
	440	#size-cells = <0>;
	441	#address-cells = <1>;
32f960e9 KG	442	reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
32f960e9 KG	443	interrupts = <1 3 12 3>;
f16dab98 RZ	444	interrupt-parent = <&i8259>;
f16dab98 RZ	445
1b3c5cda	446	keyboard@0 {
32f960e9	447	reg = <0x0>;
1b3c5cda	448	compatible = "pnpPNP,303";
f16dab98 RZ	449	};
f16dab98 RZ	450
1b3c5cda	451	mouse@1 {
32f960e9	452	reg = <0x1>;
1b3c5cda	453	compatible = "pnpPNP,f03";
f16dab98	454	};
1b3c5cda	455	};
f16dab98	456
1b3c5cda KG	457	rtc@70 {
1b3c5cda KG	458	compatible = "pnpPNP,b00";
32f960e9	459	reg = <0x1 0x70 0x2>;
1b3c5cda	460	};
f16dab98	461
1b3c5cda	462	gpio@400 {
32f960e9	463	reg = <0x1 0x400 0x80>;
f16dab98 RZ	464	};
	465	};
	466	};
f16dab98	467	};
d93daf84 JL	468	};
d93daf84 JL	469	};