[deliverable/linux.git] / arch / powerpc / boot / dts / mpc8548cds.dts

/*
 * MPC8548 CDS Device Tree Source
 *
 * Copyright 2006, 2008 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/dts-v1/;

/ {
	model = "MPC8548CDS";
	compatible = "MPC8548CDS", "MPC85xxCDS";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
/*
		ethernet2 = &enet2;
		ethernet3 = &enet3;
*/
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
		pci1 = &pci1;
		pci2 = &pci2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8548@0 {
			device_type = "cpu";
			reg = <0x0>;
			d-cache-line-size = <32>;	// 32 bytes
			i-cache-line-size = <32>;	// 32 bytes
			d-cache-size = <0x8000>;		// L1, 32K
			i-cache-size = <0x8000>;		// L1, 32K
			timebase-frequency = <0>;	//  33 MHz, from uboot
			bus-frequency = <0>;	// 166 MHz
			clock-frequency = <0>;	// 825 MHz, from uboot
			next-level-cache = <&L2>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x8000000>;	// 128M at 0x0
	};

	soc8548@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		compatible = "simple-bus";
		ranges = <0x0 0xe0000000 0x100000>;
		bus-frequency = <0>;

		ecm-law@0 {
			compatible = "fsl,ecm-law";
			reg = <0x0 0x1000>;
			fsl,num-laws = <10>;
		};

		ecm@1000 {
			compatible = "fsl,mpc8548-ecm", "fsl,ecm";
			reg = <0x1000 0x1000>;
			interrupts = <17 2>;
			interrupt-parent = <&mpic>;
		};

		memory-controller@2000 {
			compatible = "fsl,8548-memory-controller";
			reg = <0x2000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <18 2>;
		};

		L2: l2-cache-controller@20000 {
			compatible = "fsl,8548-l2-cache-controller";
			reg = <0x20000 0x1000>;
			cache-line-size = <32>;	// 32 bytes
			cache-size = <0x80000>;	// L2, 512K
			interrupt-parent = <&mpic>;
			interrupts = <16 2>;
		};

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		dma@21300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
			reg = <0x21300 0x4>;
			ranges = <0x0 0x21100 0x200>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,mpc8548-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x0 0x80>;
				cell-index = <0>;
				interrupt-parent = <&mpic>;
				interrupts = <20 2>;
			};
			dma-channel@80 {
				compatible = "fsl,mpc8548-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupt-parent = <&mpic>;
				interrupts = <21 2>;
			};
			dma-channel@100 {
				compatible = "fsl,mpc8548-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupt-parent = <&mpic>;
				interrupts = <22 2>;
			};
			dma-channel@180 {
				compatible = "fsl,mpc8548-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x180 0x80>;
				cell-index = <3>;
				interrupt-parent = <&mpic>;
				interrupts = <23 2>;
			};
		};

		enet0: ethernet@24000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <0>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x24000 0x1000>;
			ranges = <0x0 0x24000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <29 2 30 2 34 2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi0>;
			phy-handle = <&phy0>;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-mdio";
				reg = <0x520 0x20>;

				phy0: ethernet-phy@0 {
					interrupt-parent = <&mpic>;
					interrupts = <5 1>;
					reg = <0x0>;
					device_type = "ethernet-phy";
				};
				phy1: ethernet-phy@1 {
					interrupt-parent = <&mpic>;
					interrupts = <5 1>;
					reg = <0x1>;
					device_type = "ethernet-phy";
				};
				phy2: ethernet-phy@2 {
					interrupt-parent = <&mpic>;
					interrupts = <5 1>;
					reg = <0x2>;
					device_type = "ethernet-phy";
				};
				phy3: ethernet-phy@3 {
					interrupt-parent = <&mpic>;
					interrupts = <5 1>;
					reg = <0x3>;
					device_type = "ethernet-phy";
				};
				tbi0: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		enet1: ethernet@25000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <1>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x25000 0x1000>;
			ranges = <0x0 0x25000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <35 2 36 2 40 2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi1>;
			phy-handle = <&phy1>;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-tbi";
				reg = <0x520 0x20>;

				tbi1: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

/* eTSEC 3/4 are currently broken
		enet2: ethernet@26000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <2>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x26000 0x1000>;
			ranges = <0x0 0x26000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <31 2 32 2 33 2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi2>;
			phy-handle = <&phy2>;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-tbi";
				reg = <0x520 0x20>;

				tbi2: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		enet3: ethernet@27000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <3>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x27000 0x1000>;
			ranges = <0x0 0x27000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <37 2 38 2 39 2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi3>;
			phy-handle = <&phy3>;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-tbi";
				reg = <0x520 0x20>;

				tbi3: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};
 */

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4500 0x100>;	// reg base, size
			clock-frequency = <0>;	// should we fill in in uboot?
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4600 0x100>;	// reg base, size
			clock-frequency = <0>;	// should we fill in in uboot?
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		global-utilities@e0000 {	//global utilities reg
			compatible = "fsl,mpc8548-guts";
			reg = <0xe0000 0x1000>;
			fsl,has-rstcr;
		};

		crypto@30000 {
			compatible = "fsl,sec2.1", "fsl,sec2.0";
			reg = <0x30000 0x10000>;
			interrupts = <45 2>;
			interrupt-parent = <&mpic>;
			fsl,num-channels = <4>;
			fsl,channel-fifo-len = <24>;
			fsl,exec-units-mask = <0xfe>;
			fsl,descriptor-types-mask = <0x12b0ebf>;
		};

		mpic: pic@40000 {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x40000 0x40000>;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
		};
	};

	pci0: pci@e0008000 {
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <
			/* IDSEL 0x4 (PCIX Slot 2) */
			0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
			0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
			0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
			0x2000 0x0 0x0 0x4 &mpic 0x3 0x1

			/* IDSEL 0x5 (PCIX Slot 3) */
			0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
			0x2800 0x0 0x0 0x2 &mpic 0x2 0x1
			0x2800 0x0 0x0 0x3 &mpic 0x3 0x1
			0x2800 0x0 0x0 0x4 &mpic 0x0 0x1

			/* IDSEL 0x6 (PCIX Slot 4) */
			0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
			0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
			0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
			0x3000 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x8 (PCIX Slot 5) */
			0x4000 0x0 0x0 0x1 &mpic 0x0 0x1
			0x4000 0x0 0x0 0x2 &mpic 0x1 0x1
			0x4000 0x0 0x0 0x3 &mpic 0x2 0x1
			0x4000 0x0 0x0 0x4 &mpic 0x3 0x1

			/* IDSEL 0xC (Tsi310 bridge) */
			0x6000 0x0 0x0 0x1 &mpic 0x0 0x1
			0x6000 0x0 0x0 0x2 &mpic 0x1 0x1
			0x6000 0x0 0x0 0x3 &mpic 0x2 0x1
			0x6000 0x0 0x0 0x4 &mpic 0x3 0x1

			/* IDSEL 0x14 (Slot 2) */
			0xa000 0x0 0x0 0x1 &mpic 0x0 0x1
			0xa000 0x0 0x0 0x2 &mpic 0x1 0x1
			0xa000 0x0 0x0 0x3 &mpic 0x2 0x1
			0xa000 0x0 0x0 0x4 &mpic 0x3 0x1

			/* IDSEL 0x15 (Slot 3) */
			0xa800 0x0 0x0 0x1 &mpic 0x1 0x1
			0xa800 0x0 0x0 0x2 &mpic 0x2 0x1
			0xa800 0x0 0x0 0x3 &mpic 0x3 0x1
			0xa800 0x0 0x0 0x4 &mpic 0x0 0x1

			/* IDSEL 0x16 (Slot 4) */
			0xb000 0x0 0x0 0x1 &mpic 0x2 0x1
			0xb000 0x0 0x0 0x2 &mpic 0x3 0x1
			0xb000 0x0 0x0 0x3 &mpic 0x0 0x1
			0xb000 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x18 (Slot 5) */
			0xc000 0x0 0x0 0x1 &mpic 0x0 0x1
			0xc000 0x0 0x0 0x2 &mpic 0x1 0x1
			0xc000 0x0 0x0 0x3 &mpic 0x2 0x1
			0xc000 0x0 0x0 0x4 &mpic 0x3 0x1

			/* IDSEL 0x1C (Tsi310 bridge PCI primary) */
			0xe000 0x0 0x0 0x1 &mpic 0x0 0x1
			0xe000 0x0 0x0 0x2 &mpic 0x1 0x1
			0xe000 0x0 0x0 0x3 &mpic 0x2 0x1
			0xe000 0x0 0x0 0x4 &mpic 0x3 0x1>;

		interrupt-parent = <&mpic>;
		interrupts = <24 2>;
		bus-range = <0 0>;
		ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
			  0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
		clock-frequency = <66666666>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0008000 0x1000>;
		compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
		device_type = "pci";

		pci_bridge@1c {
			interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
			interrupt-map = <

				/* IDSEL 0x00 (PrPMC Site) */
				0000 0x0 0x0 0x1 &mpic 0x0 0x1
				0000 0x0 0x0 0x2 &mpic 0x1 0x1
				0000 0x0 0x0 0x3 &mpic 0x2 0x1
				0000 0x0 0x0 0x4 &mpic 0x3 0x1

				/* IDSEL 0x04 (VIA chip) */
				0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
				0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
				0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
				0x2000 0x0 0x0 0x4 &mpic 0x3 0x1

				/* IDSEL 0x05 (8139) */
				0x2800 0x0 0x0 0x1 &mpic 0x1 0x1

				/* IDSEL 0x06 (Slot 6) */
				0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
				0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
				0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
				0x3000 0x0 0x0 0x4 &mpic 0x1 0x1

				/* IDESL 0x07 (Slot 7) */
				0x3800 0x0 0x0 0x1 &mpic 0x3 0x1
				0x3800 0x0 0x0 0x2 &mpic 0x0 0x1
				0x3800 0x0 0x0 0x3 &mpic 0x1 0x1
				0x3800 0x0 0x0 0x4 &mpic 0x2 0x1>;

			reg = <0xe000 0x0 0x0 0x0 0x0>;
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			ranges = <0x2000000 0x0 0x80000000
				  0x2000000 0x0 0x80000000
				  0x0 0x20000000
				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x80000>;
			clock-frequency = <33333333>;

			isa@4 {
				device_type = "isa";
				#interrupt-cells = <2>;
				#size-cells = <1>;
				#address-cells = <2>;
				reg = <0x2000 0x0 0x0 0x0 0x0>;
				ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
				interrupt-parent = <&i8259>;

				i8259: interrupt-controller@20 {
					interrupt-controller;
					device_type = "interrupt-controller";
					reg = <0x1 0x20 0x2
					       0x1 0xa0 0x2
					       0x1 0x4d0 0x2>;
					#address-cells = <0>;
					#interrupt-cells = <2>;
					compatible = "chrp,iic";
					interrupts = <0 1>;
					interrupt-parent = <&mpic>;
				};

				rtc@70 {
					compatible = "pnpPNP,b00";
					reg = <0x1 0x70 0x2>;
				};
			};
		};
	};

	pci1: pci@e0009000 {
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <

			/* IDSEL 0x15 */
			0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
			0xa800 0x0 0x0 0x2 &mpic 0x1 0x1
			0xa800 0x0 0x0 0x3 &mpic 0x2 0x1
			0xa800 0x0 0x0 0x4 &mpic 0x3 0x1>;

		interrupt-parent = <&mpic>;
		interrupts = <25 2>;
		bus-range = <0 0>;
		ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
			  0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
		clock-frequency = <66666666>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0009000 0x1000>;
		compatible = "fsl,mpc8540-pci";
		device_type = "pci";
	};

	pci2: pcie@e000a000 {
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <

			/* IDSEL 0x0 (PEX) */
			00000 0x0 0x0 0x1 &mpic 0x0 0x1
			00000 0x0 0x0 0x2 &mpic 0x1 0x1
			00000 0x0 0x0 0x3 &mpic 0x2 0x1
			00000 0x0 0x0 0x4 &mpic 0x3 0x1>;

		interrupt-parent = <&mpic>;
		interrupts = <26 2>;
		bus-range = <0 255>;
		ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
			  0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
		clock-frequency = <33333333>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe000a000 0x1000>;
		compatible = "fsl,mpc8548-pcie";
		device_type = "pci";
		pcie@0 {
			reg = <0x0 0x0 0x0 0x0 0x0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x2000000 0x0 0xa0000000
				  0x2000000 0x0 0xa0000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x100000>;
		};
	};
};
Commit	Line	Data
2654d638	1	/*
02edff59	2	* MPC8548 CDS Device Tree Source
2654d638	3	*
32f960e9	4	* Copyright 2006, 2008 Freescale Semiconductor Inc.
2654d638 AF	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*/
	11
32f960e9	12	/dts-v1/;
2654d638 AF	13
	14	/ {
	15	model = "MPC8548CDS";
52094879	16	compatible = "MPC8548CDS", "MPC85xxCDS";
2654d638 AF	17	#address-cells = <1>;
2654d638 AF	18	#size-cells = <1>;
2654d638	19
ea082fa9 KG	20	aliases {
	21	ethernet0 = &enet0;
	22	ethernet1 = &enet1;
	23	/*
	24	ethernet2 = &enet2;
	25	ethernet3 = &enet3;
	26	*/
	27	serial0 = &serial0;
	28	serial1 = &serial1;
	29	pci0 = &pci0;
	30	pci1 = &pci1;
	31	pci2 = &pci2;
	32	};
	33
2654d638	34	cpus {
2654d638 AF	35	#address-cells = <1>;
2654d638 AF	36	#size-cells = <0>;
2654d638 AF	37
	38	PowerPC,8548@0 {
	39	device_type = "cpu";
32f960e9 KG	40	reg = <0x0>;
	41	d-cache-line-size = <32>; // 32 bytes
	42	i-cache-line-size = <32>; // 32 bytes
	43	d-cache-size = <0x8000>; // L1, 32K
	44	i-cache-size = <0x8000>; // L1, 32K
2654d638 AF	45	timebase-frequency = <0>; // 33 MHz, from uboot
	46	bus-frequency = <0>; // 166 MHz
	47	clock-frequency = <0>; // 825 MHz, from uboot
c054065b	48	next-level-cache = <&L2>;
2654d638 AF	49	};
	50	};
	51
	52	memory {
	53	device_type = "memory";
32f960e9	54	reg = <0x0 0x8000000>; // 128M at 0x0
2654d638 AF	55	};
	56
	57	soc8548@e0000000 {
	58	#address-cells = <1>;
	59	#size-cells = <1>;
2654d638	60	device_type = "soc";
cf0d19fb	61	compatible = "simple-bus";
32f960e9	62	ranges = <0x0 0xe0000000 0x100000>;
2654d638 AF	63	bus-frequency = <0>;
2654d638 AF	64
e1a22897 KG	65	ecm-law@0 {
	66	compatible = "fsl,ecm-law";
	67	reg = <0x0 0x1000>;
	68	fsl,num-laws = <10>;
	69	};
	70
	71	ecm@1000 {
	72	compatible = "fsl,mpc8548-ecm", "fsl,ecm";
	73	reg = <0x1000 0x1000>;
	74	interrupts = <17 2>;
	75	interrupt-parent = <&mpic>;
	76	};
	77
50cf6707 DJ	78	memory-controller@2000 {
50cf6707 DJ	79	compatible = "fsl,8548-memory-controller";
32f960e9	80	reg = <0x2000 0x1000>;
50cf6707	81	interrupt-parent = <&mpic>;
32f960e9	82	interrupts = <18 2>;
50cf6707 DJ	83	};
50cf6707 DJ	84
c054065b	85	L2: l2-cache-controller@20000 {
50cf6707	86	compatible = "fsl,8548-l2-cache-controller";
32f960e9 KG	87	reg = <0x20000 0x1000>;
	88	cache-line-size = <32>; // 32 bytes
	89	cache-size = <0x80000>; // L2, 512K
50cf6707	90	interrupt-parent = <&mpic>;
32f960e9	91	interrupts = <16 2>;
50cf6707 DJ	92	};
50cf6707 DJ	93
2654d638	94	i2c@3000 {
ec9686c4 KG	95	#address-cells = <1>;
	96	#size-cells = <0>;
	97	cell-index = <0>;
2654d638	98	compatible = "fsl-i2c";
32f960e9 KG	99	reg = <0x3000 0x100>;
32f960e9 KG	100	interrupts = <43 2>;
52094879	101	interrupt-parent = <&mpic>;
2654d638 AF	102	dfsrr;
	103	};
	104
ec9686c4 KG	105	i2c@3100 {
	106	#address-cells = <1>;
	107	#size-cells = <0>;
	108	cell-index = <1>;
	109	compatible = "fsl-i2c";
32f960e9 KG	110	reg = <0x3100 0x100>;
32f960e9 KG	111	interrupts = <43 2>;
ec9686c4 KG	112	interrupt-parent = <&mpic>;
	113	dfsrr;
	114	};
	115
dee80553 KG	116	dma@21300 {
	117	#address-cells = <1>;
	118	#size-cells = <1>;
	119	compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
	120	reg = <0x21300 0x4>;
	121	ranges = <0x0 0x21100 0x200>;
	122	cell-index = <0>;
	123	dma-channel@0 {
	124	compatible = "fsl,mpc8548-dma-channel",
	125	"fsl,eloplus-dma-channel";
	126	reg = <0x0 0x80>;
	127	cell-index = <0>;
	128	interrupt-parent = <&mpic>;
	129	interrupts = <20 2>;
	130	};
	131	dma-channel@80 {
	132	compatible = "fsl,mpc8548-dma-channel",
	133	"fsl,eloplus-dma-channel";
	134	reg = <0x80 0x80>;
	135	cell-index = <1>;
	136	interrupt-parent = <&mpic>;
	137	interrupts = <21 2>;
	138	};
	139	dma-channel@100 {
	140	compatible = "fsl,mpc8548-dma-channel",
	141	"fsl,eloplus-dma-channel";
	142	reg = <0x100 0x80>;
	143	cell-index = <2>;
	144	interrupt-parent = <&mpic>;
	145	interrupts = <22 2>;
	146	};
	147	dma-channel@180 {
	148	compatible = "fsl,mpc8548-dma-channel",
	149	"fsl,eloplus-dma-channel";
	150	reg = <0x180 0x80>;
	151	cell-index = <3>;
	152	interrupt-parent = <&mpic>;
	153	interrupts = <23 2>;
	154	};
	155	};
	156
e77b28eb	157	enet0: ethernet@24000 {
84ba4a58 AV	158	#address-cells = <1>;
84ba4a58 AV	159	#size-cells = <1>;
e77b28eb	160	cell-index = <0>;
2654d638 AF	161	device_type = "network";
	162	model = "eTSEC";
	163	compatible = "gianfar";
32f960e9	164	reg = <0x24000 0x1000>;
84ba4a58	165	ranges = <0x0 0x24000 0x1000>;
eae98266	166	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	167	interrupts = <29 2 30 2 34 2>;
52094879	168	interrupt-parent = <&mpic>;
b31a1d8b	169	tbi-handle = <&tbi0>;
52094879	170	phy-handle = <&phy0>;
84ba4a58 AV	171
	172	mdio@520 {
	173	#address-cells = <1>;
	174	#size-cells = <0>;
	175	compatible = "fsl,gianfar-mdio";
	176	reg = <0x520 0x20>;
	177
	178	phy0: ethernet-phy@0 {
	179	interrupt-parent = <&mpic>;
	180	interrupts = <5 1>;
	181	reg = <0x0>;
	182	device_type = "ethernet-phy";
	183	};
	184	phy1: ethernet-phy@1 {
	185	interrupt-parent = <&mpic>;
	186	interrupts = <5 1>;
	187	reg = <0x1>;
	188	device_type = "ethernet-phy";
	189	};
	190	phy2: ethernet-phy@2 {
	191	interrupt-parent = <&mpic>;
	192	interrupts = <5 1>;
	193	reg = <0x2>;
	194	device_type = "ethernet-phy";
	195	};
	196	phy3: ethernet-phy@3 {
	197	interrupt-parent = <&mpic>;
	198	interrupts = <5 1>;
	199	reg = <0x3>;
	200	device_type = "ethernet-phy";
	201	};
	202	tbi0: tbi-phy@11 {
	203	reg = <0x11>;
	204	device_type = "tbi-phy";
	205	};
	206	};
2654d638 AF	207	};
2654d638 AF	208
e77b28eb	209	enet1: ethernet@25000 {
84ba4a58 AV	210	#address-cells = <1>;
84ba4a58 AV	211	#size-cells = <1>;
e77b28eb	212	cell-index = <1>;
2654d638 AF	213	device_type = "network";
	214	model = "eTSEC";
	215	compatible = "gianfar";
32f960e9	216	reg = <0x25000 0x1000>;
84ba4a58	217	ranges = <0x0 0x25000 0x1000>;
eae98266	218	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	219	interrupts = <35 2 36 2 40 2>;
52094879	220	interrupt-parent = <&mpic>;
b31a1d8b	221	tbi-handle = <&tbi1>;
52094879	222	phy-handle = <&phy1>;
84ba4a58 AV	223
	224	mdio@520 {
	225	#address-cells = <1>;
	226	#size-cells = <0>;
	227	compatible = "fsl,gianfar-tbi";
	228	reg = <0x520 0x20>;
	229
	230	tbi1: tbi-phy@11 {
	231	reg = <0x11>;
	232	device_type = "tbi-phy";
	233	};
	234	};
2654d638 AF	235	};
2654d638 AF	236
52094879	237	/* eTSEC 3/4 are currently broken
e77b28eb	238	enet2: ethernet@26000 {
84ba4a58 AV	239	#address-cells = <1>;
84ba4a58 AV	240	#size-cells = <1>;
e77b28eb	241	cell-index = <2>;
2654d638 AF	242	device_type = "network";
	243	model = "eTSEC";
	244	compatible = "gianfar";
32f960e9	245	reg = <0x26000 0x1000>;
84ba4a58	246	ranges = <0x0 0x26000 0x1000>;
eae98266	247	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	248	interrupts = <31 2 32 2 33 2>;
52094879	249	interrupt-parent = <&mpic>;
b31a1d8b	250	tbi-handle = <&tbi2>;
52094879	251	phy-handle = <&phy2>;
84ba4a58 AV	252
	253	mdio@520 {
	254	#address-cells = <1>;
	255	#size-cells = <0>;
	256	compatible = "fsl,gianfar-tbi";
	257	reg = <0x520 0x20>;
	258
	259	tbi2: tbi-phy@11 {
	260	reg = <0x11>;
	261	device_type = "tbi-phy";
	262	};
	263	};
2654d638 AF	264	};
2654d638 AF	265
e77b28eb	266	enet3: ethernet@27000 {
84ba4a58 AV	267	#address-cells = <1>;
84ba4a58 AV	268	#size-cells = <1>;
e77b28eb	269	cell-index = <3>;
2654d638 AF	270	device_type = "network";
	271	model = "eTSEC";
	272	compatible = "gianfar";
32f960e9	273	reg = <0x27000 0x1000>;
84ba4a58	274	ranges = <0x0 0x27000 0x1000>;
eae98266	275	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	276	interrupts = <37 2 38 2 39 2>;
52094879	277	interrupt-parent = <&mpic>;
b31a1d8b	278	tbi-handle = <&tbi3>;
52094879	279	phy-handle = <&phy3>;
84ba4a58 AV	280
	281	mdio@520 {
	282	#address-cells = <1>;
	283	#size-cells = <0>;
	284	compatible = "fsl,gianfar-tbi";
	285	reg = <0x520 0x20>;
	286
	287	tbi3: tbi-phy@11 {
	288	reg = <0x11>;
	289	device_type = "tbi-phy";
	290	};
	291	};
2654d638 AF	292	};
	293	*/
	294
ea082fa9 KG	295	serial0: serial@4500 {
ea082fa9 KG	296	cell-index = <0>;
2654d638 AF	297	device_type = "serial";
2654d638 AF	298	compatible = "ns16550";
32f960e9	299	reg = <0x4500 0x100>; // reg base, size
6af01257	300	clock-frequency = <0>; // should we fill in in uboot?
32f960e9	301	interrupts = <42 2>;
52094879	302	interrupt-parent = <&mpic>;
2654d638 AF	303	};
2654d638 AF	304
ea082fa9 KG	305	serial1: serial@4600 {
ea082fa9 KG	306	cell-index = <1>;
2654d638 AF	307	device_type = "serial";
2654d638 AF	308	compatible = "ns16550";
32f960e9	309	reg = <0x4600 0x100>; // reg base, size
6af01257	310	clock-frequency = <0>; // should we fill in in uboot?
32f960e9	311	interrupts = <42 2>;
52094879	312	interrupt-parent = <&mpic>;
2654d638 AF	313	};
2654d638 AF	314
68fb0d20 RZ	315	global-utilities@e0000 { //global utilities reg
68fb0d20 RZ	316	compatible = "fsl,mpc8548-guts";
32f960e9	317	reg = <0xe0000 0x1000>;
68fb0d20 RZ	318	fsl,has-rstcr;
	319	};
	320
3fd44736 KP	321	crypto@30000 {
	322	compatible = "fsl,sec2.1", "fsl,sec2.0";
	323	reg = <0x30000 0x10000>;
	324	interrupts = <45 2>;
	325	interrupt-parent = <&mpic>;
	326	fsl,num-channels = <4>;
	327	fsl,channel-fifo-len = <24>;
	328	fsl,exec-units-mask = <0xfe>;
	329	fsl,descriptor-types-mask = <0x12b0ebf>;
	330	};
	331
1b3c5cda	332	mpic: pic@40000 {
1b3c5cda KG	333	interrupt-controller;
	334	#address-cells = <0>;
	335	#interrupt-cells = <2>;
32f960e9	336	reg = <0x40000 0x40000>;
1b3c5cda KG	337	compatible = "chrp,open-pic";
1b3c5cda KG	338	device_type = "open-pic";
1b3c5cda KG	339	};
	340	};
	341
ea082fa9	342	pci0: pci@e0008000 {
32f960e9	343	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
1b3c5cda KG	344	interrupt-map = <
1b3c5cda KG	345	/* IDSEL 0x4 (PCIX Slot 2) */
32f960e9 KG	346	0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
	347	0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
	348	0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
	349	0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
1b3c5cda KG	350
1b3c5cda KG	351	/* IDSEL 0x5 (PCIX Slot 3) */
32f960e9 KG	352	0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
	353	0x2800 0x0 0x0 0x2 &mpic 0x2 0x1
	354	0x2800 0x0 0x0 0x3 &mpic 0x3 0x1
	355	0x2800 0x0 0x0 0x4 &mpic 0x0 0x1
1b3c5cda KG	356
1b3c5cda KG	357	/* IDSEL 0x6 (PCIX Slot 4) */
32f960e9 KG	358	0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
	359	0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
	360	0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
	361	0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
1b3c5cda KG	362
1b3c5cda KG	363	/* IDSEL 0x8 (PCIX Slot 5) */
32f960e9 KG	364	0x4000 0x0 0x0 0x1 &mpic 0x0 0x1
	365	0x4000 0x0 0x0 0x2 &mpic 0x1 0x1
	366	0x4000 0x0 0x0 0x3 &mpic 0x2 0x1
	367	0x4000 0x0 0x0 0x4 &mpic 0x3 0x1
1b3c5cda KG	368
1b3c5cda KG	369	/* IDSEL 0xC (Tsi310 bridge) */
32f960e9 KG	370	0x6000 0x0 0x0 0x1 &mpic 0x0 0x1
	371	0x6000 0x0 0x0 0x2 &mpic 0x1 0x1
	372	0x6000 0x0 0x0 0x3 &mpic 0x2 0x1
	373	0x6000 0x0 0x0 0x4 &mpic 0x3 0x1
1b3c5cda KG	374
1b3c5cda KG	375	/* IDSEL 0x14 (Slot 2) */
32f960e9 KG	376	0xa000 0x0 0x0 0x1 &mpic 0x0 0x1
	377	0xa000 0x0 0x0 0x2 &mpic 0x1 0x1
	378	0xa000 0x0 0x0 0x3 &mpic 0x2 0x1
	379	0xa000 0x0 0x0 0x4 &mpic 0x3 0x1
1b3c5cda KG	380
1b3c5cda KG	381	/* IDSEL 0x15 (Slot 3) */
32f960e9 KG	382	0xa800 0x0 0x0 0x1 &mpic 0x1 0x1
	383	0xa800 0x0 0x0 0x2 &mpic 0x2 0x1
	384	0xa800 0x0 0x0 0x3 &mpic 0x3 0x1
	385	0xa800 0x0 0x0 0x4 &mpic 0x0 0x1
1b3c5cda KG	386
1b3c5cda KG	387	/* IDSEL 0x16 (Slot 4) */
32f960e9 KG	388	0xb000 0x0 0x0 0x1 &mpic 0x2 0x1
	389	0xb000 0x0 0x0 0x2 &mpic 0x3 0x1
	390	0xb000 0x0 0x0 0x3 &mpic 0x0 0x1
	391	0xb000 0x0 0x0 0x4 &mpic 0x1 0x1
1b3c5cda KG	392
1b3c5cda KG	393	/* IDSEL 0x18 (Slot 5) */
32f960e9 KG	394	0xc000 0x0 0x0 0x1 &mpic 0x0 0x1
	395	0xc000 0x0 0x0 0x2 &mpic 0x1 0x1
	396	0xc000 0x0 0x0 0x3 &mpic 0x2 0x1
	397	0xc000 0x0 0x0 0x4 &mpic 0x3 0x1
1b3c5cda KG	398
1b3c5cda KG	399	/* IDSEL 0x1C (Tsi310 bridge PCI primary) */
32f960e9 KG	400	0xe000 0x0 0x0 0x1 &mpic 0x0 0x1
	401	0xe000 0x0 0x0 0x2 &mpic 0x1 0x1
	402	0xe000 0x0 0x0 0x3 &mpic 0x2 0x1
	403	0xe000 0x0 0x0 0x4 &mpic 0x3 0x1>;
1b3c5cda KG	404
1b3c5cda KG	405	interrupt-parent = <&mpic>;
32f960e9	406	interrupts = <24 2>;
1b3c5cda	407	bus-range = <0 0>;
32f960e9 KG	408	ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
	409	0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
	410	clock-frequency = <66666666>;
1b3c5cda KG	411	#interrupt-cells = <1>;
	412	#size-cells = <2>;
	413	#address-cells = <3>;
32f960e9	414	reg = <0xe0008000 0x1000>;
1b3c5cda KG	415	compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
	416	device_type = "pci";
	417
	418	pci_bridge@1c {
32f960e9	419	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
2654d638 AF	420	interrupt-map = <
2654d638 AF	421
1b3c5cda	422	/* IDSEL 0x00 (PrPMC Site) */
32f960e9 KG	423	0000 0x0 0x0 0x1 &mpic 0x0 0x1
	424	0000 0x0 0x0 0x2 &mpic 0x1 0x1
	425	0000 0x0 0x0 0x3 &mpic 0x2 0x1
	426	0000 0x0 0x0 0x4 &mpic 0x3 0x1
1b3c5cda KG	427
1b3c5cda KG	428	/* IDSEL 0x04 (VIA chip) */
32f960e9 KG	429	0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
	430	0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
	431	0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
	432	0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
1b3c5cda KG	433
1b3c5cda KG	434	/* IDSEL 0x05 (8139) */
32f960e9	435	0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
1b3c5cda KG	436
1b3c5cda KG	437	/* IDSEL 0x06 (Slot 6) */
32f960e9 KG	438	0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
	439	0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
	440	0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
	441	0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
1b3c5cda KG	442
1b3c5cda KG	443	/* IDESL 0x07 (Slot 7) */
32f960e9 KG	444	0x3800 0x0 0x0 0x1 &mpic 0x3 0x1
	445	0x3800 0x0 0x0 0x2 &mpic 0x0 0x1
	446	0x3800 0x0 0x0 0x3 &mpic 0x1 0x1
	447	0x3800 0x0 0x0 0x4 &mpic 0x2 0x1>;
1b3c5cda	448
32f960e9	449	reg = <0xe000 0x0 0x0 0x0 0x0>;
2654d638 AF	450	#interrupt-cells = <1>;
	451	#size-cells = <2>;
	452	#address-cells = <3>;
32f960e9 KG	453	ranges = <0x2000000 0x0 0x80000000
	454	0x2000000 0x0 0x80000000
	455	0x0 0x20000000
	456	0x1000000 0x0 0x0
	457	0x1000000 0x0 0x0
	458	0x0 0x80000>;
	459	clock-frequency = <33333333>;
2654d638	460
1b3c5cda KG	461	isa@4 {
	462	device_type = "isa";
	463	#interrupt-cells = <2>;
	464	#size-cells = <1>;
	465	#address-cells = <2>;
32f960e9 KG	466	reg = <0x2000 0x0 0x0 0x0 0x0>;
32f960e9 KG	467	ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
1b3c5cda KG	468	interrupt-parent = <&i8259>;
	469
	470	i8259: interrupt-controller@20 {
	471	interrupt-controller;
	472	device_type = "interrupt-controller";
32f960e9 KG	473	reg = <0x1 0x20 0x2
	474	0x1 0xa0 0x2
	475	0x1 0x4d0 0x2>;
1b3c5cda	476	#address-cells = <0>;
6af01257	477	#interrupt-cells = <2>;
1b3c5cda KG	478	compatible = "chrp,iic";
	479	interrupts = <0 1>;
	480	interrupt-parent = <&mpic>;
6af01257	481	};
2654d638	482
1b3c5cda KG	483	rtc@70 {
1b3c5cda KG	484	compatible = "pnpPNP,b00";
32f960e9	485	reg = <0x1 0x70 0x2>;
1b3c5cda KG	486	};
1b3c5cda KG	487	};
02edff59	488	};
1b3c5cda	489	};
02edff59	490
ea082fa9	491	pci1: pci@e0009000 {
32f960e9	492	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
1b3c5cda KG	493	interrupt-map = <
	494
	495	/* IDSEL 0x15 */
32f960e9 KG	496	0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
	497	0xa800 0x0 0x0 0x2 &mpic 0x1 0x1
	498	0xa800 0x0 0x0 0x3 &mpic 0x2 0x1
	499	0xa800 0x0 0x0 0x4 &mpic 0x3 0x1>;
1b3c5cda KG	500
1b3c5cda KG	501	interrupt-parent = <&mpic>;
32f960e9	502	interrupts = <25 2>;
1b3c5cda	503	bus-range = <0 0>;
32f960e9 KG	504	ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
	505	0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
	506	clock-frequency = <66666666>;
1b3c5cda KG	507	#interrupt-cells = <1>;
	508	#size-cells = <2>;
	509	#address-cells = <3>;
32f960e9	510	reg = <0xe0009000 0x1000>;
1b3c5cda KG	511	compatible = "fsl,mpc8540-pci";
	512	device_type = "pci";
	513	};
02edff59	514
ea082fa9	515	pci2: pcie@e000a000 {
32f960e9	516	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
1b3c5cda KG	517	interrupt-map = <
	518
	519	/* IDSEL 0x0 (PEX) */
32f960e9 KG	520	00000 0x0 0x0 0x1 &mpic 0x0 0x1
	521	00000 0x0 0x0 0x2 &mpic 0x1 0x1
	522	00000 0x0 0x0 0x3 &mpic 0x2 0x1
	523	00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
1b3c5cda KG	524
1b3c5cda KG	525	interrupt-parent = <&mpic>;
32f960e9 KG	526	interrupts = <26 2>;
	527	bus-range = <0 255>;
	528	ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
ad16880d	529	0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
32f960e9	530	clock-frequency = <33333333>;
1b3c5cda KG	531	#interrupt-cells = <1>;
	532	#size-cells = <2>;
	533	#address-cells = <3>;
32f960e9	534	reg = <0xe000a000 0x1000>;
1b3c5cda KG	535	compatible = "fsl,mpc8548-pcie";
	536	device_type = "pci";
	537	pcie@0 {
32f960e9	538	reg = <0x0 0x0 0x0 0x0 0x0>;
02edff59 RZ	539	#size-cells = <2>;
02edff59 RZ	540	#address-cells = <3>;
2654d638	541	device_type = "pci";
32f960e9 KG	542	ranges = <0x2000000 0x0 0xa0000000
	543	0x2000000 0x0 0xa0000000
	544	0x0 0x20000000
2654d638	545
32f960e9 KG	546	0x1000000 0x0 0x0
32f960e9 KG	547	0x1000000 0x0 0x0
ad16880d	548	0x0 0x100000>;
2654d638 AF	549	};
	550	};
	551	};