[deliverable/linux.git] / arch / powerpc / boot / dts / mpc8548cds.dts

/*
 * MPC8548 CDS Device Tree Source
 *
 * Copyright 2006, 2008 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/dts-v1/;

/ {
	model = "MPC8548CDS";
	compatible = "MPC8548CDS", "MPC85xxCDS";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
/*
		ethernet2 = &enet2;
		ethernet3 = &enet3;
*/
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
		pci1 = &pci1;
		pci2 = &pci2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8548@0 {
			device_type = "cpu";
			reg = <0x0>;
			d-cache-line-size = <32>;	// 32 bytes
			i-cache-line-size = <32>;	// 32 bytes
			d-cache-size = <0x8000>;		// L1, 32K
			i-cache-size = <0x8000>;		// L1, 32K
			timebase-frequency = <0>;	//  33 MHz, from uboot
			bus-frequency = <0>;	// 166 MHz
			clock-frequency = <0>;	// 825 MHz, from uboot
			next-level-cache = <&L2>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x8000000>;	// 128M at 0x0
	};

	soc8548@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		compatible = "simple-bus";
		ranges = <0x0 0xe0000000 0x100000>;
		reg = <0xe0000000 0x1000>;	// CCSRBAR
		bus-frequency = <0>;

		memory-controller@2000 {
			compatible = "fsl,8548-memory-controller";
			reg = <0x2000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <18 2>;
		};

		L2: l2-cache-controller@20000 {
			compatible = "fsl,8548-l2-cache-controller";
			reg = <0x20000 0x1000>;
			cache-line-size = <32>;	// 32 bytes
			cache-size = <0x80000>;	// L2, 512K
			interrupt-parent = <&mpic>;
			interrupts = <16 2>;
		};

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		dma@21300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
			reg = <0x21300 0x4>;
			ranges = <0x0 0x21100 0x200>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,mpc8548-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x0 0x80>;
				cell-index = <0>;
				interrupt-parent = <&mpic>;
				interrupts = <20 2>;
			};
			dma-channel@80 {
				compatible = "fsl,mpc8548-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupt-parent = <&mpic>;
				interrupts = <21 2>;
			};
			dma-channel@100 {
				compatible = "fsl,mpc8548-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupt-parent = <&mpic>;
				interrupts = <22 2>;
			};
			dma-channel@180 {
				compatible = "fsl,mpc8548-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x180 0x80>;
				cell-index = <3>;
				interrupt-parent = <&mpic>;
				interrupts = <23 2>;
			};
		};

		mdio@24520 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,gianfar-mdio";
			reg = <0x24520 0x20>;

			phy0: ethernet-phy@0 {
				interrupt-parent = <&mpic>;
				interrupts = <5 1>;
				reg = <0x0>;
				device_type = "ethernet-phy";
			};
			phy1: ethernet-phy@1 {
				interrupt-parent = <&mpic>;
				interrupts = <5 1>;
				reg = <0x1>;
				device_type = "ethernet-phy";
			};
			phy2: ethernet-phy@2 {
				interrupt-parent = <&mpic>;
				interrupts = <5 1>;
				reg = <0x2>;
				device_type = "ethernet-phy";
			};
			phy3: ethernet-phy@3 {
				interrupt-parent = <&mpic>;
				interrupts = <5 1>;
				reg = <0x3>;
				device_type = "ethernet-phy";
			};
		};

		enet0: ethernet@24000 {
			cell-index = <0>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x24000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <29 2 30 2 34 2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy0>;
		};

		enet1: ethernet@25000 {
			cell-index = <1>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x25000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <35 2 36 2 40 2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy1>;
		};

/* eTSEC 3/4 are currently broken
		enet2: ethernet@26000 {
			cell-index = <2>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x26000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <31 2 32 2 33 2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy2>;
		};

		enet3: ethernet@27000 {
			cell-index = <3>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x27000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <37 2 38 2 39 2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy3>;
		};
 */

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4500 0x100>;	// reg base, size
			clock-frequency = <0>;	// should we fill in in uboot?
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4600 0x100>;	// reg base, size
			clock-frequency = <0>;	// should we fill in in uboot?
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		global-utilities@e0000 {	//global utilities reg
			compatible = "fsl,mpc8548-guts";
			reg = <0xe0000 0x1000>;
			fsl,has-rstcr;
		};

		crypto@30000 {
			compatible = "fsl,sec2.1", "fsl,sec2.0";
			reg = <0x30000 0x10000>;
			interrupts = <45 2>;
			interrupt-parent = <&mpic>;
			fsl,num-channels = <4>;
			fsl,channel-fifo-len = <24>;
			fsl,exec-units-mask = <0xfe>;
			fsl,descriptor-types-mask = <0x12b0ebf>;
		};

		mpic: pic@40000 {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x40000 0x40000>;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
		};
	};

	pci0: pci@e0008000 {
		cell-index = <0>;
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <
			/* IDSEL 0x4 (PCIX Slot 2) */
			0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
			0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
			0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
			0x2000 0x0 0x0 0x4 &mpic 0x3 0x1

			/* IDSEL 0x5 (PCIX Slot 3) */
			0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
			0x2800 0x0 0x0 0x2 &mpic 0x2 0x1
			0x2800 0x0 0x0 0x3 &mpic 0x3 0x1
			0x2800 0x0 0x0 0x4 &mpic 0x0 0x1

			/* IDSEL 0x6 (PCIX Slot 4) */
			0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
			0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
			0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
			0x3000 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x8 (PCIX Slot 5) */
			0x4000 0x0 0x0 0x1 &mpic 0x0 0x1
			0x4000 0x0 0x0 0x2 &mpic 0x1 0x1
			0x4000 0x0 0x0 0x3 &mpic 0x2 0x1
			0x4000 0x0 0x0 0x4 &mpic 0x3 0x1

			/* IDSEL 0xC (Tsi310 bridge) */
			0x6000 0x0 0x0 0x1 &mpic 0x0 0x1
			0x6000 0x0 0x0 0x2 &mpic 0x1 0x1
			0x6000 0x0 0x0 0x3 &mpic 0x2 0x1
			0x6000 0x0 0x0 0x4 &mpic 0x3 0x1

			/* IDSEL 0x14 (Slot 2) */
			0xa000 0x0 0x0 0x1 &mpic 0x0 0x1
			0xa000 0x0 0x0 0x2 &mpic 0x1 0x1
			0xa000 0x0 0x0 0x3 &mpic 0x2 0x1
			0xa000 0x0 0x0 0x4 &mpic 0x3 0x1

			/* IDSEL 0x15 (Slot 3) */
			0xa800 0x0 0x0 0x1 &mpic 0x1 0x1
			0xa800 0x0 0x0 0x2 &mpic 0x2 0x1
			0xa800 0x0 0x0 0x3 &mpic 0x3 0x1
			0xa800 0x0 0x0 0x4 &mpic 0x0 0x1

			/* IDSEL 0x16 (Slot 4) */
			0xb000 0x0 0x0 0x1 &mpic 0x2 0x1
			0xb000 0x0 0x0 0x2 &mpic 0x3 0x1
			0xb000 0x0 0x0 0x3 &mpic 0x0 0x1
			0xb000 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x18 (Slot 5) */
			0xc000 0x0 0x0 0x1 &mpic 0x0 0x1
			0xc000 0x0 0x0 0x2 &mpic 0x1 0x1
			0xc000 0x0 0x0 0x3 &mpic 0x2 0x1
			0xc000 0x0 0x0 0x4 &mpic 0x3 0x1

			/* IDSEL 0x1C (Tsi310 bridge PCI primary) */
			0xe000 0x0 0x0 0x1 &mpic 0x0 0x1
			0xe000 0x0 0x0 0x2 &mpic 0x1 0x1
			0xe000 0x0 0x0 0x3 &mpic 0x2 0x1
			0xe000 0x0 0x0 0x4 &mpic 0x3 0x1>;

		interrupt-parent = <&mpic>;
		interrupts = <24 2>;
		bus-range = <0 0>;
		ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
			  0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
		clock-frequency = <66666666>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0008000 0x1000>;
		compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
		device_type = "pci";

		pci_bridge@1c {
			interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
			interrupt-map = <

				/* IDSEL 0x00 (PrPMC Site) */
				0000 0x0 0x0 0x1 &mpic 0x0 0x1
				0000 0x0 0x0 0x2 &mpic 0x1 0x1
				0000 0x0 0x0 0x3 &mpic 0x2 0x1
				0000 0x0 0x0 0x4 &mpic 0x3 0x1

				/* IDSEL 0x04 (VIA chip) */
				0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
				0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
				0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
				0x2000 0x0 0x0 0x4 &mpic 0x3 0x1

				/* IDSEL 0x05 (8139) */
				0x2800 0x0 0x0 0x1 &mpic 0x1 0x1

				/* IDSEL 0x06 (Slot 6) */
				0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
				0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
				0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
				0x3000 0x0 0x0 0x4 &mpic 0x1 0x1

				/* IDESL 0x07 (Slot 7) */
				0x3800 0x0 0x0 0x1 &mpic 0x3 0x1
				0x3800 0x0 0x0 0x2 &mpic 0x0 0x1
				0x3800 0x0 0x0 0x3 &mpic 0x1 0x1
				0x3800 0x0 0x0 0x4 &mpic 0x2 0x1>;

			reg = <0xe000 0x0 0x0 0x0 0x0>;
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			ranges = <0x2000000 0x0 0x80000000
				  0x2000000 0x0 0x80000000
				  0x0 0x20000000
				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x80000>;
			clock-frequency = <33333333>;

			isa@4 {
				device_type = "isa";
				#interrupt-cells = <2>;
				#size-cells = <1>;
				#address-cells = <2>;
				reg = <0x2000 0x0 0x0 0x0 0x0>;
				ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
				interrupt-parent = <&i8259>;

				i8259: interrupt-controller@20 {
					interrupt-controller;
					device_type = "interrupt-controller";
					reg = <0x1 0x20 0x2
					       0x1 0xa0 0x2
					       0x1 0x4d0 0x2>;
					#address-cells = <0>;
					#interrupt-cells = <2>;
					compatible = "chrp,iic";
					interrupts = <0 1>;
					interrupt-parent = <&mpic>;
				};

				rtc@70 {
					compatible = "pnpPNP,b00";
					reg = <0x1 0x70 0x2>;
				};
			};
		};
	};

	pci1: pci@e0009000 {
		cell-index = <1>;
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <

			/* IDSEL 0x15 */
			0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
			0xa800 0x0 0x0 0x2 &mpic 0x1 0x1
			0xa800 0x0 0x0 0x3 &mpic 0x2 0x1
			0xa800 0x0 0x0 0x4 &mpic 0x3 0x1>;

		interrupt-parent = <&mpic>;
		interrupts = <25 2>;
		bus-range = <0 0>;
		ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
			  0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
		clock-frequency = <66666666>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0009000 0x1000>;
		compatible = "fsl,mpc8540-pci";
		device_type = "pci";
	};

	pci2: pcie@e000a000 {
		cell-index = <2>;
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <

			/* IDSEL 0x0 (PEX) */
			00000 0x0 0x0 0x1 &mpic 0x0 0x1
			00000 0x0 0x0 0x2 &mpic 0x1 0x1
			00000 0x0 0x0 0x3 &mpic 0x2 0x1
			00000 0x0 0x0 0x4 &mpic 0x3 0x1>;

		interrupt-parent = <&mpic>;
		interrupts = <26 2>;
		bus-range = <0 255>;
		ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
			  0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
		clock-frequency = <33333333>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe000a000 0x1000>;
		compatible = "fsl,mpc8548-pcie";
		device_type = "pci";
		pcie@0 {
			reg = <0x0 0x0 0x0 0x0 0x0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x2000000 0x0 0xa0000000
				  0x2000000 0x0 0xa0000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x100000>;
		};
	};
};
Commit	Line	Data
2654d638	1	/*
02edff59	2	* MPC8548 CDS Device Tree Source
2654d638	3	*
32f960e9	4	* Copyright 2006, 2008 Freescale Semiconductor Inc.
2654d638 AF	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*/
	11
32f960e9	12	/dts-v1/;
2654d638 AF	13
	14	/ {
	15	model = "MPC8548CDS";
52094879	16	compatible = "MPC8548CDS", "MPC85xxCDS";
2654d638 AF	17	#address-cells = <1>;
2654d638 AF	18	#size-cells = <1>;
2654d638	19
ea082fa9 KG	20	aliases {
	21	ethernet0 = &enet0;
	22	ethernet1 = &enet1;
	23	/*
	24	ethernet2 = &enet2;
	25	ethernet3 = &enet3;
	26	*/
	27	serial0 = &serial0;
	28	serial1 = &serial1;
	29	pci0 = &pci0;
	30	pci1 = &pci1;
	31	pci2 = &pci2;
	32	};
	33
2654d638	34	cpus {
2654d638 AF	35	#address-cells = <1>;
2654d638 AF	36	#size-cells = <0>;
2654d638 AF	37
	38	PowerPC,8548@0 {
	39	device_type = "cpu";
32f960e9 KG	40	reg = <0x0>;
	41	d-cache-line-size = <32>; // 32 bytes
	42	i-cache-line-size = <32>; // 32 bytes
	43	d-cache-size = <0x8000>; // L1, 32K
	44	i-cache-size = <0x8000>; // L1, 32K
2654d638 AF	45	timebase-frequency = <0>; // 33 MHz, from uboot
	46	bus-frequency = <0>; // 166 MHz
	47	clock-frequency = <0>; // 825 MHz, from uboot
c054065b	48	next-level-cache = <&L2>;
2654d638 AF	49	};
	50	};
	51
	52	memory {
	53	device_type = "memory";
32f960e9	54	reg = <0x0 0x8000000>; // 128M at 0x0
2654d638 AF	55	};
	56
	57	soc8548@e0000000 {
	58	#address-cells = <1>;
	59	#size-cells = <1>;
2654d638	60	device_type = "soc";
cf0d19fb	61	compatible = "simple-bus";
32f960e9 KG	62	ranges = <0x0 0xe0000000 0x100000>;
32f960e9 KG	63	reg = <0xe0000000 0x1000>; // CCSRBAR
2654d638 AF	64	bus-frequency = <0>;
2654d638 AF	65
50cf6707 DJ	66	memory-controller@2000 {
50cf6707 DJ	67	compatible = "fsl,8548-memory-controller";
32f960e9	68	reg = <0x2000 0x1000>;
50cf6707	69	interrupt-parent = <&mpic>;
32f960e9	70	interrupts = <18 2>;
50cf6707 DJ	71	};
50cf6707 DJ	72
c054065b	73	L2: l2-cache-controller@20000 {
50cf6707	74	compatible = "fsl,8548-l2-cache-controller";
32f960e9 KG	75	reg = <0x20000 0x1000>;
	76	cache-line-size = <32>; // 32 bytes
	77	cache-size = <0x80000>; // L2, 512K
50cf6707	78	interrupt-parent = <&mpic>;
32f960e9	79	interrupts = <16 2>;
50cf6707 DJ	80	};
50cf6707 DJ	81
2654d638	82	i2c@3000 {
ec9686c4 KG	83	#address-cells = <1>;
	84	#size-cells = <0>;
	85	cell-index = <0>;
2654d638	86	compatible = "fsl-i2c";
32f960e9 KG	87	reg = <0x3000 0x100>;
32f960e9 KG	88	interrupts = <43 2>;
52094879	89	interrupt-parent = <&mpic>;
2654d638 AF	90	dfsrr;
	91	};
	92
ec9686c4 KG	93	i2c@3100 {
	94	#address-cells = <1>;
	95	#size-cells = <0>;
	96	cell-index = <1>;
	97	compatible = "fsl-i2c";
32f960e9 KG	98	reg = <0x3100 0x100>;
32f960e9 KG	99	interrupts = <43 2>;
ec9686c4 KG	100	interrupt-parent = <&mpic>;
	101	dfsrr;
	102	};
	103
dee80553 KG	104	dma@21300 {
	105	#address-cells = <1>;
	106	#size-cells = <1>;
	107	compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
	108	reg = <0x21300 0x4>;
	109	ranges = <0x0 0x21100 0x200>;
	110	cell-index = <0>;
	111	dma-channel@0 {
	112	compatible = "fsl,mpc8548-dma-channel",
	113	"fsl,eloplus-dma-channel";
	114	reg = <0x0 0x80>;
	115	cell-index = <0>;
	116	interrupt-parent = <&mpic>;
	117	interrupts = <20 2>;
	118	};
	119	dma-channel@80 {
	120	compatible = "fsl,mpc8548-dma-channel",
	121	"fsl,eloplus-dma-channel";
	122	reg = <0x80 0x80>;
	123	cell-index = <1>;
	124	interrupt-parent = <&mpic>;
	125	interrupts = <21 2>;
	126	};
	127	dma-channel@100 {
	128	compatible = "fsl,mpc8548-dma-channel",
	129	"fsl,eloplus-dma-channel";
	130	reg = <0x100 0x80>;
	131	cell-index = <2>;
	132	interrupt-parent = <&mpic>;
	133	interrupts = <22 2>;
	134	};
	135	dma-channel@180 {
	136	compatible = "fsl,mpc8548-dma-channel",
	137	"fsl,eloplus-dma-channel";
	138	reg = <0x180 0x80>;
	139	cell-index = <3>;
	140	interrupt-parent = <&mpic>;
	141	interrupts = <23 2>;
	142	};
	143	};
	144
2654d638 AF	145	mdio@24520 {
	146	#address-cells = <1>;
	147	#size-cells = <0>;
e77b28eb	148	compatible = "fsl,gianfar-mdio";
32f960e9	149	reg = <0x24520 0x20>;
e77b28eb	150
52094879 KG	151	phy0: ethernet-phy@0 {
52094879 KG	152	interrupt-parent = <&mpic>;
58fe255f	153	interrupts = <5 1>;
32f960e9	154	reg = <0x0>;
2654d638 AF	155	device_type = "ethernet-phy";
2654d638 AF	156	};
52094879 KG	157	phy1: ethernet-phy@1 {
52094879 KG	158	interrupt-parent = <&mpic>;
58fe255f	159	interrupts = <5 1>;
32f960e9	160	reg = <0x1>;
2654d638 AF	161	device_type = "ethernet-phy";
2654d638 AF	162	};
52094879 KG	163	phy2: ethernet-phy@2 {
52094879 KG	164	interrupt-parent = <&mpic>;
58fe255f	165	interrupts = <5 1>;
32f960e9	166	reg = <0x2>;
2654d638 AF	167	device_type = "ethernet-phy";
2654d638 AF	168	};
52094879 KG	169	phy3: ethernet-phy@3 {
52094879 KG	170	interrupt-parent = <&mpic>;
58fe255f	171	interrupts = <5 1>;
32f960e9	172	reg = <0x3>;
2654d638 AF	173	device_type = "ethernet-phy";
	174	};
	175	};
	176
e77b28eb KG	177	enet0: ethernet@24000 {
e77b28eb KG	178	cell-index = <0>;
2654d638 AF	179	device_type = "network";
	180	model = "eTSEC";
	181	compatible = "gianfar";
32f960e9	182	reg = <0x24000 0x1000>;
eae98266	183	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	184	interrupts = <29 2 30 2 34 2>;
52094879 KG	185	interrupt-parent = <&mpic>;
52094879 KG	186	phy-handle = <&phy0>;
2654d638 AF	187	};
2654d638 AF	188
e77b28eb KG	189	enet1: ethernet@25000 {
e77b28eb KG	190	cell-index = <1>;
2654d638 AF	191	device_type = "network";
	192	model = "eTSEC";
	193	compatible = "gianfar";
32f960e9	194	reg = <0x25000 0x1000>;
eae98266	195	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	196	interrupts = <35 2 36 2 40 2>;
52094879 KG	197	interrupt-parent = <&mpic>;
52094879 KG	198	phy-handle = <&phy1>;
2654d638 AF	199	};
2654d638 AF	200
52094879	201	/* eTSEC 3/4 are currently broken
e77b28eb KG	202	enet2: ethernet@26000 {
e77b28eb KG	203	cell-index = <2>;
2654d638 AF	204	device_type = "network";
	205	model = "eTSEC";
	206	compatible = "gianfar";
32f960e9	207	reg = <0x26000 0x1000>;
eae98266	208	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	209	interrupts = <31 2 32 2 33 2>;
52094879 KG	210	interrupt-parent = <&mpic>;
52094879 KG	211	phy-handle = <&phy2>;
2654d638 AF	212	};
2654d638 AF	213
e77b28eb KG	214	enet3: ethernet@27000 {
e77b28eb KG	215	cell-index = <3>;
2654d638 AF	216	device_type = "network";
	217	model = "eTSEC";
	218	compatible = "gianfar";
32f960e9	219	reg = <0x27000 0x1000>;
eae98266	220	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	221	interrupts = <37 2 38 2 39 2>;
52094879 KG	222	interrupt-parent = <&mpic>;
52094879 KG	223	phy-handle = <&phy3>;
2654d638 AF	224	};
	225	*/
	226
ea082fa9 KG	227	serial0: serial@4500 {
ea082fa9 KG	228	cell-index = <0>;
2654d638 AF	229	device_type = "serial";
2654d638 AF	230	compatible = "ns16550";
32f960e9	231	reg = <0x4500 0x100>; // reg base, size
6af01257	232	clock-frequency = <0>; // should we fill in in uboot?
32f960e9	233	interrupts = <42 2>;
52094879	234	interrupt-parent = <&mpic>;
2654d638 AF	235	};
2654d638 AF	236
ea082fa9 KG	237	serial1: serial@4600 {
ea082fa9 KG	238	cell-index = <1>;
2654d638 AF	239	device_type = "serial";
2654d638 AF	240	compatible = "ns16550";
32f960e9	241	reg = <0x4600 0x100>; // reg base, size
6af01257	242	clock-frequency = <0>; // should we fill in in uboot?
32f960e9	243	interrupts = <42 2>;
52094879	244	interrupt-parent = <&mpic>;
2654d638 AF	245	};
2654d638 AF	246
68fb0d20 RZ	247	global-utilities@e0000 { //global utilities reg
68fb0d20 RZ	248	compatible = "fsl,mpc8548-guts";
32f960e9	249	reg = <0xe0000 0x1000>;
68fb0d20 RZ	250	fsl,has-rstcr;
	251	};
	252
3fd44736 KP	253	crypto@30000 {
	254	compatible = "fsl,sec2.1", "fsl,sec2.0";
	255	reg = <0x30000 0x10000>;
	256	interrupts = <45 2>;
	257	interrupt-parent = <&mpic>;
	258	fsl,num-channels = <4>;
	259	fsl,channel-fifo-len = <24>;
	260	fsl,exec-units-mask = <0xfe>;
	261	fsl,descriptor-types-mask = <0x12b0ebf>;
	262	};
	263
1b3c5cda	264	mpic: pic@40000 {
1b3c5cda KG	265	interrupt-controller;
	266	#address-cells = <0>;
	267	#interrupt-cells = <2>;
32f960e9	268	reg = <0x40000 0x40000>;
1b3c5cda KG	269	compatible = "chrp,open-pic";
1b3c5cda KG	270	device_type = "open-pic";
1b3c5cda KG	271	};
	272	};
	273
ea082fa9 KG	274	pci0: pci@e0008000 {
ea082fa9 KG	275	cell-index = <0>;
32f960e9	276	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
1b3c5cda KG	277	interrupt-map = <
1b3c5cda KG	278	/* IDSEL 0x4 (PCIX Slot 2) */
32f960e9 KG	279	0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
	280	0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
	281	0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
	282	0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
1b3c5cda KG	283
1b3c5cda KG	284	/* IDSEL 0x5 (PCIX Slot 3) */
32f960e9 KG	285	0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
	286	0x2800 0x0 0x0 0x2 &mpic 0x2 0x1
	287	0x2800 0x0 0x0 0x3 &mpic 0x3 0x1
	288	0x2800 0x0 0x0 0x4 &mpic 0x0 0x1
1b3c5cda KG	289
1b3c5cda KG	290	/* IDSEL 0x6 (PCIX Slot 4) */
32f960e9 KG	291	0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
	292	0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
	293	0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
	294	0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
1b3c5cda KG	295
1b3c5cda KG	296	/* IDSEL 0x8 (PCIX Slot 5) */
32f960e9 KG	297	0x4000 0x0 0x0 0x1 &mpic 0x0 0x1
	298	0x4000 0x0 0x0 0x2 &mpic 0x1 0x1
	299	0x4000 0x0 0x0 0x3 &mpic 0x2 0x1
	300	0x4000 0x0 0x0 0x4 &mpic 0x3 0x1
1b3c5cda KG	301
1b3c5cda KG	302	/* IDSEL 0xC (Tsi310 bridge) */
32f960e9 KG	303	0x6000 0x0 0x0 0x1 &mpic 0x0 0x1
	304	0x6000 0x0 0x0 0x2 &mpic 0x1 0x1
	305	0x6000 0x0 0x0 0x3 &mpic 0x2 0x1
	306	0x6000 0x0 0x0 0x4 &mpic 0x3 0x1
1b3c5cda KG	307
1b3c5cda KG	308	/* IDSEL 0x14 (Slot 2) */
32f960e9 KG	309	0xa000 0x0 0x0 0x1 &mpic 0x0 0x1
	310	0xa000 0x0 0x0 0x2 &mpic 0x1 0x1
	311	0xa000 0x0 0x0 0x3 &mpic 0x2 0x1
	312	0xa000 0x0 0x0 0x4 &mpic 0x3 0x1
1b3c5cda KG	313
1b3c5cda KG	314	/* IDSEL 0x15 (Slot 3) */
32f960e9 KG	315	0xa800 0x0 0x0 0x1 &mpic 0x1 0x1
	316	0xa800 0x0 0x0 0x2 &mpic 0x2 0x1
	317	0xa800 0x0 0x0 0x3 &mpic 0x3 0x1
	318	0xa800 0x0 0x0 0x4 &mpic 0x0 0x1
1b3c5cda KG	319
1b3c5cda KG	320	/* IDSEL 0x16 (Slot 4) */
32f960e9 KG	321	0xb000 0x0 0x0 0x1 &mpic 0x2 0x1
	322	0xb000 0x0 0x0 0x2 &mpic 0x3 0x1
	323	0xb000 0x0 0x0 0x3 &mpic 0x0 0x1
	324	0xb000 0x0 0x0 0x4 &mpic 0x1 0x1
1b3c5cda KG	325
1b3c5cda KG	326	/* IDSEL 0x18 (Slot 5) */
32f960e9 KG	327	0xc000 0x0 0x0 0x1 &mpic 0x0 0x1
	328	0xc000 0x0 0x0 0x2 &mpic 0x1 0x1
	329	0xc000 0x0 0x0 0x3 &mpic 0x2 0x1
	330	0xc000 0x0 0x0 0x4 &mpic 0x3 0x1
1b3c5cda KG	331
1b3c5cda KG	332	/* IDSEL 0x1C (Tsi310 bridge PCI primary) */
32f960e9 KG	333	0xe000 0x0 0x0 0x1 &mpic 0x0 0x1
	334	0xe000 0x0 0x0 0x2 &mpic 0x1 0x1
	335	0xe000 0x0 0x0 0x3 &mpic 0x2 0x1
	336	0xe000 0x0 0x0 0x4 &mpic 0x3 0x1>;
1b3c5cda KG	337
1b3c5cda KG	338	interrupt-parent = <&mpic>;
32f960e9	339	interrupts = <24 2>;
1b3c5cda	340	bus-range = <0 0>;
32f960e9 KG	341	ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
	342	0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
	343	clock-frequency = <66666666>;
1b3c5cda KG	344	#interrupt-cells = <1>;
	345	#size-cells = <2>;
	346	#address-cells = <3>;
32f960e9	347	reg = <0xe0008000 0x1000>;
1b3c5cda KG	348	compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
	349	device_type = "pci";
	350
	351	pci_bridge@1c {
32f960e9	352	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
2654d638 AF	353	interrupt-map = <
2654d638 AF	354
1b3c5cda	355	/* IDSEL 0x00 (PrPMC Site) */
32f960e9 KG	356	0000 0x0 0x0 0x1 &mpic 0x0 0x1
	357	0000 0x0 0x0 0x2 &mpic 0x1 0x1
	358	0000 0x0 0x0 0x3 &mpic 0x2 0x1
	359	0000 0x0 0x0 0x4 &mpic 0x3 0x1
1b3c5cda KG	360
1b3c5cda KG	361	/* IDSEL 0x04 (VIA chip) */
32f960e9 KG	362	0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
	363	0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
	364	0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
	365	0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
1b3c5cda KG	366
1b3c5cda KG	367	/* IDSEL 0x05 (8139) */
32f960e9	368	0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
1b3c5cda KG	369
1b3c5cda KG	370	/* IDSEL 0x06 (Slot 6) */
32f960e9 KG	371	0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
	372	0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
	373	0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
	374	0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
1b3c5cda KG	375
1b3c5cda KG	376	/* IDESL 0x07 (Slot 7) */
32f960e9 KG	377	0x3800 0x0 0x0 0x1 &mpic 0x3 0x1
	378	0x3800 0x0 0x0 0x2 &mpic 0x0 0x1
	379	0x3800 0x0 0x0 0x3 &mpic 0x1 0x1
	380	0x3800 0x0 0x0 0x4 &mpic 0x2 0x1>;
1b3c5cda	381
32f960e9	382	reg = <0xe000 0x0 0x0 0x0 0x0>;
2654d638 AF	383	#interrupt-cells = <1>;
	384	#size-cells = <2>;
	385	#address-cells = <3>;
32f960e9 KG	386	ranges = <0x2000000 0x0 0x80000000
	387	0x2000000 0x0 0x80000000
	388	0x0 0x20000000
	389	0x1000000 0x0 0x0
	390	0x1000000 0x0 0x0
	391	0x0 0x80000>;
	392	clock-frequency = <33333333>;
2654d638	393
1b3c5cda KG	394	isa@4 {
	395	device_type = "isa";
	396	#interrupt-cells = <2>;
	397	#size-cells = <1>;
	398	#address-cells = <2>;
32f960e9 KG	399	reg = <0x2000 0x0 0x0 0x0 0x0>;
32f960e9 KG	400	ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
1b3c5cda KG	401	interrupt-parent = <&i8259>;
	402
	403	i8259: interrupt-controller@20 {
	404	interrupt-controller;
	405	device_type = "interrupt-controller";
32f960e9 KG	406	reg = <0x1 0x20 0x2
	407	0x1 0xa0 0x2
	408	0x1 0x4d0 0x2>;
1b3c5cda	409	#address-cells = <0>;
6af01257	410	#interrupt-cells = <2>;
1b3c5cda KG	411	compatible = "chrp,iic";
	412	interrupts = <0 1>;
	413	interrupt-parent = <&mpic>;
6af01257	414	};
2654d638	415
1b3c5cda KG	416	rtc@70 {
1b3c5cda KG	417	compatible = "pnpPNP,b00";
32f960e9	418	reg = <0x1 0x70 0x2>;
1b3c5cda KG	419	};
1b3c5cda KG	420	};
02edff59	421	};
1b3c5cda	422	};
02edff59	423
ea082fa9 KG	424	pci1: pci@e0009000 {
ea082fa9 KG	425	cell-index = <1>;
32f960e9	426	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
1b3c5cda KG	427	interrupt-map = <
	428
	429	/* IDSEL 0x15 */
32f960e9 KG	430	0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
	431	0xa800 0x0 0x0 0x2 &mpic 0x1 0x1
	432	0xa800 0x0 0x0 0x3 &mpic 0x2 0x1
	433	0xa800 0x0 0x0 0x4 &mpic 0x3 0x1>;
1b3c5cda KG	434
1b3c5cda KG	435	interrupt-parent = <&mpic>;
32f960e9	436	interrupts = <25 2>;
1b3c5cda	437	bus-range = <0 0>;
32f960e9 KG	438	ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
	439	0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
	440	clock-frequency = <66666666>;
1b3c5cda KG	441	#interrupt-cells = <1>;
	442	#size-cells = <2>;
	443	#address-cells = <3>;
32f960e9	444	reg = <0xe0009000 0x1000>;
1b3c5cda KG	445	compatible = "fsl,mpc8540-pci";
	446	device_type = "pci";
	447	};
02edff59	448
ea082fa9 KG	449	pci2: pcie@e000a000 {
ea082fa9 KG	450	cell-index = <2>;
32f960e9	451	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
1b3c5cda KG	452	interrupt-map = <
	453
	454	/* IDSEL 0x0 (PEX) */
32f960e9 KG	455	00000 0x0 0x0 0x1 &mpic 0x0 0x1
	456	00000 0x0 0x0 0x2 &mpic 0x1 0x1
	457	00000 0x0 0x0 0x3 &mpic 0x2 0x1
	458	00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
1b3c5cda KG	459
1b3c5cda KG	460	interrupt-parent = <&mpic>;
32f960e9 KG	461	interrupts = <26 2>;
	462	bus-range = <0 255>;
	463	ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
ad16880d	464	0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
32f960e9	465	clock-frequency = <33333333>;
1b3c5cda KG	466	#interrupt-cells = <1>;
	467	#size-cells = <2>;
	468	#address-cells = <3>;
32f960e9	469	reg = <0xe000a000 0x1000>;
1b3c5cda KG	470	compatible = "fsl,mpc8548-pcie";
	471	device_type = "pci";
	472	pcie@0 {
32f960e9	473	reg = <0x0 0x0 0x0 0x0 0x0>;
02edff59 RZ	474	#size-cells = <2>;
02edff59 RZ	475	#address-cells = <3>;
2654d638	476	device_type = "pci";
32f960e9 KG	477	ranges = <0x2000000 0x0 0xa0000000
	478	0x2000000 0x0 0xa0000000
	479	0x0 0x20000000
2654d638	480
32f960e9 KG	481	0x1000000 0x0 0x0
32f960e9 KG	482	0x1000000 0x0 0x0
ad16880d	483	0x0 0x100000>;
2654d638 AF	484	};
	485	};
	486	};