[deliverable/linux.git] / arch / powerpc / boot / dts / mpc8548cds.dtsi

/*
 * MPC8548CDS Device Tree Source stub (no addresses or top-level ranges)
 *
 * Copyright 2012 Freescale Semiconductor Inc.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of Freescale Semiconductor nor the
 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 *
 * ALTERNATIVELY, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") as published by the Free Software
 * Foundation, either version 2 of that License or (at your option) any
 * later version.
 *
 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

&board_lbc {
	nor@0,0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "cfi-flash";
		reg = <0x0 0x0 0x01000000>;
		bank-width = <2>;
		device-width = <2>;

		partition@0 {
			reg = <0x0 0x0b00000>;
			label = "ramdisk-nor";
		};

		partition@300000 {
			reg = <0x0b00000 0x0400000>;
			label = "kernel-nor";
		};

		partition@700000 {
			reg = <0x0f00000 0x060000>;
			label = "dtb-nor";
		};

		partition@760000 {
			reg = <0x0f60000 0x020000>;
			label = "env-nor";
			read-only;
		};

		partition@780000 {
			reg = <0x0f80000 0x080000>;
			label = "u-boot-nor";
			read-only;
		};
	};

	board-control@1,0 {
		compatible = "fsl,mpc8548cds-fpga";
		reg = <0x1 0x0 0x1000>;
	};
};

&board_soc {
	i2c@3000 {
		eeprom@50 {
			compatible = "atmel,24c64";
			reg = <0x50>;
		};

		eeprom@56 {
			compatible = "atmel,24c64";
			reg = <0x56>;
		};

		eeprom@57 {
			compatible = "atmel,24c64";
			reg = <0x57>;
		};
	};

	i2c@3100 {
		eeprom@50 {
			compatible = "atmel,24c64";
			reg = <0x50>;
		};
	};

	enet0: ethernet@24000 {
		tbi-handle = <&tbi0>;
		phy-handle = <&phy0>;
	};

	mdio@24520 {
		phy0: ethernet-phy@0 {
			interrupts = <5 1 0 0>;
			reg = <0x0>;
		};
		phy1: ethernet-phy@1 {
			interrupts = <5 1 0 0>;
			reg = <0x1>;
		};
		phy2: ethernet-phy@2 {
			interrupts = <5 1 0 0>;
			reg = <0x2>;
		};
		phy3: ethernet-phy@3 {
			interrupts = <5 1 0 0>;
			reg = <0x3>;
		};
		tbi0: tbi-phy@11 {
			reg = <0x11>;
			device_type = "tbi-phy";
		};
	};

	enet1: ethernet@25000 {
		tbi-handle = <&tbi1>;
		phy-handle = <&phy1>;
	};

	mdio@25520 {
		tbi1: tbi-phy@11 {
			reg = <0x11>;
			device_type = "tbi-phy";
		};
	};

	enet2: ethernet@26000 {
		tbi-handle = <&tbi2>;
		phy-handle = <&phy2>;
	};

	mdio@26520 {
		tbi2: tbi-phy@11 {
			reg = <0x11>;
			device_type = "tbi-phy";
		};
	};

	enet3: ethernet@27000 {
		tbi-handle = <&tbi3>;
		phy-handle = <&phy3>;
	};

	mdio@27520 {
		tbi3: tbi-phy@11 {
			reg = <0x11>;
			device_type = "tbi-phy";
		};
	};
};

&board_pci0 {
	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
	interrupt-map = <
		/* IDSEL 0x4 (PCIX Slot 2) */
		0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
		0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
		0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
		0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0

		/* IDSEL 0x5 (PCIX Slot 3) */
		0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
		0x2800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
		0x2800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
		0x2800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0

		/* IDSEL 0x6 (PCIX Slot 4) */
		0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
		0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
		0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
		0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0

		/* IDSEL 0x8 (PCIX Slot 5) */
		0x4000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
		0x4000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
		0x4000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
		0x4000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0

		/* IDSEL 0xC (Tsi310 bridge) */
		0x6000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
		0x6000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
		0x6000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
		0x6000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0

		/* IDSEL 0x14 (Slot 2) */
		0xa000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
		0xa000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
		0xa000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
		0xa000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0

		/* IDSEL 0x15 (Slot 3) */
		0xa800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
		0xa800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
		0xa800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
		0xa800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0

		/* IDSEL 0x16 (Slot 4) */
		0xb000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
		0xb000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
		0xb000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
		0xb000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0

		/* IDSEL 0x18 (Slot 5) */
		0xc000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
		0xc000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
		0xc000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
		0xc000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0

		/* IDSEL 0x1C (Tsi310 bridge PCI primary) */
		0xe000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
		0xe000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
		0xe000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
		0xe000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;

	pci_bridge@1c {
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <

			/* IDSEL 0x00 (PrPMC Site) */
			0000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
			0000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
			0000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
			0000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0

			/* IDSEL 0x04 (VIA chip) */
			0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
			0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
			0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
			0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0

			/* IDSEL 0x05 (8139) */
			0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0

			/* IDSEL 0x06 (Slot 6) */
			0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
			0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
			0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
			0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0

			/* IDESL 0x07 (Slot 7) */
			0x3800 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
			0x3800 0x0 0x0 0x2 &mpic 0x0 0x1 0 0
			0x3800 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
			0x3800 0x0 0x0 0x4 &mpic 0x2 0x1 0 0>;

		reg = <0xe000 0x0 0x0 0x0 0x0>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		ranges = <0x2000000 0x0 0x80000000
			  0x2000000 0x0 0x80000000
			  0x0 0x20000000
			  0x1000000 0x0 0x0
			  0x1000000 0x0 0x0
			  0x0 0x80000>;
		clock-frequency = <33333333>;

		isa@4 {
			device_type = "isa";
			#interrupt-cells = <2>;
			#size-cells = <1>;
			#address-cells = <2>;
			reg = <0x2000 0x0 0x0 0x0 0x0>;
			ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
			interrupt-parent = <&i8259>;

			i8259: interrupt-controller@20 {
				interrupt-controller;
				device_type = "interrupt-controller";
				reg = <0x1 0x20 0x2
				       0x1 0xa0 0x2
				       0x1 0x4d0 0x2>;
				#address-cells = <0>;
				#interrupt-cells = <2>;
				compatible = "chrp,iic";
				interrupts = <0 1 0 0>;
				interrupt-parent = <&mpic>;
			};

			rtc@70 {
				compatible = "pnpPNP,b00";
				reg = <0x1 0x70 0x2>;
			};
		};
	};
};
Commit	Line	Data
0d4fdd32 ZC	1	/*
	2	* MPC8548CDS Device Tree Source stub (no addresses or top-level ranges)
	3	*
	4	* Copyright 2012 Freescale Semiconductor Inc.
	5	*
	6	* Redistribution and use in source and binary forms, with or without
	7	* modification, are permitted provided that the following conditions are met:
	8	* * Redistributions of source code must retain the above copyright
	9	* notice, this list of conditions and the following disclaimer.
	10	* * Redistributions in binary form must reproduce the above copyright
	11	* notice, this list of conditions and the following disclaimer in the
	12	* documentation and/or other materials provided with the distribution.
	13	* * Neither the name of Freescale Semiconductor nor the
	14	* names of its contributors may be used to endorse or promote products
	15	* derived from this software without specific prior written permission.
	16	*
	17	*
	18	* ALTERNATIVELY, this software may be distributed under the terms of the
	19	* GNU General Public License ("GPL") as published by the Free Software
	20	* Foundation, either version 2 of that License or (at your option) any
	21	* later version.
	22	*
	23	* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
	24	* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	25	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	26	* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
	27	* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	28	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	29	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	30	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	31	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	32	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	33	*/
	34
	35	&board_lbc {
	36	nor@0,0 {
	37	#address-cells = <1>;
	38	#size-cells = <1>;
	39	compatible = "cfi-flash";
	40	reg = <0x0 0x0 0x01000000>;
	41	bank-width = <2>;
	42	device-width = <2>;
	43
	44	partition@0 {
	45	reg = <0x0 0x0b00000>;
	46	label = "ramdisk-nor";
	47	};
	48
	49	partition@300000 {
	50	reg = <0x0b00000 0x0400000>;
	51	label = "kernel-nor";
	52	};
	53
	54	partition@700000 {
	55	reg = <0x0f00000 0x060000>;
	56	label = "dtb-nor";
	57	};
	58
	59	partition@760000 {
	60	reg = <0x0f60000 0x020000>;
	61	label = "env-nor";
	62	read-only;
	63	};
	64
65	partition@780000 {
66	reg = <0x0f80000 0x080000>;
67	label = "u-boot-nor";
68	read-only;
69	};
70	};
71
72	board-control@1,0 {
73	compatible = "fsl,mpc8548cds-fpga";
74	reg = <0x1 0x0 0x1000>;
75	};
76	};
77
78	&board_soc {
79	i2c@3000 {
80	eeprom@50 {
81	compatible = "atmel,24c64";
82	reg = <0x50>;
83	};
84
85	eeprom@56 {
86	compatible = "atmel,24c64";
87	reg = <0x56>;
88	};
89
90	eeprom@57 {
91	compatible = "atmel,24c64";
92	reg = <0x57>;
93	};
94	};
95
96	i2c@3100 {
97	eeprom@50 {
98	compatible = "atmel,24c64";
99	reg = <0x50>;
100	};
101	};
102
103	enet0: ethernet@24000 {
104	tbi-handle = <&tbi0>;
105	phy-handle = <&phy0>;
106	};
107
108	mdio@24520 {
109	phy0: ethernet-phy@0 {
110	interrupts = <5 1 0 0>;
111	reg = <0x0>;
0d4fdd32 ZC	112	};
	113	phy1: ethernet-phy@1 {
	114	interrupts = <5 1 0 0>;
	115	reg = <0x1>;
0d4fdd32 ZC	116	};
	117	phy2: ethernet-phy@2 {
	118	interrupts = <5 1 0 0>;
	119	reg = <0x2>;
0d4fdd32 ZC	120	};
	121	phy3: ethernet-phy@3 {
	122	interrupts = <5 1 0 0>;
	123	reg = <0x3>;
0d4fdd32 ZC	124	};
	125	tbi0: tbi-phy@11 {
	126	reg = <0x11>;
	127	device_type = "tbi-phy";
	128	};
	129	};
	130
	131	enet1: ethernet@25000 {
	132	tbi-handle = <&tbi1>;
	133	phy-handle = <&phy1>;
	134	};
	135
	136	mdio@25520 {
	137	tbi1: tbi-phy@11 {
	138	reg = <0x11>;
	139	device_type = "tbi-phy";
	140	};
	141	};
	142
	143	enet2: ethernet@26000 {
	144	tbi-handle = <&tbi2>;
	145	phy-handle = <&phy2>;
	146	};
	147
	148	mdio@26520 {
	149	tbi2: tbi-phy@11 {
	150	reg = <0x11>;
	151	device_type = "tbi-phy";
	152	};
	153	};
	154
	155	enet3: ethernet@27000 {
	156	tbi-handle = <&tbi3>;
	157	phy-handle = <&phy3>;
	158	};
	159
	160	mdio@27520 {
	161	tbi3: tbi-phy@11 {
	162	reg = <0x11>;
	163	device_type = "tbi-phy";
	164	};
	165	};
	166	};
	167
	168	&board_pci0 {
	169	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
	170	interrupt-map = <
	171	/* IDSEL 0x4 (PCIX Slot 2) */
	172	0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
	173	0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
	174	0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
	175	0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
	176
	177	/* IDSEL 0x5 (PCIX Slot 3) */
	178	0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
	179	0x2800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
	180	0x2800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
	181	0x2800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
	182
	183	/* IDSEL 0x6 (PCIX Slot 4) */
	184	0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
	185	0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
	186	0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
	187	0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
188
189	/* IDSEL 0x8 (PCIX Slot 5) */
190	0x4000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
191	0x4000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
192	0x4000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
193	0x4000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
194
195	/* IDSEL 0xC (Tsi310 bridge) */
196	0x6000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
197	0x6000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
198	0x6000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
199	0x6000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
200
201	/* IDSEL 0x14 (Slot 2) */
202	0xa000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
203	0xa000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
204	0xa000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
205	0xa000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
206
207	/* IDSEL 0x15 (Slot 3) */
208	0xa800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
209	0xa800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
210	0xa800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
211	0xa800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
212
213	/* IDSEL 0x16 (Slot 4) */
214	0xb000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
215	0xb000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
216	0xb000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
217	0xb000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
218
219	/* IDSEL 0x18 (Slot 5) */
220	0xc000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
221	0xc000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
222	0xc000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
223	0xc000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
224
225	/* IDSEL 0x1C (Tsi310 bridge PCI primary) */
226	0xe000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
227	0xe000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
228	0xe000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
229	0xe000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
230
231	pci_bridge@1c {
232	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
233	interrupt-map = <
234
235	/* IDSEL 0x00 (PrPMC Site) */
236	0000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
237	0000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
238	0000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
239	0000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
240
241	/* IDSEL 0x04 (VIA chip) */
242	0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
243	0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
244	0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
245	0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
246
247	/* IDSEL 0x05 (8139) */
248	0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
249
250	/* IDSEL 0x06 (Slot 6) */
251	0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
252	0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
253	0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
254	0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
255
256	/* IDESL 0x07 (Slot 7) */
257	0x3800 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
258	0x3800 0x0 0x0 0x2 &mpic 0x0 0x1 0 0
259	0x3800 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
260	0x3800 0x0 0x0 0x4 &mpic 0x2 0x1 0 0>;
261
262	reg = <0xe000 0x0 0x0 0x0 0x0>;
263	#interrupt-cells = <1>;
264	#size-cells = <2>;
265	#address-cells = <3>;
266	ranges = <0x2000000 0x0 0x80000000
267	0x2000000 0x0 0x80000000
268	0x0 0x20000000
269	0x1000000 0x0 0x0
270	0x1000000 0x0 0x0
271	0x0 0x80000>;
272	clock-frequency = <33333333>;
273
274	isa@4 {
275	device_type = "isa";
276	#interrupt-cells = <2>;
277	#size-cells = <1>;
278	#address-cells = <2>;
279	reg = <0x2000 0x0 0x0 0x0 0x0>;
280	ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
281	interrupt-parent = <&i8259>;
282
283	i8259: interrupt-controller@20 {
284	interrupt-controller;
285	device_type = "interrupt-controller";
286	reg = <0x1 0x20 0x2
287	0x1 0xa0 0x2
288	0x1 0x4d0 0x2>;
289	#address-cells = <0>;
290	#interrupt-cells = <2>;
291	compatible = "chrp,iic";
292	interrupts = <0 1 0 0>;
293	interrupt-parent = <&mpic>;
294	};
295
296	rtc@70 {
297	compatible = "pnpPNP,b00";
298	reg = <0x1 0x70 0x2>;
299	};
300	};
301	};
302	};