[deliverable/linux.git] / arch / powerpc / boot / dts / mpc8555cds.dts

/*
 * MPC8555 CDS Device Tree Source
 *
 * Copyright 2006, 2008 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/dts-v1/;

/include/ "fsl/e500v2_power_isa.dtsi"

/ {
	model = "MPC8555CDS";
	compatible = "MPC8555CDS", "MPC85xxCDS";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
		pci1 = &pci1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8555@0 {
			device_type = "cpu";
			reg = <0x0>;
			d-cache-line-size = <32>;	// 32 bytes
			i-cache-line-size = <32>;	// 32 bytes
			d-cache-size = <0x8000>;		// L1, 32K
			i-cache-size = <0x8000>;		// L1, 32K
			timebase-frequency = <0>;	//  33 MHz, from uboot
			bus-frequency = <0>;	// 166 MHz
			clock-frequency = <0>;	// 825 MHz, from uboot
			next-level-cache = <&L2>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x8000000>;	// 128M at 0x0
	};

	soc8555@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		compatible = "simple-bus";
		ranges = <0x0 0xe0000000 0x100000>;
		bus-frequency = <0>;

		ecm-law@0 {
			compatible = "fsl,ecm-law";
			reg = <0x0 0x1000>;
			fsl,num-laws = <8>;
		};

		ecm@1000 {
			compatible = "fsl,mpc8555-ecm", "fsl,ecm";
			reg = <0x1000 0x1000>;
			interrupts = <17 2>;
			interrupt-parent = <&mpic>;
		};

		memory-controller@2000 {
			compatible = "fsl,mpc8555-memory-controller";
			reg = <0x2000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <18 2>;
		};

		L2: l2-cache-controller@20000 {
			compatible = "fsl,mpc8555-l2-cache-controller";
			reg = <0x20000 0x1000>;
			cache-line-size = <32>;	// 32 bytes
			cache-size = <0x40000>;	// L2, 256K
			interrupt-parent = <&mpic>;
			interrupts = <16 2>;
		};

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		dma@21300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma";
			reg = <0x21300 0x4>;
			ranges = <0x0 0x21100 0x200>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,mpc8555-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x0 0x80>;
				cell-index = <0>;
				interrupt-parent = <&mpic>;
				interrupts = <20 2>;
			};
			dma-channel@80 {
				compatible = "fsl,mpc8555-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupt-parent = <&mpic>;
				interrupts = <21 2>;
			};
			dma-channel@100 {
				compatible = "fsl,mpc8555-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupt-parent = <&mpic>;
				interrupts = <22 2>;
			};
			dma-channel@180 {
				compatible = "fsl,mpc8555-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x180 0x80>;
				cell-index = <3>;
				interrupt-parent = <&mpic>;
				interrupts = <23 2>;
			};
		};

		enet0: ethernet@24000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <0>;
			device_type = "network";
			model = "TSEC";
			compatible = "gianfar";
			reg = <0x24000 0x1000>;
			ranges = <0x0 0x24000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <29 2 30 2 34 2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi0>;
			phy-handle = <&phy0>;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-mdio";
				reg = <0x520 0x20>;

				phy0: ethernet-phy@0 {
					interrupt-parent = <&mpic>;
					interrupts = <5 1>;
					reg = <0x0>;
				};
				phy1: ethernet-phy@1 {
					interrupt-parent = <&mpic>;
					interrupts = <5 1>;
					reg = <0x1>;
				};
				tbi0: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		enet1: ethernet@25000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <1>;
			device_type = "network";
			model = "TSEC";
			compatible = "gianfar";
			reg = <0x25000 0x1000>;
			ranges = <0x0 0x25000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <35 2 36 2 40 2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi1>;
			phy-handle = <&phy1>;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-tbi";
				reg = <0x520 0x20>;

				tbi1: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "fsl,ns16550", "ns16550";
			reg = <0x4500 0x100>; 	// reg base, size
			clock-frequency = <0>; 	// should we fill in in uboot?
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "fsl,ns16550", "ns16550";
			reg = <0x4600 0x100>;	// reg base, size
			clock-frequency = <0>; 	// should we fill in in uboot?
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		crypto@30000 {
			compatible = "fsl,sec2.0";
			reg = <0x30000 0x10000>;
			interrupts = <45 2>;
			interrupt-parent = <&mpic>;
			fsl,num-channels = <4>;
			fsl,channel-fifo-len = <24>;
			fsl,exec-units-mask = <0x7e>;
			fsl,descriptor-types-mask = <0x01010ebf>;
		};

		mpic: pic@40000 {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x40000 0x40000>;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
		};

		cpm@919c0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
			reg = <0x919c0 0x30>;
			ranges;

			muram@80000 {
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0x80000 0x10000>;

				data@0 {
					compatible = "fsl,cpm-muram-data";
					reg = <0x0 0x2000 0x9000 0x1000>;
				};
			};

			brg@919f0 {
				compatible = "fsl,mpc8555-brg",
				             "fsl,cpm2-brg",
				             "fsl,cpm-brg";
				reg = <0x919f0 0x10 0x915f0 0x10>;
			};

			cpmpic: pic@90c00 {
				interrupt-controller;
				#address-cells = <0>;
				#interrupt-cells = <2>;
				interrupts = <46 2>;
				interrupt-parent = <&mpic>;
				reg = <0x90c00 0x80>;
				compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
			};
		};
	};

	pci0: pci@e0008000 {
		interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
		interrupt-map = <

			/* IDSEL 0x10 */
			0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
			0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
			0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
			0x8000 0x0 0x0 0x4 &mpic 0x3 0x1

			/* IDSEL 0x11 */
			0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
			0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
			0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
			0x8800 0x0 0x0 0x4 &mpic 0x3 0x1

			/* IDSEL 0x12 (Slot 1) */
			0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
			0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
			0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
			0x9000 0x0 0x0 0x4 &mpic 0x3 0x1

			/* IDSEL 0x13 (Slot 2) */
			0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
			0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
			0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
			0x9800 0x0 0x0 0x4 &mpic 0x0 0x1

			/* IDSEL 0x14 (Slot 3) */
			0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
			0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
			0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
			0xa000 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x15 (Slot 4) */
			0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
			0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
			0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
			0xa800 0x0 0x0 0x4 &mpic 0x2 0x1

			/* Bus 1 (Tundra Bridge) */
			/* IDSEL 0x12 (ISA bridge) */
			0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
			0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
			0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
			0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
		interrupt-parent = <&mpic>;
		interrupts = <24 2>;
		bus-range = <0 0>;
		ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
			  0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
		clock-frequency = <66666666>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0008000 0x1000>;
		compatible = "fsl,mpc8540-pci";
		device_type = "pci";

		i8259@19000 {
			interrupt-controller;
			device_type = "interrupt-controller";
			reg = <0x19000 0x0 0x0 0x0 0x1>;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			compatible = "chrp,iic";
			interrupts = <1>;
			interrupt-parent = <&pci0>;
		};
	};

	pci1: pci@e0009000 {
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <

			/* IDSEL 0x15 */
			0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
			0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
			0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
			0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
		interrupt-parent = <&mpic>;
		interrupts = <25 2>;
		bus-range = <0 0>;
		ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
			  0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
		clock-frequency = <66666666>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0009000 0x1000>;
		compatible = "fsl,mpc8540-pci";
		device_type = "pci";
	};
};
Commit	Line	Data
2654d638 AF	1	/*
	2	* MPC8555 CDS Device Tree Source
	3	*
32f960e9	4	* Copyright 2006, 2008 Freescale Semiconductor Inc.
2654d638 AF	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*/
	11
32f960e9	12	/dts-v1/;
2654d638	13
2eb28006 OY	14	/include/ "fsl/e500v2_power_isa.dtsi"
2eb28006 OY	15
2654d638 AF	16	/ {
2654d638 AF	17	model = "MPC8555CDS";
52094879	18	compatible = "MPC8555CDS", "MPC85xxCDS";
2654d638 AF	19	#address-cells = <1>;
2654d638 AF	20	#size-cells = <1>;
2654d638	21
ea082fa9 KG	22	aliases {
	23	ethernet0 = &enet0;
	24	ethernet1 = &enet1;
	25	serial0 = &serial0;
	26	serial1 = &serial1;
	27	pci0 = &pci0;
	28	pci1 = &pci1;
	29	};
	30
2654d638	31	cpus {
2654d638 AF	32	#address-cells = <1>;
2654d638 AF	33	#size-cells = <0>;
2654d638 AF	34
	35	PowerPC,8555@0 {
	36	device_type = "cpu";
32f960e9 KG	37	reg = <0x0>;
	38	d-cache-line-size = <32>; // 32 bytes
	39	i-cache-line-size = <32>; // 32 bytes
	40	d-cache-size = <0x8000>; // L1, 32K
	41	i-cache-size = <0x8000>; // L1, 32K
2654d638 AF	42	timebase-frequency = <0>; // 33 MHz, from uboot
	43	bus-frequency = <0>; // 166 MHz
	44	clock-frequency = <0>; // 825 MHz, from uboot
c054065b	45	next-level-cache = <&L2>;
2654d638 AF	46	};
	47	};
	48
	49	memory {
	50	device_type = "memory";
32f960e9	51	reg = <0x0 0x8000000>; // 128M at 0x0
2654d638 AF	52	};
	53
	54	soc8555@e0000000 {
	55	#address-cells = <1>;
	56	#size-cells = <1>;
2654d638	57	device_type = "soc";
cf0d19fb	58	compatible = "simple-bus";
32f960e9	59	ranges = <0x0 0xe0000000 0x100000>;
2654d638 AF	60	bus-frequency = <0>;
2654d638 AF	61
e1a22897 KG	62	ecm-law@0 {
	63	compatible = "fsl,ecm-law";
	64	reg = <0x0 0x1000>;
	65	fsl,num-laws = <8>;
	66	};
	67
	68	ecm@1000 {
	69	compatible = "fsl,mpc8555-ecm", "fsl,ecm";
	70	reg = <0x1000 0x1000>;
	71	interrupts = <17 2>;
	72	interrupt-parent = <&mpic>;
	73	};
	74
4da421d6	75	memory-controller@2000 {
8a4ab218	76	compatible = "fsl,mpc8555-memory-controller";
32f960e9	77	reg = <0x2000 0x1000>;
4da421d6	78	interrupt-parent = <&mpic>;
32f960e9	79	interrupts = <18 2>;
4da421d6 KG	80	};
4da421d6 KG	81
c054065b	82	L2: l2-cache-controller@20000 {
8a4ab218	83	compatible = "fsl,mpc8555-l2-cache-controller";
32f960e9 KG	84	reg = <0x20000 0x1000>;
	85	cache-line-size = <32>; // 32 bytes
	86	cache-size = <0x40000>; // L2, 256K
4da421d6	87	interrupt-parent = <&mpic>;
32f960e9	88	interrupts = <16 2>;
4da421d6 KG	89	};
4da421d6 KG	90
2654d638	91	i2c@3000 {
ec9686c4 KG	92	#address-cells = <1>;
	93	#size-cells = <0>;
	94	cell-index = <0>;
2654d638	95	compatible = "fsl-i2c";
32f960e9 KG	96	reg = <0x3000 0x100>;
32f960e9 KG	97	interrupts = <43 2>;
52094879	98	interrupt-parent = <&mpic>;
2654d638 AF	99	dfsrr;
	100	};
	101
dee80553 KG	102	dma@21300 {
	103	#address-cells = <1>;
	104	#size-cells = <1>;
	105	compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma";
	106	reg = <0x21300 0x4>;
	107	ranges = <0x0 0x21100 0x200>;
	108	cell-index = <0>;
	109	dma-channel@0 {
	110	compatible = "fsl,mpc8555-dma-channel",
	111	"fsl,eloplus-dma-channel";
	112	reg = <0x0 0x80>;
	113	cell-index = <0>;
	114	interrupt-parent = <&mpic>;
	115	interrupts = <20 2>;
	116	};
	117	dma-channel@80 {
	118	compatible = "fsl,mpc8555-dma-channel",
	119	"fsl,eloplus-dma-channel";
	120	reg = <0x80 0x80>;
	121	cell-index = <1>;
	122	interrupt-parent = <&mpic>;
	123	interrupts = <21 2>;
	124	};
	125	dma-channel@100 {
	126	compatible = "fsl,mpc8555-dma-channel",
	127	"fsl,eloplus-dma-channel";
	128	reg = <0x100 0x80>;
	129	cell-index = <2>;
	130	interrupt-parent = <&mpic>;
	131	interrupts = <22 2>;
	132	};
	133	dma-channel@180 {
	134	compatible = "fsl,mpc8555-dma-channel",
	135	"fsl,eloplus-dma-channel";
	136	reg = <0x180 0x80>;
	137	cell-index = <3>;
	138	interrupt-parent = <&mpic>;
	139	interrupts = <23 2>;
	140	};
	141	};
	142
e77b28eb	143	enet0: ethernet@24000 {
84ba4a58 AV	144	#address-cells = <1>;
84ba4a58 AV	145	#size-cells = <1>;
e77b28eb	146	cell-index = <0>;
2654d638 AF	147	device_type = "network";
	148	model = "TSEC";
	149	compatible = "gianfar";
32f960e9	150	reg = <0x24000 0x1000>;
84ba4a58	151	ranges = <0x0 0x24000 0x1000>;
eae98266	152	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	153	interrupts = <29 2 30 2 34 2>;
52094879	154	interrupt-parent = <&mpic>;
b31a1d8b	155	tbi-handle = <&tbi0>;
52094879	156	phy-handle = <&phy0>;
84ba4a58 AV	157
	158	mdio@520 {
	159	#address-cells = <1>;
	160	#size-cells = <0>;
	161	compatible = "fsl,gianfar-mdio";
	162	reg = <0x520 0x20>;
	163
	164	phy0: ethernet-phy@0 {
	165	interrupt-parent = <&mpic>;
	166	interrupts = <5 1>;
	167	reg = <0x0>;
84ba4a58 AV	168	};
	169	phy1: ethernet-phy@1 {
	170	interrupt-parent = <&mpic>;
	171	interrupts = <5 1>;
	172	reg = <0x1>;
84ba4a58 AV	173	};
	174	tbi0: tbi-phy@11 {
	175	reg = <0x11>;
	176	device_type = "tbi-phy";
	177	};
	178	};
2654d638 AF	179	};
2654d638 AF	180
e77b28eb	181	enet1: ethernet@25000 {
84ba4a58 AV	182	#address-cells = <1>;
84ba4a58 AV	183	#size-cells = <1>;
e77b28eb	184	cell-index = <1>;
2654d638 AF	185	device_type = "network";
	186	model = "TSEC";
	187	compatible = "gianfar";
32f960e9	188	reg = <0x25000 0x1000>;
84ba4a58	189	ranges = <0x0 0x25000 0x1000>;
eae98266	190	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	191	interrupts = <35 2 36 2 40 2>;
52094879	192	interrupt-parent = <&mpic>;
b31a1d8b	193	tbi-handle = <&tbi1>;
52094879	194	phy-handle = <&phy1>;
84ba4a58 AV	195
	196	mdio@520 {
	197	#address-cells = <1>;
	198	#size-cells = <0>;
	199	compatible = "fsl,gianfar-tbi";
	200	reg = <0x520 0x20>;
	201
	202	tbi1: tbi-phy@11 {
	203	reg = <0x11>;
	204	device_type = "tbi-phy";
	205	};
	206	};
2654d638 AF	207	};
2654d638 AF	208
ea082fa9 KG	209	serial0: serial@4500 {
ea082fa9 KG	210	cell-index = <0>;
2654d638	211	device_type = "serial";
f706bed1	212	compatible = "fsl,ns16550", "ns16550";
32f960e9	213	reg = <0x4500 0x100>; // reg base, size
2654d638	214	clock-frequency = <0>; // should we fill in in uboot?
32f960e9	215	interrupts = <42 2>;
52094879	216	interrupt-parent = <&mpic>;
2654d638 AF	217	};
2654d638 AF	218
ea082fa9 KG	219	serial1: serial@4600 {
ea082fa9 KG	220	cell-index = <1>;
2654d638	221	device_type = "serial";
f706bed1	222	compatible = "fsl,ns16550", "ns16550";
32f960e9	223	reg = <0x4600 0x100>; // reg base, size
2654d638	224	clock-frequency = <0>; // should we fill in in uboot?
32f960e9	225	interrupts = <42 2>;
52094879	226	interrupt-parent = <&mpic>;
2654d638 AF	227	};
2654d638 AF	228
3fd44736 KP	229	crypto@30000 {
	230	compatible = "fsl,sec2.0";
	231	reg = <0x30000 0x10000>;
	232	interrupts = <45 2>;
	233	interrupt-parent = <&mpic>;
	234	fsl,num-channels = <4>;
	235	fsl,channel-fifo-len = <24>;
	236	fsl,exec-units-mask = <0x7e>;
	237	fsl,descriptor-types-mask = <0x01010ebf>;
	238	};
	239
52094879	240	mpic: pic@40000 {
2654d638 AF	241	interrupt-controller;
	242	#address-cells = <0>;
	243	#interrupt-cells = <2>;
32f960e9	244	reg = <0x40000 0x40000>;
2654d638 AF	245	compatible = "chrp,open-pic";
2654d638 AF	246	device_type = "open-pic";
2654d638	247	};
ab9683ca SW	248
	249	cpm@919c0 {
	250	#address-cells = <1>;
	251	#size-cells = <1>;
	252	compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
32f960e9	253	reg = <0x919c0 0x30>;
ab9683ca SW	254	ranges;
	255
	256	muram@80000 {
	257	#address-cells = <1>;
	258	#size-cells = <1>;
32f960e9	259	ranges = <0x0 0x80000 0x10000>;
ab9683ca SW	260
	261	data@0 {
	262	compatible = "fsl,cpm-muram-data";
32f960e9	263	reg = <0x0 0x2000 0x9000 0x1000>;
ab9683ca SW	264	};
	265	};
	266
	267	brg@919f0 {
	268	compatible = "fsl,mpc8555-brg",
	269	"fsl,cpm2-brg",
	270	"fsl,cpm-brg";
32f960e9	271	reg = <0x919f0 0x10 0x915f0 0x10>;
ab9683ca SW	272	};
	273
	274	cpmpic: pic@90c00 {
	275	interrupt-controller;
	276	#address-cells = <0>;
	277	#interrupt-cells = <2>;
32f960e9	278	interrupts = <46 2>;
ab9683ca	279	interrupt-parent = <&mpic>;
32f960e9	280	reg = <0x90c00 0x80>;
ab9683ca SW	281	compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
	282	};
	283	};
2654d638	284	};
1b3c5cda	285
ea082fa9	286	pci0: pci@e0008000 {
32f960e9	287	interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
1b3c5cda KG	288	interrupt-map = <
	289
	290	/* IDSEL 0x10 */
32f960e9 KG	291	0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
	292	0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
	293	0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
	294	0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
1b3c5cda KG	295
1b3c5cda KG	296	/* IDSEL 0x11 */
32f960e9 KG	297	0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
	298	0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
	299	0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
	300	0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
1b3c5cda KG	301
1b3c5cda KG	302	/* IDSEL 0x12 (Slot 1) */
32f960e9 KG	303	0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
	304	0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
	305	0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
	306	0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
1b3c5cda KG	307
1b3c5cda KG	308	/* IDSEL 0x13 (Slot 2) */
32f960e9 KG	309	0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
	310	0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
	311	0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
	312	0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
1b3c5cda KG	313
1b3c5cda KG	314	/* IDSEL 0x14 (Slot 3) */
32f960e9 KG	315	0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
	316	0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
	317	0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
	318	0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
1b3c5cda KG	319
1b3c5cda KG	320	/* IDSEL 0x15 (Slot 4) */
32f960e9 KG	321	0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
	322	0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
	323	0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
	324	0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
1b3c5cda KG	325
	326	/* Bus 1 (Tundra Bridge) */
	327	/* IDSEL 0x12 (ISA bridge) */
32f960e9 KG	328	0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
	329	0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
	330	0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
	331	0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
1b3c5cda	332	interrupt-parent = <&mpic>;
32f960e9	333	interrupts = <24 2>;
1b3c5cda	334	bus-range = <0 0>;
32f960e9 KG	335	ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
	336	0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
	337	clock-frequency = <66666666>;
1b3c5cda KG	338	#interrupt-cells = <1>;
	339	#size-cells = <2>;
	340	#address-cells = <3>;
32f960e9	341	reg = <0xe0008000 0x1000>;
1b3c5cda KG	342	compatible = "fsl,mpc8540-pci";
	343	device_type = "pci";
	344
	345	i8259@19000 {
	346	interrupt-controller;
	347	device_type = "interrupt-controller";
32f960e9	348	reg = <0x19000 0x0 0x0 0x0 0x1>;
1b3c5cda KG	349	#address-cells = <0>;
	350	#interrupt-cells = <2>;
	351	compatible = "chrp,iic";
	352	interrupts = <1>;
ea082fa9	353	interrupt-parent = <&pci0>;
1b3c5cda KG	354	};
	355	};
	356
ea082fa9	357	pci1: pci@e0009000 {
32f960e9	358	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
1b3c5cda KG	359	interrupt-map = <
	360
	361	/* IDSEL 0x15 */
32f960e9 KG	362	0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
	363	0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
	364	0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
	365	0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
1b3c5cda	366	interrupt-parent = <&mpic>;
32f960e9	367	interrupts = <25 2>;
1b3c5cda	368	bus-range = <0 0>;
32f960e9 KG	369	ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
	370	0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
	371	clock-frequency = <66666666>;
1b3c5cda KG	372	#interrupt-cells = <1>;
	373	#size-cells = <2>;
	374	#address-cells = <3>;
32f960e9	375	reg = <0xe0009000 0x1000>;
1b3c5cda KG	376	compatible = "fsl,mpc8540-pci";
	377	device_type = "pci";
	378	};
2654d638	379	};