[deliverable/linux.git] / arch / powerpc / boot / dts / mpc8572ds.dts

/*
 * MPC8572 DS Device Tree Source
 *
 * Copyright 2007, 2008 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/dts-v1/;
/ {
	model = "fsl,MPC8572DS";
	compatible = "fsl,MPC8572DS";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		ethernet2 = &enet2;
		ethernet3 = &enet3;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
		pci1 = &pci1;
		pci2 = &pci2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8572@0 {
			device_type = "cpu";
			reg = <0x0>;
			d-cache-line-size = <32>;	// 32 bytes
			i-cache-line-size = <32>;	// 32 bytes
			d-cache-size = <0x8000>;		// L1, 32K
			i-cache-size = <0x8000>;		// L1, 32K
			timebase-frequency = <0>;
			bus-frequency = <0>;
			clock-frequency = <0>;
		};

		PowerPC,8572@1 {
			device_type = "cpu";
			reg = <0x1>;
			d-cache-line-size = <32>;	// 32 bytes
			i-cache-line-size = <32>;	// 32 bytes
			d-cache-size = <0x8000>;		// L1, 32K
			i-cache-size = <0x8000>;		// L1, 32K
			timebase-frequency = <0>;
			bus-frequency = <0>;
			clock-frequency = <0>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x0>;	// Filled by U-Boot
	};

	soc8572@ffe00000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		ranges = <0x0 0xffe00000 0x100000>;
		reg = <0xffe00000 0x1000>;	// CCSRBAR & soc regs, remove once parse code for immrbase fixed
		bus-frequency = <0>;		// Filled out by uboot.

		memory-controller@2000 {
			compatible = "fsl,mpc8572-memory-controller";
			reg = <0x2000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <18 2>;
		};

		memory-controller@6000 {
			compatible = "fsl,mpc8572-memory-controller";
			reg = <0x6000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <18 2>;
		};

		l2-cache-controller@20000 {
			compatible = "fsl,mpc8572-l2-cache-controller";
			reg = <0x20000 0x1000>;
			cache-line-size = <32>;	// 32 bytes
			cache-size = <0x80000>;	// L2, 512K
			interrupt-parent = <&mpic>;
			interrupts = <16 2>;
		};

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		mdio@24520 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,gianfar-mdio";
			reg = <0x24520 0x20>;

			phy0: ethernet-phy@0 {
				interrupt-parent = <&mpic>;
				interrupts = <10 1>;
				reg = <0x0>;
			};
			phy1: ethernet-phy@1 {
				interrupt-parent = <&mpic>;
				interrupts = <10 1>;
				reg = <0x1>;
			};
			phy2: ethernet-phy@2 {
				interrupt-parent = <&mpic>;
				interrupts = <10 1>;
				reg = <0x2>;
			};
			phy3: ethernet-phy@3 {
				interrupt-parent = <&mpic>;
				interrupts = <10 1>;
				reg = <0x3>;
			};
		};

		enet0: ethernet@24000 {
			cell-index = <0>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x24000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <29 2 30 2 34 2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy0>;
			phy-connection-type = "rgmii-id";
		};

		enet1: ethernet@25000 {
			cell-index = <1>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x25000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <35 2 36 2 40 2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy1>;
			phy-connection-type = "rgmii-id";
		};

		enet2: ethernet@26000 {
			cell-index = <2>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x26000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <31 2 32 2 33 2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy2>;
			phy-connection-type = "rgmii-id";
		};

		enet3: ethernet@27000 {
			cell-index = <3>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x27000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <37 2 38 2 39 2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy3>;
			phy-connection-type = "rgmii-id";
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4500 0x100>;
			clock-frequency = <0>;
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4600 0x100>;
			clock-frequency = <0>;
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		global-utilities@e0000 {	//global utilities block
			compatible = "fsl,mpc8572-guts";
			reg = <0xe0000 0x1000>;
			fsl,has-rstcr;
		};

		msi@41600 {
			compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
			reg = <0x41600 0x80>;
			msi-available-ranges = <0 0x100>;
			interrupts = <
				0xe0 0
				0xe1 0
				0xe2 0
				0xe3 0
				0xe4 0
				0xe5 0
				0xe6 0
				0xe7 0>;
			interrupt-parent = <&mpic>;
		};

		mpic: pic@40000 {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x40000 0x40000>;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
		};
	};

	pci0: pcie@ffe08000 {
		cell-index = <0>;
		compatible = "fsl,mpc8548-pcie";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xffe08000 0x1000>;
		bus-range = <0 255>;
		ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
			  0x1000000 0x0 0x0 0xffc00000 0x0 0x10000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <24 2>;
		interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
		interrupt-map = <
			/* IDSEL 0x11 func 0 - PCI slot 1 */
			0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
			0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
			0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
			0x8800 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x11 func 1 - PCI slot 1 */
			0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
			0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
			0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
			0x8900 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x11 func 2 - PCI slot 1 */
			0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
			0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
			0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
			0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x11 func 3 - PCI slot 1 */
			0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
			0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
			0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
			0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x11 func 4 - PCI slot 1 */
			0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
			0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
			0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
			0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x11 func 5 - PCI slot 1 */
			0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
			0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
			0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
			0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x11 func 6 - PCI slot 1 */
			0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
			0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
			0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
			0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x11 func 7 - PCI slot 1 */
			0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
			0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
			0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
			0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x12 func 0 - PCI slot 2 */
			0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
			0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
			0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
			0x9000 0x0 0x0 0x4 &mpic 0x2 0x1

			/* IDSEL 0x12 func 1 - PCI slot 2 */
			0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
			0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
			0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
			0x9100 0x0 0x0 0x4 &mpic 0x2 0x1

			/* IDSEL 0x12 func 2 - PCI slot 2 */
			0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
			0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
			0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
			0x9200 0x0 0x0 0x4 &mpic 0x2 0x1

			/* IDSEL 0x12 func 3 - PCI slot 2 */
			0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
			0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
			0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
			0x9300 0x0 0x0 0x4 &mpic 0x2 0x1

			/* IDSEL 0x12 func 4 - PCI slot 2 */
			0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
			0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
			0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
			0x9400 0x0 0x0 0x4 &mpic 0x2 0x1

			/* IDSEL 0x12 func 5 - PCI slot 2 */
			0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
			0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
			0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
			0x9500 0x0 0x0 0x4 &mpic 0x2 0x1

			/* IDSEL 0x12 func 6 - PCI slot 2 */
			0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
			0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
			0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
			0x9600 0x0 0x0 0x4 &mpic 0x2 0x1

			/* IDSEL 0x12 func 7 - PCI slot 2 */
			0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
			0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
			0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
			0x9700 0x0 0x0 0x4 &mpic 0x2 0x1

			// IDSEL 0x1c  USB
			0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
			0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
			0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
			0xe300 0x0 0x0 0x4 &i8259 0xb 0x2

			// IDSEL 0x1d  Audio
			0xe800 0x0 0x0 0x1 &i8259 0x6 0x2

			// IDSEL 0x1e Legacy
			0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
			0xf100 0x0 0x0 0x1 &i8259 0x7 0x2

			// IDSEL 0x1f IDE/SATA
			0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
			0xf900 0x0 0x0 0x1 &i8259 0x5 0x2

			>;

		pcie@0 {
			reg = <0x0 0x0 0x0 0x0 0x0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x2000000 0x0 0x80000000
				  0x2000000 0x0 0x80000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x100000>;
			uli1575@0 {
				reg = <0x0 0x0 0x0 0x0 0x0>;
				#size-cells = <2>;
				#address-cells = <3>;
				ranges = <0x2000000 0x0 0x80000000
					  0x2000000 0x0 0x80000000
					  0x0 0x20000000

					  0x1000000 0x0 0x0
					  0x1000000 0x0 0x0
					  0x0 0x100000>;
				isa@1e {
					device_type = "isa";
					#interrupt-cells = <2>;
					#size-cells = <1>;
					#address-cells = <2>;
					reg = <0xf000 0x0 0x0 0x0 0x0>;
					ranges = <0x1 0x0 0x1000000 0x0 0x0
						  0x1000>;
					interrupt-parent = <&i8259>;

					i8259: interrupt-controller@20 {
						reg = <0x1 0x20 0x2
						       0x1 0xa0 0x2
						       0x1 0x4d0 0x2>;
						interrupt-controller;
						device_type = "interrupt-controller";
						#address-cells = <0>;
						#interrupt-cells = <2>;
						compatible = "chrp,iic";
						interrupts = <9 2>;
						interrupt-parent = <&mpic>;
					};

					i8042@60 {
						#size-cells = <0>;
						#address-cells = <1>;
						reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
						interrupts = <1 3 12 3>;
						interrupt-parent =
							<&i8259>;

						keyboard@0 {
							reg = <0x0>;
							compatible = "pnpPNP,303";
						};

						mouse@1 {
							reg = <0x1>;
							compatible = "pnpPNP,f03";
						};
					};

					rtc@70 {
						compatible = "pnpPNP,b00";
						reg = <0x1 0x70 0x2>;
					};

					gpio@400 {
						reg = <0x1 0x400 0x80>;
					};
				};
			};
		};

	};

	pci1: pcie@ffe09000 {
		cell-index = <1>;
		compatible = "fsl,mpc8548-pcie";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xffe09000 0x1000>;
		bus-range = <0 255>;
		ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
			  0x1000000 0x0 0x0 0xffc10000 0x0 0x10000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <26 2>;
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <
			/* IDSEL 0x0 */
			0000 0x0 0x0 0x1 &mpic 0x4 0x1
			0000 0x0 0x0 0x2 &mpic 0x5 0x1
			0000 0x0 0x0 0x3 &mpic 0x6 0x1
			0000 0x0 0x0 0x4 &mpic 0x7 0x1
			>;
		pcie@0 {
			reg = <0x0 0x0 0x0 0x0 0x0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x2000000 0x0 0xa0000000
				  0x2000000 0x0 0xa0000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x100000>;
		};
	};

	pci2: pcie@ffe0a000 {
		cell-index = <2>;
		compatible = "fsl,mpc8548-pcie";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xffe0a000 0x1000>;
		bus-range = <0 255>;
		ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
			  0x1000000 0x0 0x0 0xffc20000 0x0 0x10000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <27 2>;
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <
			/* IDSEL 0x0 */
			0000 0x0 0x0 0x1 &mpic 0x0 0x1
			0000 0x0 0x0 0x2 &mpic 0x1 0x1
			0000 0x0 0x0 0x3 &mpic 0x2 0x1
			0000 0x0 0x0 0x4 &mpic 0x3 0x1
			>;
		pcie@0 {
			reg = <0x0 0x0 0x0 0x0 0x0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x2000000 0x0 0xc0000000
				  0x2000000 0x0 0xc0000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x100000>;
		};
	};
};
Commit	Line	Data
5d54ddcb KG	1	/*
	2	* MPC8572 DS Device Tree Source
	3	*
32f960e9	4	* Copyright 2007, 2008 Freescale Semiconductor Inc.
5d54ddcb KG	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*/
	11
32f960e9	12	/dts-v1/;
5d54ddcb KG	13	/ {
	14	model = "fsl,MPC8572DS";
	15	compatible = "fsl,MPC8572DS";
	16	#address-cells = <1>;
	17	#size-cells = <1>;
	18
ea082fa9 KG	19	aliases {
	20	ethernet0 = &enet0;
	21	ethernet1 = &enet1;
	22	ethernet2 = &enet2;
	23	ethernet3 = &enet3;
	24	serial0 = &serial0;
	25	serial1 = &serial1;
	26	pci0 = &pci0;
	27	pci1 = &pci1;
	28	pci2 = &pci2;
	29	};
	30
5d54ddcb KG	31	cpus {
	32	#address-cells = <1>;
	33	#size-cells = <0>;
	34
	35	PowerPC,8572@0 {
	36	device_type = "cpu";
32f960e9 KG	37	reg = <0x0>;
	38	d-cache-line-size = <32>; // 32 bytes
	39	i-cache-line-size = <32>; // 32 bytes
	40	d-cache-size = <0x8000>; // L1, 32K
	41	i-cache-size = <0x8000>; // L1, 32K
5d54ddcb	42	timebase-frequency = <0>;
7e25867f KG	43	bus-frequency = <0>;
	44	clock-frequency = <0>;
	45	};
	46
	47	PowerPC,8572@1 {
	48	device_type = "cpu";
32f960e9 KG	49	reg = <0x1>;
	50	d-cache-line-size = <32>; // 32 bytes
	51	i-cache-line-size = <32>; // 32 bytes
	52	d-cache-size = <0x8000>; // L1, 32K
	53	i-cache-size = <0x8000>; // L1, 32K
7e25867f	54	timebase-frequency = <0>;
5d54ddcb KG	55	bus-frequency = <0>;
	56	clock-frequency = <0>;
	57	};
	58	};
	59
	60	memory {
	61	device_type = "memory";
32f960e9	62	reg = <0x0 0x0>; // Filled by U-Boot
5d54ddcb KG	63	};
	64
	65	soc8572@ffe00000 {
	66	#address-cells = <1>;
	67	#size-cells = <1>;
	68	device_type = "soc";
32f960e9 KG	69	ranges = <0x0 0xffe00000 0x100000>;
32f960e9 KG	70	reg = <0xffe00000 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed
5d54ddcb KG	71	bus-frequency = <0>; // Filled out by uboot.
	72
	73	memory-controller@2000 {
	74	compatible = "fsl,mpc8572-memory-controller";
32f960e9	75	reg = <0x2000 0x1000>;
5d54ddcb	76	interrupt-parent = <&mpic>;
32f960e9	77	interrupts = <18 2>;
5d54ddcb KG	78	};
	79
	80	memory-controller@6000 {
	81	compatible = "fsl,mpc8572-memory-controller";
32f960e9	82	reg = <0x6000 0x1000>;
5d54ddcb	83	interrupt-parent = <&mpic>;
32f960e9	84	interrupts = <18 2>;
5d54ddcb KG	85	};
	86
	87	l2-cache-controller@20000 {
	88	compatible = "fsl,mpc8572-l2-cache-controller";
32f960e9 KG	89	reg = <0x20000 0x1000>;
	90	cache-line-size = <32>; // 32 bytes
	91	cache-size = <0x80000>; // L2, 512K
5d54ddcb	92	interrupt-parent = <&mpic>;
32f960e9	93	interrupts = <16 2>;
5d54ddcb KG	94	};
	95
	96	i2c@3000 {
ec9686c4 KG	97	#address-cells = <1>;
	98	#size-cells = <0>;
	99	cell-index = <0>;
5d54ddcb	100	compatible = "fsl-i2c";
32f960e9 KG	101	reg = <0x3000 0x100>;
32f960e9 KG	102	interrupts = <43 2>;
5d54ddcb KG	103	interrupt-parent = <&mpic>;
	104	dfsrr;
	105	};
	106
	107	i2c@3100 {
ec9686c4 KG	108	#address-cells = <1>;
	109	#size-cells = <0>;
	110	cell-index = <1>;
5d54ddcb	111	compatible = "fsl-i2c";
32f960e9 KG	112	reg = <0x3100 0x100>;
32f960e9 KG	113	interrupts = <43 2>;
5d54ddcb KG	114	interrupt-parent = <&mpic>;
	115	dfsrr;
	116	};
	117
	118	mdio@24520 {
	119	#address-cells = <1>;
	120	#size-cells = <0>;
e77b28eb	121	compatible = "fsl,gianfar-mdio";
32f960e9	122	reg = <0x24520 0x20>;
e77b28eb	123
5d54ddcb KG	124	phy0: ethernet-phy@0 {
5d54ddcb KG	125	interrupt-parent = <&mpic>;
32f960e9 KG	126	interrupts = <10 1>;
32f960e9 KG	127	reg = <0x0>;
5d54ddcb KG	128	};
	129	phy1: ethernet-phy@1 {
	130	interrupt-parent = <&mpic>;
32f960e9 KG	131	interrupts = <10 1>;
32f960e9 KG	132	reg = <0x1>;
5d54ddcb KG	133	};
	134	phy2: ethernet-phy@2 {
	135	interrupt-parent = <&mpic>;
32f960e9 KG	136	interrupts = <10 1>;
32f960e9 KG	137	reg = <0x2>;
5d54ddcb KG	138	};
	139	phy3: ethernet-phy@3 {
	140	interrupt-parent = <&mpic>;
32f960e9 KG	141	interrupts = <10 1>;
32f960e9 KG	142	reg = <0x3>;
5d54ddcb KG	143	};
	144	};
	145
e77b28eb KG	146	enet0: ethernet@24000 {
e77b28eb KG	147	cell-index = <0>;
5d54ddcb KG	148	device_type = "network";
	149	model = "eTSEC";
	150	compatible = "gianfar";
32f960e9	151	reg = <0x24000 0x1000>;
5d54ddcb	152	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	153	interrupts = <29 2 30 2 34 2>;
5d54ddcb KG	154	interrupt-parent = <&mpic>;
	155	phy-handle = <&phy0>;
	156	phy-connection-type = "rgmii-id";
	157	};
	158
e77b28eb KG	159	enet1: ethernet@25000 {
e77b28eb KG	160	cell-index = <1>;
5d54ddcb KG	161	device_type = "network";
	162	model = "eTSEC";
	163	compatible = "gianfar";
32f960e9	164	reg = <0x25000 0x1000>;
5d54ddcb	165	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	166	interrupts = <35 2 36 2 40 2>;
5d54ddcb KG	167	interrupt-parent = <&mpic>;
	168	phy-handle = <&phy1>;
	169	phy-connection-type = "rgmii-id";
	170	};
	171
e77b28eb KG	172	enet2: ethernet@26000 {
e77b28eb KG	173	cell-index = <2>;
5d54ddcb KG	174	device_type = "network";
	175	model = "eTSEC";
	176	compatible = "gianfar";
32f960e9	177	reg = <0x26000 0x1000>;
5d54ddcb	178	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	179	interrupts = <31 2 32 2 33 2>;
5d54ddcb KG	180	interrupt-parent = <&mpic>;
	181	phy-handle = <&phy2>;
	182	phy-connection-type = "rgmii-id";
	183	};
	184
e77b28eb KG	185	enet3: ethernet@27000 {
e77b28eb KG	186	cell-index = <3>;
5d54ddcb KG	187	device_type = "network";
	188	model = "eTSEC";
	189	compatible = "gianfar";
32f960e9	190	reg = <0x27000 0x1000>;
5d54ddcb	191	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	192	interrupts = <37 2 38 2 39 2>;
5d54ddcb KG	193	interrupt-parent = <&mpic>;
	194	phy-handle = <&phy3>;
	195	phy-connection-type = "rgmii-id";
	196	};
	197
ea082fa9 KG	198	serial0: serial@4500 {
ea082fa9 KG	199	cell-index = <0>;
5d54ddcb KG	200	device_type = "serial";
5d54ddcb KG	201	compatible = "ns16550";
32f960e9	202	reg = <0x4500 0x100>;
5d54ddcb	203	clock-frequency = <0>;
32f960e9	204	interrupts = <42 2>;
5d54ddcb KG	205	interrupt-parent = <&mpic>;
	206	};
	207
ea082fa9 KG	208	serial1: serial@4600 {
ea082fa9 KG	209	cell-index = <1>;
5d54ddcb KG	210	device_type = "serial";
5d54ddcb KG	211	compatible = "ns16550";
32f960e9	212	reg = <0x4600 0x100>;
5d54ddcb	213	clock-frequency = <0>;
32f960e9	214	interrupts = <42 2>;
5d54ddcb KG	215	interrupt-parent = <&mpic>;
	216	};
	217
	218	global-utilities@e0000 { //global utilities block
	219	compatible = "fsl,mpc8572-guts";
32f960e9	220	reg = <0xe0000 0x1000>;
5d54ddcb KG	221	fsl,has-rstcr;
	222	};
	223
741edc49 JJ	224	msi@41600 {
	225	compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
	226	reg = <0x41600 0x80>;
	227	msi-available-ranges = <0 0x100>;
	228	interrupts = <
	229	0xe0 0
	230	0xe1 0
	231	0xe2 0
	232	0xe3 0
	233	0xe4 0
	234	0xe5 0
	235	0xe6 0
	236	0xe7 0>;
	237	interrupt-parent = <&mpic>;
	238	};
	239
5d54ddcb	240	mpic: pic@40000 {
5d54ddcb KG	241	interrupt-controller;
	242	#address-cells = <0>;
	243	#interrupt-cells = <2>;
32f960e9	244	reg = <0x40000 0x40000>;
5d54ddcb KG	245	compatible = "chrp,open-pic";
5d54ddcb KG	246	device_type = "open-pic";
5d54ddcb KG	247	};
	248	};
	249
ea082fa9 KG	250	pci0: pcie@ffe08000 {
ea082fa9 KG	251	cell-index = <0>;
5d54ddcb KG	252	compatible = "fsl,mpc8548-pcie";
	253	device_type = "pci";
	254	#interrupt-cells = <1>;
	255	#size-cells = <2>;
	256	#address-cells = <3>;
32f960e9 KG	257	reg = <0xffe08000 0x1000>;
	258	bus-range = <0 255>;
	259	ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
	260	0x1000000 0x0 0x0 0xffc00000 0x0 0x10000>;
	261	clock-frequency = <33333333>;
5d54ddcb	262	interrupt-parent = <&mpic>;
32f960e9 KG	263	interrupts = <24 2>;
32f960e9 KG	264	interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
5d54ddcb	265	interrupt-map = <
bebfa06c	266	/* IDSEL 0x11 func 0 - PCI slot 1 */
32f960e9 KG	267	0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
	268	0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
	269	0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
	270	0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
5d54ddcb	271
bebfa06c	272	/* IDSEL 0x11 func 1 - PCI slot 1 */
32f960e9 KG	273	0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
	274	0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
	275	0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
	276	0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
bebfa06c KG	277
bebfa06c KG	278	/* IDSEL 0x11 func 2 - PCI slot 1 */
32f960e9 KG	279	0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
	280	0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
	281	0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
	282	0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
bebfa06c KG	283
bebfa06c KG	284	/* IDSEL 0x11 func 3 - PCI slot 1 */
32f960e9 KG	285	0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
	286	0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
	287	0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
	288	0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
bebfa06c KG	289
bebfa06c KG	290	/* IDSEL 0x11 func 4 - PCI slot 1 */
32f960e9 KG	291	0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
	292	0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
	293	0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
	294	0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
bebfa06c KG	295
bebfa06c KG	296	/* IDSEL 0x11 func 5 - PCI slot 1 */
32f960e9 KG	297	0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
	298	0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
	299	0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
	300	0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
bebfa06c KG	301
bebfa06c KG	302	/* IDSEL 0x11 func 6 - PCI slot 1 */
32f960e9 KG	303	0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
	304	0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
	305	0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
	306	0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
bebfa06c KG	307
bebfa06c KG	308	/* IDSEL 0x11 func 7 - PCI slot 1 */
32f960e9 KG	309	0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
	310	0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
	311	0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
	312	0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
bebfa06c KG	313
bebfa06c KG	314	/* IDSEL 0x12 func 0 - PCI slot 2 */
32f960e9 KG	315	0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
	316	0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
	317	0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
	318	0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
5d54ddcb	319
bebfa06c	320	/* IDSEL 0x12 func 1 - PCI slot 2 */
32f960e9 KG	321	0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
	322	0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
	323	0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
	324	0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
bebfa06c KG	325
bebfa06c KG	326	/* IDSEL 0x12 func 2 - PCI slot 2 */
32f960e9 KG	327	0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
	328	0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
	329	0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
	330	0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
bebfa06c KG	331
bebfa06c KG	332	/* IDSEL 0x12 func 3 - PCI slot 2 */
32f960e9 KG	333	0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
	334	0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
	335	0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
	336	0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
bebfa06c KG	337
bebfa06c KG	338	/* IDSEL 0x12 func 4 - PCI slot 2 */
32f960e9 KG	339	0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
	340	0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
	341	0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
	342	0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
bebfa06c KG	343
bebfa06c KG	344	/* IDSEL 0x12 func 5 - PCI slot 2 */
32f960e9 KG	345	0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
	346	0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
	347	0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
	348	0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
bebfa06c KG	349
bebfa06c KG	350	/* IDSEL 0x12 func 6 - PCI slot 2 */
32f960e9 KG	351	0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
	352	0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
	353	0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
	354	0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
bebfa06c KG	355
bebfa06c KG	356	/* IDSEL 0x12 func 7 - PCI slot 2 */
32f960e9 KG	357	0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
	358	0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
	359	0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
	360	0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
bebfa06c	361
5d54ddcb	362	// IDSEL 0x1c USB
32f960e9 KG	363	0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
	364	0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
	365	0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
	366	0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
5d54ddcb KG	367
5d54ddcb KG	368	// IDSEL 0x1d Audio
32f960e9	369	0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
5d54ddcb KG	370
5d54ddcb KG	371	// IDSEL 0x1e Legacy
32f960e9 KG	372	0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
32f960e9 KG	373	0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
5d54ddcb KG	374
5d54ddcb KG	375	// IDSEL 0x1f IDE/SATA
32f960e9 KG	376	0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
32f960e9 KG	377	0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
5d54ddcb KG	378
	379	>;
	380
	381	pcie@0 {
32f960e9	382	reg = <0x0 0x0 0x0 0x0 0x0>;
5d54ddcb KG	383	#size-cells = <2>;
	384	#address-cells = <3>;
	385	device_type = "pci";
32f960e9 KG	386	ranges = <0x2000000 0x0 0x80000000
	387	0x2000000 0x0 0x80000000
	388	0x0 0x20000000
5d54ddcb	389
32f960e9 KG	390	0x1000000 0x0 0x0
	391	0x1000000 0x0 0x0
	392	0x0 0x100000>;
5d54ddcb	393	uli1575@0 {
32f960e9	394	reg = <0x0 0x0 0x0 0x0 0x0>;
5d54ddcb KG	395	#size-cells = <2>;
5d54ddcb KG	396	#address-cells = <3>;
32f960e9 KG	397	ranges = <0x2000000 0x0 0x80000000
	398	0x2000000 0x0 0x80000000
	399	0x0 0x20000000
5d54ddcb	400
32f960e9 KG	401	0x1000000 0x0 0x0
	402	0x1000000 0x0 0x0
	403	0x0 0x100000>;
5d54ddcb KG	404	isa@1e {
	405	device_type = "isa";
	406	#interrupt-cells = <2>;
	407	#size-cells = <1>;
	408	#address-cells = <2>;
32f960e9 KG	409	reg = <0xf000 0x0 0x0 0x0 0x0>;
	410	ranges = <0x1 0x0 0x1000000 0x0 0x0
	411	0x1000>;
5d54ddcb KG	412	interrupt-parent = <&i8259>;
	413
	414	i8259: interrupt-controller@20 {
32f960e9 KG	415	reg = <0x1 0x20 0x2
	416	0x1 0xa0 0x2
	417	0x1 0x4d0 0x2>;
5d54ddcb KG	418	interrupt-controller;
	419	device_type = "interrupt-controller";
	420	#address-cells = <0>;
	421	#interrupt-cells = <2>;
	422	compatible = "chrp,iic";
	423	interrupts = <9 2>;
	424	interrupt-parent = <&mpic>;
	425	};
	426
	427	i8042@60 {
	428	#size-cells = <0>;
	429	#address-cells = <1>;
32f960e9 KG	430	reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
32f960e9 KG	431	interrupts = <1 3 12 3>;
5d54ddcb KG	432	interrupt-parent =
	433	<&i8259>;
	434
	435	keyboard@0 {
32f960e9	436	reg = <0x0>;
5d54ddcb KG	437	compatible = "pnpPNP,303";
	438	};
	439
	440	mouse@1 {
32f960e9	441	reg = <0x1>;
5d54ddcb KG	442	compatible = "pnpPNP,f03";
	443	};
	444	};
	445
	446	rtc@70 {
	447	compatible = "pnpPNP,b00";
32f960e9	448	reg = <0x1 0x70 0x2>;
5d54ddcb KG	449	};
	450
	451	gpio@400 {
32f960e9	452	reg = <0x1 0x400 0x80>;
5d54ddcb KG	453	};
	454	};
	455	};
	456	};
	457
	458	};
	459
ea082fa9 KG	460	pci1: pcie@ffe09000 {
ea082fa9 KG	461	cell-index = <1>;
5d54ddcb KG	462	compatible = "fsl,mpc8548-pcie";
	463	device_type = "pci";
	464	#interrupt-cells = <1>;
	465	#size-cells = <2>;
	466	#address-cells = <3>;
32f960e9 KG	467	reg = <0xffe09000 0x1000>;
	468	bus-range = <0 255>;
	469	ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
	470	0x1000000 0x0 0x0 0xffc10000 0x0 0x10000>;
	471	clock-frequency = <33333333>;
5d54ddcb	472	interrupt-parent = <&mpic>;
32f960e9 KG	473	interrupts = <26 2>;
32f960e9 KG	474	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
5d54ddcb KG	475	interrupt-map = <
5d54ddcb KG	476	/* IDSEL 0x0 */
32f960e9 KG	477	0000 0x0 0x0 0x1 &mpic 0x4 0x1
	478	0000 0x0 0x0 0x2 &mpic 0x5 0x1
	479	0000 0x0 0x0 0x3 &mpic 0x6 0x1
	480	0000 0x0 0x0 0x4 &mpic 0x7 0x1
5d54ddcb KG	481	>;
5d54ddcb KG	482	pcie@0 {
32f960e9	483	reg = <0x0 0x0 0x0 0x0 0x0>;
5d54ddcb KG	484	#size-cells = <2>;
	485	#address-cells = <3>;
	486	device_type = "pci";
32f960e9 KG	487	ranges = <0x2000000 0x0 0xa0000000
	488	0x2000000 0x0 0xa0000000
	489	0x0 0x20000000
5d54ddcb	490
32f960e9 KG	491	0x1000000 0x0 0x0
	492	0x1000000 0x0 0x0
	493	0x0 0x100000>;
5d54ddcb KG	494	};
	495	};
	496
ea082fa9 KG	497	pci2: pcie@ffe0a000 {
ea082fa9 KG	498	cell-index = <2>;
5d54ddcb KG	499	compatible = "fsl,mpc8548-pcie";
	500	device_type = "pci";
	501	#interrupt-cells = <1>;
	502	#size-cells = <2>;
	503	#address-cells = <3>;
32f960e9 KG	504	reg = <0xffe0a000 0x1000>;
	505	bus-range = <0 255>;
	506	ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
	507	0x1000000 0x0 0x0 0xffc20000 0x0 0x10000>;
	508	clock-frequency = <33333333>;
5d54ddcb	509	interrupt-parent = <&mpic>;
32f960e9 KG	510	interrupts = <27 2>;
32f960e9 KG	511	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
5d54ddcb KG	512	interrupt-map = <
5d54ddcb KG	513	/* IDSEL 0x0 */
32f960e9 KG	514	0000 0x0 0x0 0x1 &mpic 0x0 0x1
	515	0000 0x0 0x0 0x2 &mpic 0x1 0x1
	516	0000 0x0 0x0 0x3 &mpic 0x2 0x1
	517	0000 0x0 0x0 0x4 &mpic 0x3 0x1
5d54ddcb KG	518	>;
5d54ddcb KG	519	pcie@0 {
32f960e9	520	reg = <0x0 0x0 0x0 0x0 0x0>;
5d54ddcb KG	521	#size-cells = <2>;
	522	#address-cells = <3>;
	523	device_type = "pci";
32f960e9 KG	524	ranges = <0x2000000 0x0 0xc0000000
	525	0x2000000 0x0 0xc0000000
	526	0x0 0x20000000
5d54ddcb	527
32f960e9 KG	528	0x1000000 0x0 0x0
	529	0x1000000 0x0 0x0
	530	0x0 0x100000>;
5d54ddcb KG	531	};
	532	};
	533	};