[deliverable/linux.git] / arch / powerpc / boot / dts / mpc8572ds_camp_core0.dts

/*
 * MPC8572 DS Core0 Device Tree Source in CAMP mode.
 *
 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
 * can be shared, all the other devices must be assigned to one core only.
 * This dts file allows core0 to have memory, l2, i2c, dma1, global-util, eth0,
 * eth1, crypto, pci0, pci1.
 *
 * Copyright 2007-2009 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/dts-v1/;
/ {
	model = "fsl,MPC8572DS";
	compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		serial0 = &serial0;
		pci0 = &pci0;
		pci1 = &pci1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8572@0 {
			device_type = "cpu";
			reg = <0x0>;
			d-cache-line-size = <32>;	// 32 bytes
			i-cache-line-size = <32>;	// 32 bytes
			d-cache-size = <0x8000>;		// L1, 32K
			i-cache-size = <0x8000>;		// L1, 32K
			timebase-frequency = <0>;
			bus-frequency = <0>;
			clock-frequency = <0>;
			next-level-cache = <&L2>;
		};

	};

	memory {
		device_type = "memory";
		reg = <0x0 0x0>;	// Filled by U-Boot
	};

	soc8572@ffe00000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		compatible = "simple-bus";
		ranges = <0x0 0xffe00000 0x100000>;
		reg = <0xffe00000 0x1000>;	// CCSRBAR & soc regs, remove once parse code for immrbase fixed
		bus-frequency = <0>;		// Filled out by uboot.

		memory-controller@2000 {
			compatible = "fsl,mpc8572-memory-controller";
			reg = <0x2000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <18 2>;
		};

		memory-controller@6000 {
			compatible = "fsl,mpc8572-memory-controller";
			reg = <0x6000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <18 2>;
		};

		L2: l2-cache-controller@20000 {
			compatible = "fsl,mpc8572-l2-cache-controller";
			reg = <0x20000 0x1000>;
			cache-line-size = <32>;	// 32 bytes
			cache-size = <0x80000>;	// L2, 512K
			interrupt-parent = <&mpic>;
			interrupts = <16 2>;
		};

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		dma@21300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
			reg = <0x21300 0x4>;
			ranges = <0x0 0x21100 0x200>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,mpc8572-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x0 0x80>;
				cell-index = <0>;
				interrupt-parent = <&mpic>;
				interrupts = <20 2>;
			};
			dma-channel@80 {
				compatible = "fsl,mpc8572-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupt-parent = <&mpic>;
				interrupts = <21 2>;
			};
			dma-channel@100 {
				compatible = "fsl,mpc8572-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupt-parent = <&mpic>;
				interrupts = <22 2>;
			};
			dma-channel@180 {
				compatible = "fsl,mpc8572-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x180 0x80>;
				cell-index = <3>;
				interrupt-parent = <&mpic>;
				interrupts = <23 2>;
			};
		};

		mdio@24520 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,gianfar-mdio";
			reg = <0x24520 0x20>;

			phy0: ethernet-phy@0 {
				interrupt-parent = <&mpic>;
				interrupts = <10 1>;
				reg = <0x0>;
			};
			phy1: ethernet-phy@1 {
				interrupt-parent = <&mpic>;
				interrupts = <10 1>;
				reg = <0x1>;
			};
		};

		enet0: ethernet@24000 {
			cell-index = <0>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x24000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <29 2 30 2 34 2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy0>;
			phy-connection-type = "rgmii-id";
		};

		enet1: ethernet@25000 {
			cell-index = <1>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x25000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <35 2 36 2 40 2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy1>;
			phy-connection-type = "rgmii-id";
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4500 0x100>;
			clock-frequency = <0>;
		};

		global-utilities@e0000 {	//global utilities block
			compatible = "fsl,mpc8572-guts";
			reg = <0xe0000 0x1000>;
			fsl,has-rstcr;
		};

		crypto@30000 {
			compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
				     "fsl,sec2.1", "fsl,sec2.0";
			reg = <0x30000 0x10000>;
			interrupts = <45 2 58 2>;
			interrupt-parent = <&mpic>;
			fsl,num-channels = <4>;
			fsl,channel-fifo-len = <24>;
			fsl,exec-units-mask = <0x9fe>;
			fsl,descriptor-types-mask = <0x3ab0ebf>;
		};

		mpic: pic@40000 {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x40000 0x40000>;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
			protected-sources = <
			31 32 33 37 38 39       /* enet2 enet3 */
			76 77 78 79 26 42	/* dma2 pci2 serial*/
			0xe0 0xe1 0xe2 0xe3     /* msi */
			0xe4 0xe5 0xe6 0xe7
			>;
		};
	};

	pci0: pcie@ffe08000 {
		cell-index = <0>;
		compatible = "fsl,mpc8548-pcie";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xffe08000 0x1000>;
		bus-range = <0 255>;
		ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
			  0x1000000 0x0 0x0 0xffc00000 0x0 0x10000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <24 2>;
		interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
		interrupt-map = <
			/* IDSEL 0x11 func 0 - PCI slot 1 */
			0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
			0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
			0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
			0x8800 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x11 func 1 - PCI slot 1 */
			0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
			0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
			0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
			0x8900 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x11 func 2 - PCI slot 1 */
			0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
			0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
			0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
			0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x11 func 3 - PCI slot 1 */
			0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
			0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
			0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
			0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x11 func 4 - PCI slot 1 */
			0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
			0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
			0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
			0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x11 func 5 - PCI slot 1 */
			0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
			0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
			0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
			0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x11 func 6 - PCI slot 1 */
			0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
			0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
			0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
			0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x11 func 7 - PCI slot 1 */
			0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
			0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
			0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
			0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x12 func 0 - PCI slot 2 */
			0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
			0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
			0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
			0x9000 0x0 0x0 0x4 &mpic 0x2 0x1

			/* IDSEL 0x12 func 1 - PCI slot 2 */
			0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
			0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
			0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
			0x9100 0x0 0x0 0x4 &mpic 0x2 0x1

			/* IDSEL 0x12 func 2 - PCI slot 2 */
			0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
			0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
			0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
			0x9200 0x0 0x0 0x4 &mpic 0x2 0x1

			/* IDSEL 0x12 func 3 - PCI slot 2 */
			0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
			0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
			0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
			0x9300 0x0 0x0 0x4 &mpic 0x2 0x1

			/* IDSEL 0x12 func 4 - PCI slot 2 */
			0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
			0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
			0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
			0x9400 0x0 0x0 0x4 &mpic 0x2 0x1

			/* IDSEL 0x12 func 5 - PCI slot 2 */
			0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
			0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
			0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
			0x9500 0x0 0x0 0x4 &mpic 0x2 0x1

			/* IDSEL 0x12 func 6 - PCI slot 2 */
			0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
			0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
			0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
			0x9600 0x0 0x0 0x4 &mpic 0x2 0x1

			/* IDSEL 0x12 func 7 - PCI slot 2 */
			0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
			0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
			0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
			0x9700 0x0 0x0 0x4 &mpic 0x2 0x1

			// IDSEL 0x1c  USB
			0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
			0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
			0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
			0xe300 0x0 0x0 0x4 &i8259 0xb 0x2

			// IDSEL 0x1d  Audio
			0xe800 0x0 0x0 0x1 &i8259 0x6 0x2

			// IDSEL 0x1e Legacy
			0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
			0xf100 0x0 0x0 0x1 &i8259 0x7 0x2

			// IDSEL 0x1f IDE/SATA
			0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
			0xf900 0x0 0x0 0x1 &i8259 0x5 0x2

			>;

		pcie@0 {
			reg = <0x0 0x0 0x0 0x0 0x0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x2000000 0x0 0x80000000
				  0x2000000 0x0 0x80000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x10000>;
			uli1575@0 {
				reg = <0x0 0x0 0x0 0x0 0x0>;
				#size-cells = <2>;
				#address-cells = <3>;
				ranges = <0x2000000 0x0 0x80000000
					  0x2000000 0x0 0x80000000
					  0x0 0x20000000

					  0x1000000 0x0 0x0
					  0x1000000 0x0 0x0
					  0x0 0x10000>;
				isa@1e {
					device_type = "isa";
					#interrupt-cells = <2>;
					#size-cells = <1>;
					#address-cells = <2>;
					reg = <0xf000 0x0 0x0 0x0 0x0>;
					ranges = <0x1 0x0 0x1000000 0x0 0x0
						  0x1000>;
					interrupt-parent = <&i8259>;

					i8259: interrupt-controller@20 {
						reg = <0x1 0x20 0x2
						       0x1 0xa0 0x2
						       0x1 0x4d0 0x2>;
						interrupt-controller;
						device_type = "interrupt-controller";
						#address-cells = <0>;
						#interrupt-cells = <2>;
						compatible = "chrp,iic";
						interrupts = <9 2>;
						interrupt-parent = <&mpic>;
					};

					i8042@60 {
						#size-cells = <0>;
						#address-cells = <1>;
						reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
						interrupts = <1 3 12 3>;
						interrupt-parent =
							<&i8259>;

						keyboard@0 {
							reg = <0x0>;
							compatible = "pnpPNP,303";
						};

						mouse@1 {
							reg = <0x1>;
							compatible = "pnpPNP,f03";
						};
					};

					rtc@70 {
						compatible = "pnpPNP,b00";
						reg = <0x1 0x70 0x2>;
					};

					gpio@400 {
						reg = <0x1 0x400 0x80>;
					};
				};
			};
		};

	};

	pci1: pcie@ffe09000 {
		cell-index = <1>;
		compatible = "fsl,mpc8548-pcie";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xffe09000 0x1000>;
		bus-range = <0 255>;
		ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
			  0x1000000 0x0 0x0 0xffc10000 0x0 0x10000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <25 2>;
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <
			/* IDSEL 0x0 */
			0000 0x0 0x0 0x1 &mpic 0x4 0x1
			0000 0x0 0x0 0x2 &mpic 0x5 0x1
			0000 0x0 0x0 0x3 &mpic 0x6 0x1
			0000 0x0 0x0 0x4 &mpic 0x7 0x1
			>;
		pcie@0 {
			reg = <0x0 0x0 0x0 0x0 0x0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x2000000 0x0 0xa0000000
				  0x2000000 0x0 0xa0000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x10000>;
		};
	};
};
Commit	Line	Data
361425fc HW	1	/*
	2	* MPC8572 DS Core0 Device Tree Source in CAMP mode.
	3	*
	4	* In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
	5	* can be shared, all the other devices must be assigned to one core only.
	6	* This dts file allows core0 to have memory, l2, i2c, dma1, global-util, eth0,
	7	* eth1, crypto, pci0, pci1.
	8	*
ca34040c	9	* Copyright 2007-2009 Freescale Semiconductor Inc.
361425fc HW	10	*
	11	* This program is free software; you can redistribute it and/or modify it
	12	* under the terms of the GNU General Public License as published by the
	13	* Free Software Foundation; either version 2 of the License, or (at your
	14	* option) any later version.
	15	*/
	16
	17	/dts-v1/;
	18	/ {
	19	model = "fsl,MPC8572DS";
	20	compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP";
	21	#address-cells = <1>;
	22	#size-cells = <1>;
	23
	24	aliases {
	25	ethernet0 = &enet0;
	26	ethernet1 = &enet1;
	27	serial0 = &serial0;
	28	pci0 = &pci0;
	29	pci1 = &pci1;
	30	};
	31
	32	cpus {
	33	#address-cells = <1>;
	34	#size-cells = <0>;
	35
	36	PowerPC,8572@0 {
	37	device_type = "cpu";
	38	reg = <0x0>;
	39	d-cache-line-size = <32>; // 32 bytes
	40	i-cache-line-size = <32>; // 32 bytes
	41	d-cache-size = <0x8000>; // L1, 32K
	42	i-cache-size = <0x8000>; // L1, 32K
	43	timebase-frequency = <0>;
	44	bus-frequency = <0>;
	45	clock-frequency = <0>;
	46	next-level-cache = <&L2>;
	47	};
	48
	49	};
	50
	51	memory {
	52	device_type = "memory";
	53	reg = <0x0 0x0>; // Filled by U-Boot
	54	};
	55
	56	soc8572@ffe00000 {
	57	#address-cells = <1>;
	58	#size-cells = <1>;
	59	device_type = "soc";
	60	compatible = "simple-bus";
	61	ranges = <0x0 0xffe00000 0x100000>;
	62	reg = <0xffe00000 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed
	63	bus-frequency = <0>; // Filled out by uboot.
	64
	65	memory-controller@2000 {
	66	compatible = "fsl,mpc8572-memory-controller";
	67	reg = <0x2000 0x1000>;
	68	interrupt-parent = <&mpic>;
	69	interrupts = <18 2>;
	70	};
	71
	72	memory-controller@6000 {
	73	compatible = "fsl,mpc8572-memory-controller";
74	reg = <0x6000 0x1000>;
75	interrupt-parent = <&mpic>;
76	interrupts = <18 2>;
77	};
78
79	L2: l2-cache-controller@20000 {
80	compatible = "fsl,mpc8572-l2-cache-controller";
81	reg = <0x20000 0x1000>;
82	cache-line-size = <32>; // 32 bytes
83	cache-size = <0x80000>; // L2, 512K
84	interrupt-parent = <&mpic>;
85	interrupts = <16 2>;
86	};
87
88	i2c@3000 {
89	#address-cells = <1>;
90	#size-cells = <0>;
91	cell-index = <0>;
92	compatible = "fsl-i2c";
93	reg = <0x3000 0x100>;
94	interrupts = <43 2>;
95	interrupt-parent = <&mpic>;
96	dfsrr;
97	};
98
99	i2c@3100 {
100	#address-cells = <1>;
101	#size-cells = <0>;
102	cell-index = <1>;
103	compatible = "fsl-i2c";
104	reg = <0x3100 0x100>;
105	interrupts = <43 2>;
106	interrupt-parent = <&mpic>;
107	dfsrr;
108	};
109
110	dma@21300 {
111	#address-cells = <1>;
112	#size-cells = <1>;
113	compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
114	reg = <0x21300 0x4>;
115	ranges = <0x0 0x21100 0x200>;
116	cell-index = <0>;
117	dma-channel@0 {
118	compatible = "fsl,mpc8572-dma-channel",
119	"fsl,eloplus-dma-channel";
120	reg = <0x0 0x80>;
121	cell-index = <0>;
122	interrupt-parent = <&mpic>;
123	interrupts = <20 2>;
124	};
125	dma-channel@80 {
126	compatible = "fsl,mpc8572-dma-channel",
127	"fsl,eloplus-dma-channel";
128	reg = <0x80 0x80>;
129	cell-index = <1>;
130	interrupt-parent = <&mpic>;
131	interrupts = <21 2>;
132	};
133	dma-channel@100 {
134	compatible = "fsl,mpc8572-dma-channel",
135	"fsl,eloplus-dma-channel";
136	reg = <0x100 0x80>;
137	cell-index = <2>;
138	interrupt-parent = <&mpic>;
139	interrupts = <22 2>;
140	};
141	dma-channel@180 {
142	compatible = "fsl,mpc8572-dma-channel",
143	"fsl,eloplus-dma-channel";
144	reg = <0x180 0x80>;
145	cell-index = <3>;
146	interrupt-parent = <&mpic>;
147	interrupts = <23 2>;
148	};
149	};
150
151	mdio@24520 {
152	#address-cells = <1>;
153	#size-cells = <0>;
154	compatible = "fsl,gianfar-mdio";
155	reg = <0x24520 0x20>;
156
157	phy0: ethernet-phy@0 {
158	interrupt-parent = <&mpic>;
159	interrupts = <10 1>;
160	reg = <0x0>;
161	};
162	phy1: ethernet-phy@1 {
163	interrupt-parent = <&mpic>;
164	interrupts = <10 1>;
165	reg = <0x1>;
166	};
167	};
168
169	enet0: ethernet@24000 {
170	cell-index = <0>;
171	device_type = "network";
172	model = "eTSEC";
173	compatible = "gianfar";
174	reg = <0x24000 0x1000>;
175	local-mac-address = [ 00 00 00 00 00 00 ];
176	interrupts = <29 2 30 2 34 2>;
177	interrupt-parent = <&mpic>;
178	phy-handle = <&phy0>;
179	phy-connection-type = "rgmii-id";
180	};
181
182	enet1: ethernet@25000 {
183	cell-index = <1>;
184	device_type = "network";
185	model = "eTSEC";
186	compatible = "gianfar";
187	reg = <0x25000 0x1000>;
188	local-mac-address = [ 00 00 00 00 00 00 ];
189	interrupts = <35 2 36 2 40 2>;
190	interrupt-parent = <&mpic>;
191	phy-handle = <&phy1>;
192	phy-connection-type = "rgmii-id";
193	};
194
195	serial0: serial@4500 {
196	cell-index = <0>;
197	device_type = "serial";
198	compatible = "ns16550";
199	reg = <0x4500 0x100>;
200	clock-frequency = <0>;
201	};
202
203	global-utilities@e0000 { //global utilities block
204	compatible = "fsl,mpc8572-guts";
205	reg = <0xe0000 0x1000>;
206	fsl,has-rstcr;
207	};
208
209	crypto@30000 {
210	compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
211	"fsl,sec2.1", "fsl,sec2.0";
212	reg = <0x30000 0x10000>;
213	interrupts = <45 2 58 2>;
214	interrupt-parent = <&mpic>;
215	fsl,num-channels = <4>;
216	fsl,channel-fifo-len = <24>;
217	fsl,exec-units-mask = <0x9fe>;
218	fsl,descriptor-types-mask = <0x3ab0ebf>;
219	};
220
221	mpic: pic@40000 {
222	interrupt-controller;
223	#address-cells = <0>;
224	#interrupt-cells = <2>;
225	reg = <0x40000 0x40000>;
226	compatible = "chrp,open-pic";
227	device_type = "open-pic";
228	protected-sources = <
229	31 32 33 37 38 39 /* enet2 enet3 */
f084e8db	230	76 77 78 79 26 42 /* dma2 pci2 serial*/
361425fc HW	231	0xe0 0xe1 0xe2 0xe3 /* msi */
	232	0xe4 0xe5 0xe6 0xe7
	233	>;
	234	};
	235	};
	236
	237	pci0: pcie@ffe08000 {
	238	cell-index = <0>;
	239	compatible = "fsl,mpc8548-pcie";
	240	device_type = "pci";
	241	#interrupt-cells = <1>;
	242	#size-cells = <2>;
	243	#address-cells = <3>;
	244	reg = <0xffe08000 0x1000>;
	245	bus-range = <0 255>;
	246	ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
	247	0x1000000 0x0 0x0 0xffc00000 0x0 0x10000>;
	248	clock-frequency = <33333333>;
	249	interrupt-parent = <&mpic>;
	250	interrupts = <24 2>;
	251	interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
	252	interrupt-map = <
	253	/* IDSEL 0x11 func 0 - PCI slot 1 */
	254	0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
	255	0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
	256	0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
	257	0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
	258
	259	/* IDSEL 0x11 func 1 - PCI slot 1 */
	260	0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
	261	0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
	262	0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
	263	0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
	264
	265	/* IDSEL 0x11 func 2 - PCI slot 1 */
	266	0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
	267	0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
	268	0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
	269	0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
	270
	271	/* IDSEL 0x11 func 3 - PCI slot 1 */
	272	0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
	273	0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
	274	0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
	275	0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
	276
	277	/* IDSEL 0x11 func 4 - PCI slot 1 */
	278	0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
	279	0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
	280	0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
	281	0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
	282
	283	/* IDSEL 0x11 func 5 - PCI slot 1 */
	284	0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
	285	0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
	286	0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
	287	0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
	288
	289	/* IDSEL 0x11 func 6 - PCI slot 1 */
	290	0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
	291	0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
	292	0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
	293	0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
	294
295	/* IDSEL 0x11 func 7 - PCI slot 1 */
296	0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
297	0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
298	0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
299	0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
300
301	/* IDSEL 0x12 func 0 - PCI slot 2 */
302	0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
303	0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
304	0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
305	0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
306
307	/* IDSEL 0x12 func 1 - PCI slot 2 */
308	0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
309	0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
310	0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
311	0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
312
313	/* IDSEL 0x12 func 2 - PCI slot 2 */
314	0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
315	0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
316	0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
317	0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
318
319	/* IDSEL 0x12 func 3 - PCI slot 2 */
320	0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
321	0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
322	0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
323	0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
324
325	/* IDSEL 0x12 func 4 - PCI slot 2 */
326	0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
327	0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
328	0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
329	0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
330
331	/* IDSEL 0x12 func 5 - PCI slot 2 */
332	0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
333	0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
334	0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
335	0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
336
337	/* IDSEL 0x12 func 6 - PCI slot 2 */
338	0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
339	0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
340	0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
341	0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
342
343	/* IDSEL 0x12 func 7 - PCI slot 2 */
344	0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
345	0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
346	0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
347	0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
348
349	// IDSEL 0x1c USB
350	0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
351	0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
352	0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
353	0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
354
355	// IDSEL 0x1d Audio
356	0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
357
358	// IDSEL 0x1e Legacy
359	0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
360	0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
361
362	// IDSEL 0x1f IDE/SATA
363	0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
364	0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
365
366	>;
367
368	pcie@0 {
369	reg = <0x0 0x0 0x0 0x0 0x0>;
370	#size-cells = <2>;
371	#address-cells = <3>;
372	device_type = "pci";
373	ranges = <0x2000000 0x0 0x80000000
374	0x2000000 0x0 0x80000000
375	0x0 0x20000000
376
377	0x1000000 0x0 0x0
378	0x1000000 0x0 0x0
ca34040c	379	0x0 0x10000>;
361425fc HW	380	uli1575@0 {
	381	reg = <0x0 0x0 0x0 0x0 0x0>;
	382	#size-cells = <2>;
	383	#address-cells = <3>;
	384	ranges = <0x2000000 0x0 0x80000000
	385	0x2000000 0x0 0x80000000
	386	0x0 0x20000000
	387
	388	0x1000000 0x0 0x0
	389	0x1000000 0x0 0x0
ca34040c	390	0x0 0x10000>;
361425fc HW	391	isa@1e {
	392	device_type = "isa";
	393	#interrupt-cells = <2>;
	394	#size-cells = <1>;
	395	#address-cells = <2>;
	396	reg = <0xf000 0x0 0x0 0x0 0x0>;
	397	ranges = <0x1 0x0 0x1000000 0x0 0x0
	398	0x1000>;
	399	interrupt-parent = <&i8259>;
	400
	401	i8259: interrupt-controller@20 {
	402	reg = <0x1 0x20 0x2
	403	0x1 0xa0 0x2
	404	0x1 0x4d0 0x2>;
	405	interrupt-controller;
	406	device_type = "interrupt-controller";
	407	#address-cells = <0>;
	408	#interrupt-cells = <2>;
	409	compatible = "chrp,iic";
	410	interrupts = <9 2>;
	411	interrupt-parent = <&mpic>;
	412	};
	413
	414	i8042@60 {
	415	#size-cells = <0>;
	416	#address-cells = <1>;
	417	reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
	418	interrupts = <1 3 12 3>;
	419	interrupt-parent =
	420	<&i8259>;
	421
	422	keyboard@0 {
	423	reg = <0x0>;
	424	compatible = "pnpPNP,303";
	425	};
	426
	427	mouse@1 {
	428	reg = <0x1>;
	429	compatible = "pnpPNP,f03";
	430	};
	431	};
	432
	433	rtc@70 {
	434	compatible = "pnpPNP,b00";
	435	reg = <0x1 0x70 0x2>;
	436	};
	437
	438	gpio@400 {
	439	reg = <0x1 0x400 0x80>;
	440	};
	441	};
	442	};
	443	};
	444
	445	};
	446
	447	pci1: pcie@ffe09000 {
	448	cell-index = <1>;
	449	compatible = "fsl,mpc8548-pcie";
	450	device_type = "pci";
	451	#interrupt-cells = <1>;
	452	#size-cells = <2>;
	453	#address-cells = <3>;
	454	reg = <0xffe09000 0x1000>;
455	bus-range = <0 255>;
456	ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
457	0x1000000 0x0 0x0 0xffc10000 0x0 0x10000>;
458	clock-frequency = <33333333>;
459	interrupt-parent = <&mpic>;
be122d6d	460	interrupts = <25 2>;
361425fc HW	461	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
	462	interrupt-map = <
	463	/* IDSEL 0x0 */
	464	0000 0x0 0x0 0x1 &mpic 0x4 0x1
	465	0000 0x0 0x0 0x2 &mpic 0x5 0x1
	466	0000 0x0 0x0 0x3 &mpic 0x6 0x1
	467	0000 0x0 0x0 0x4 &mpic 0x7 0x1
	468	>;
	469	pcie@0 {
	470	reg = <0x0 0x0 0x0 0x0 0x0>;
	471	#size-cells = <2>;
	472	#address-cells = <3>;
	473	device_type = "pci";
	474	ranges = <0x2000000 0x0 0xa0000000
	475	0x2000000 0x0 0xa0000000
	476	0x0 0x20000000
	477
	478	0x1000000 0x0 0x0
	479	0x1000000 0x0 0x0
ca34040c	480	0x0 0x10000>;
361425fc HW	481	};
	482	};
	483	};