[deliverable/linux.git] / arch / powerpc / boot / dts / mpc8610_hpcd.dts

/*
 * MPC8610 HPCD Device Tree Source
 *
 * Copyright 2007-2008 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under the terms of the GNU General Public License Version 2 as published
 * by the Free Software Foundation.
 */

/dts-v1/;

/ {
	model = "MPC8610HPCD";
	compatible = "fsl,MPC8610HPCD";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
		pci1 = &pci1;
		pci2 = &pci2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8610@0 {
			device_type = "cpu";
			reg = <0>;
			d-cache-line-size = <32>;
			i-cache-line-size = <32>;
			d-cache-size = <32768>;		// L1
			i-cache-size = <32768>;		// L1
			timebase-frequency = <0>;	// From uboot
			bus-frequency = <0>;		// From uboot
			clock-frequency = <0>;		// From uboot
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x20000000>;	// 512M at 0x0
	};

	localbus@e0005000 {
		#address-cells = <2>;
		#size-cells = <1>;
		compatible = "fsl,mpc8610-elbc", "fsl,elbc", "simple-bus";
		reg = <0xe0005000 0x1000>;
		interrupts = <19 2>;
		interrupt-parent = <&mpic>;
		ranges = <0 0 0xf8000000 0x08000000
			  1 0 0xf0000000 0x08000000
			  2 0 0xe8400000 0x00008000
			  4 0 0xe8440000 0x00008000
			  5 0 0xe8480000 0x00008000
			  6 0 0xe84c0000 0x00008000
			  3 0 0xe8000000 0x00000020>;

		flash@0,0 {
			compatible = "cfi-flash";
			reg = <0 0 0x8000000>;
			bank-width = <2>;
			device-width = <1>;
		};

		flash@1,0 {
			compatible = "cfi-flash";
			reg = <1 0 0x8000000>;
			bank-width = <2>;
			device-width = <1>;
		};

		flash@2,0 {
			compatible = "fsl,mpc8610-fcm-nand",
				     "fsl,elbc-fcm-nand";
			reg = <2 0 0x8000>;
		};

		flash@4,0 {
			compatible = "fsl,mpc8610-fcm-nand",
				     "fsl,elbc-fcm-nand";
			reg = <4 0 0x8000>;
		};

		flash@5,0 {
			compatible = "fsl,mpc8610-fcm-nand",
				     "fsl,elbc-fcm-nand";
			reg = <5 0 0x8000>;
		};

		flash@6,0 {
			compatible = "fsl,mpc8610-fcm-nand",
				     "fsl,elbc-fcm-nand";
			reg = <6 0 0x8000>;
		};

		board-control@3,0 {
			compatible = "fsl,fpga-pixis";
			reg = <3 0 0x20>;
		};
	};

	soc@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		#interrupt-cells = <2>;
		device_type = "soc";
		compatible = "fsl,mpc8610-immr", "simple-bus";
		ranges = <0x0 0xe0000000 0x00100000>;
		reg = <0xe0000000 0x1000>;
		bus-frequency = <0>;

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;

			cs4270:codec@4f {
				compatible = "cirrus,cs4270";
				reg = <0x4f>;
				/* MCLK source is a stand-alone oscillator */
				clock-frequency = <12288000>;
			};
		};

		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4500 0x100>;
			clock-frequency = <0>;
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4600 0x100>;
			clock-frequency = <0>;
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		display@2c000 {
			compatible = "fsl,diu";
			reg = <0x2c000 100>;
			interrupts = <72 2>;
			interrupt-parent = <&mpic>;
		};

		mpic: interrupt-controller@40000 {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x40000 0x40000>;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
		};

		msi@41600 {
			compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
			reg = <0x41600 0x80>;
			msi-available-ranges = <0 0x100>;
			interrupts = <
				0xe0 0
				0xe1 0
				0xe2 0
				0xe3 0
				0xe4 0
				0xe5 0
				0xe6 0
				0xe7 0>;
			interrupt-parent = <&mpic>;
		};

		global-utilities@e0000 {
			compatible = "fsl,mpc8610-guts";
			reg = <0xe0000 0x1000>;
			fsl,has-rstcr;
		};

		i2s@16000 {
			compatible = "fsl,mpc8610-ssi";
			cell-index = <0>;
			reg = <0x16000 0x100>;
			interrupt-parent = <&mpic>;
			interrupts = <62 2>;
			fsl,mode = "i2s-slave";
			codec-handle = <&cs4270>;
		};

		ssi@16100 {
			compatible = "fsl,mpc8610-ssi";
			cell-index = <1>;
			reg = <0x16100 0x100>;
			interrupt-parent = <&mpic>;
			interrupts = <63 2>;
		};

		dma@21300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
			cell-index = <0>;
			reg = <0x21300 0x4>; /* DMA general status register */
			ranges = <0x0 0x21100 0x200>;

			dma-channel@0 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,eloplus-dma-channel";
				cell-index = <0>;
				reg = <0x0 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <20 2>;
			};
			dma-channel@1 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,eloplus-dma-channel";
				cell-index = <1>;
				reg = <0x80 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <21 2>;
			};
			dma-channel@2 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,eloplus-dma-channel";
				cell-index = <2>;
				reg = <0x100 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <22 2>;
			};
			dma-channel@3 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,eloplus-dma-channel";
				cell-index = <3>;
				reg = <0x180 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <23 2>;
			};
		};

		dma@c300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
			cell-index = <1>;
			reg = <0xc300 0x4>; /* DMA general status register */
			ranges = <0x0 0xc100 0x200>;

			dma-channel@0 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,eloplus-dma-channel";
				cell-index = <0>;
				reg = <0x0 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <60 2>;
			};
			dma-channel@1 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,eloplus-dma-channel";
				cell-index = <1>;
				reg = <0x80 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <61 2>;
			};
			dma-channel@2 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,eloplus-dma-channel";
				cell-index = <2>;
				reg = <0x100 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <62 2>;
			};
			dma-channel@3 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,eloplus-dma-channel";
				cell-index = <3>;
				reg = <0x180 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <63 2>;
			};
		};

	};

	pci0: pci@e0008000 {
		cell-index = <0>;
		compatible = "fsl,mpc8610-pci";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0008000 0x1000>;
		bus-range = <0 0>;
		ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
			  0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <24 2>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <
			/* IDSEL 0x11 */
			0x8800 0 0 1 &mpic 4 1
			0x8800 0 0 2 &mpic 5 1
			0x8800 0 0 3 &mpic 6 1
			0x8800 0 0 4 &mpic 7 1

			/* IDSEL 0x12 */
			0x9000 0 0 1 &mpic 5 1
			0x9000 0 0 2 &mpic 6 1
			0x9000 0 0 3 &mpic 7 1
			0x9000 0 0 4 &mpic 4 1
			>;
	};

	pci1: pcie@e000a000 {
		cell-index = <1>;
		compatible = "fsl,mpc8641-pcie";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe000a000 0x1000>;
		bus-range = <1 3>;
		ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
			  0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <26 2>;
		interrupt-map-mask = <0xf800 0 0 7>;

		interrupt-map = <
			/* IDSEL 0x1b */
			0xd800 0 0 1 &mpic 2 1

			/* IDSEL 0x1c*/
			0xe000 0 0 1 &mpic 1 1
			0xe000 0 0 2 &mpic 1 1
			0xe000 0 0 3 &mpic 1 1
			0xe000 0 0 4 &mpic 1 1

			/* IDSEL 0x1f */
			0xf800 0 0 1 &mpic 3 2
			0xf800 0 0 2 &mpic 0 1
		>;

		pcie@0 {
			reg = <0 0 0 0 0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x02000000 0x0 0xa0000000
				  0x02000000 0x0 0xa0000000
				  0x0 0x10000000
				  0x01000000 0x0 0x00000000
				  0x01000000 0x0 0x00000000
				  0x0 0x00100000>;
			uli1575@0 {
				reg = <0 0 0 0 0>;
				#size-cells = <2>;
				#address-cells = <3>;
				ranges = <0x02000000 0x0 0xa0000000
					  0x02000000 0x0 0xa0000000
					  0x0 0x10000000
					  0x01000000 0x0 0x00000000
					  0x01000000 0x0 0x00000000
					  0x0 0x00100000>;
			};
		};
	};

	pci2: pcie@e0009000 {
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		device_type = "pci";
		compatible = "fsl,mpc8641-pcie";
		reg = <0xe0009000 0x00001000>;
		ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
			  0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
		bus-range = <0 255>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <0x0000 0 0 1 &mpic 4 1
				 0x0000 0 0 2 &mpic 5 1
				 0x0000 0 0 3 &mpic 6 1
				 0x0000 0 0 4 &mpic 7 1>;
		interrupt-parent = <&mpic>;
		interrupts = <25 2>;
		clock-frequency = <33333333>;
	};
};
Commit	Line	Data
53f3945a XX	1	/*
	2	* MPC8610 HPCD Device Tree Source
	3	*
c7d24a2d	4	* Copyright 2007-2008 Freescale Semiconductor Inc.
53f3945a XX	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License Version 2 as published
	8	* by the Free Software Foundation.
	9	*/
	10
6e050d4e	11	/dts-v1/;
53f3945a XX	12
	13	/ {
	14	model = "MPC8610HPCD";
	15	compatible = "fsl,MPC8610HPCD";
	16	#address-cells = <1>;
	17	#size-cells = <1>;
	18
ea082fa9 KG	19	aliases {
	20	serial0 = &serial0;
	21	serial1 = &serial1;
	22	pci0 = &pci0;
	23	pci1 = &pci1;
e598477a	24	pci2 = &pci2;
ea082fa9 KG	25	};
ea082fa9 KG	26
53f3945a XX	27	cpus {
	28	#address-cells = <1>;
	29	#size-cells = <0>;
	30
	31	PowerPC,8610@0 {
	32	device_type = "cpu";
	33	reg = <0>;
6e050d4e JL	34	d-cache-line-size = <32>;
	35	i-cache-line-size = <32>;
	36	d-cache-size = <32768>; // L1
	37	i-cache-size = <32768>; // L1
	38	timebase-frequency = <0>; // From uboot
53f3945a XX	39	bus-frequency = <0>; // From uboot
	40	clock-frequency = <0>; // From uboot
	41	};
	42	};
	43
	44	memory {
	45	device_type = "memory";
6e050d4e	46	reg = <0x00000000 0x20000000>; // 512M at 0x0
53f3945a XX	47	};
53f3945a XX	48
34b4a873 AV	49	localbus@e0005000 {
	50	#address-cells = <2>;
	51	#size-cells = <1>;
	52	compatible = "fsl,mpc8610-elbc", "fsl,elbc", "simple-bus";
	53	reg = <0xe0005000 0x1000>;
	54	interrupts = <19 2>;
	55	interrupt-parent = <&mpic>;
	56	ranges = <0 0 0xf8000000 0x08000000
	57	1 0 0xf0000000 0x08000000
	58	2 0 0xe8400000 0x00008000
	59	4 0 0xe8440000 0x00008000
	60	5 0 0xe8480000 0x00008000
	61	6 0 0xe84c0000 0x00008000
	62	3 0 0xe8000000 0x00000020>;
	63
	64	flash@0,0 {
	65	compatible = "cfi-flash";
	66	reg = <0 0 0x8000000>;
	67	bank-width = <2>;
	68	device-width = <1>;
	69	};
	70
	71	flash@1,0 {
	72	compatible = "cfi-flash";
	73	reg = <1 0 0x8000000>;
	74	bank-width = <2>;
	75	device-width = <1>;
	76	};
	77
	78	flash@2,0 {
	79	compatible = "fsl,mpc8610-fcm-nand",
	80	"fsl,elbc-fcm-nand";
	81	reg = <2 0 0x8000>;
	82	};
	83
	84	flash@4,0 {
	85	compatible = "fsl,mpc8610-fcm-nand",
	86	"fsl,elbc-fcm-nand";
	87	reg = <4 0 0x8000>;
	88	};
	89
	90	flash@5,0 {
	91	compatible = "fsl,mpc8610-fcm-nand",
	92	"fsl,elbc-fcm-nand";
	93	reg = <5 0 0x8000>;
	94	};
	95
	96	flash@6,0 {
	97	compatible = "fsl,mpc8610-fcm-nand",
	98	"fsl,elbc-fcm-nand";
	99	reg = <6 0 0x8000>;
	100	};
	101
	102	board-control@3,0 {
	103	compatible = "fsl,fpga-pixis";
	104	reg = <3 0 0x20>;
	105	};
9b53a9e2 YS	106	};
9b53a9e2 YS	107
53f3945a XX	108	soc@e0000000 {
	109	#address-cells = <1>;
	110	#size-cells = <1>;
	111	#interrupt-cells = <2>;
	112	device_type = "soc";
c7d24a2d	113	compatible = "fsl,mpc8610-immr", "simple-bus";
6e050d4e JL	114	ranges = <0x0 0xe0000000 0x00100000>;
6e050d4e JL	115	reg = <0xe0000000 0x1000>;
53f3945a XX	116	bus-frequency = <0>;
	117
	118	i2c@3000 {
53f3945a XX	119	#address-cells = <1>;
53f3945a XX	120	#size-cells = <0>;
ec9686c4 KG	121	cell-index = <0>;
ec9686c4 KG	122	compatible = "fsl-i2c";
6e050d4e JL	123	reg = <0x3000 0x100>;
6e050d4e JL	124	interrupts = <43 2>;
53f3945a XX	125	interrupt-parent = <&mpic>;
53f3945a XX	126	dfsrr;
c7d24a2d	127
6e050d4e	128	cs4270:codec@4f {
c7d24a2d	129	compatible = "cirrus,cs4270";
6e050d4e	130	reg = <0x4f>;
c7d24a2d	131	/* MCLK source is a stand-alone oscillator */
6e050d4e JL	132	clock-frequency = <12288000>;
6e050d4e JL	133	};
53f3945a XX	134	};
	135
	136	i2c@3100 {
53f3945a XX	137	#address-cells = <1>;
53f3945a XX	138	#size-cells = <0>;
ec9686c4 KG	139	cell-index = <1>;
ec9686c4 KG	140	compatible = "fsl-i2c";
6e050d4e JL	141	reg = <0x3100 0x100>;
6e050d4e JL	142	interrupts = <43 2>;
53f3945a XX	143	interrupt-parent = <&mpic>;
	144	dfsrr;
	145	};
	146
ea082fa9 KG	147	serial0: serial@4500 {
ea082fa9 KG	148	cell-index = <0>;
53f3945a XX	149	device_type = "serial";
53f3945a XX	150	compatible = "ns16550";
6e050d4e	151	reg = <0x4500 0x100>;
53f3945a	152	clock-frequency = <0>;
6e050d4e	153	interrupts = <42 2>;
53f3945a XX	154	interrupt-parent = <&mpic>;
	155	};
	156
ea082fa9 KG	157	serial1: serial@4600 {
ea082fa9 KG	158	cell-index = <1>;
53f3945a XX	159	device_type = "serial";
53f3945a XX	160	compatible = "ns16550";
6e050d4e	161	reg = <0x4600 0x100>;
53f3945a	162	clock-frequency = <0>;
aecb2b6e	163	interrupts = <42 2>;
53f3945a XX	164	interrupt-parent = <&mpic>;
	165	};
	166
9b53a9e2 YS	167	display@2c000 {
	168	compatible = "fsl,diu";
	169	reg = <0x2c000 100>;
	170	interrupts = <72 2>;
	171	interrupt-parent = <&mpic>;
	172	};
	173
53f3945a	174	mpic: interrupt-controller@40000 {
53f3945a XX	175	interrupt-controller;
	176	#address-cells = <0>;
	177	#interrupt-cells = <2>;
6e050d4e	178	reg = <0x40000 0x40000>;
53f3945a XX	179	compatible = "chrp,open-pic";
53f3945a XX	180	device_type = "open-pic";
53f3945a XX	181	};
53f3945a XX	182
0023352f JJ	183	msi@41600 {
	184	compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
	185	reg = <0x41600 0x80>;
	186	msi-available-ranges = <0 0x100>;
	187	interrupts = <
	188	0xe0 0
	189	0xe1 0
	190	0xe2 0
	191	0xe3 0
	192	0xe4 0
	193	0xe5 0
	194	0xe6 0
	195	0xe7 0>;
	196	interrupt-parent = <&mpic>;
	197	};
	198
53f3945a XX	199	global-utilities@e0000 {
53f3945a XX	200	compatible = "fsl,mpc8610-guts";
6e050d4e	201	reg = <0xe0000 0x1000>;
53f3945a XX	202	fsl,has-rstcr;
53f3945a XX	203	};
c7d24a2d TT	204
	205	i2s@16000 {
	206	compatible = "fsl,mpc8610-ssi";
	207	cell-index = <0>;
6e050d4e	208	reg = <0x16000 0x100>;
c7d24a2d	209	interrupt-parent = <&mpic>;
6e050d4e	210	interrupts = <62 2>;
c7d24a2d TT	211	fsl,mode = "i2s-slave";
	212	codec-handle = <&cs4270>;
	213	};
	214
	215	ssi@16100 {
	216	compatible = "fsl,mpc8610-ssi";
	217	cell-index = <1>;
6e050d4e	218	reg = <0x16100 0x100>;
c7d24a2d	219	interrupt-parent = <&mpic>;
6e050d4e	220	interrupts = <63 2>;
c7d24a2d TT	221	};
c7d24a2d TT	222
6e050d4e JL	223	dma@21300 {
	224	#address-cells = <1>;
	225	#size-cells = <1>;
	226	compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
	227	cell-index = <0>;
	228	reg = <0x21300 0x4>; /* DMA general status register */
	229	ranges = <0x0 0x21100 0x200>;
c7d24a2d	230
6e050d4e	231	dma-channel@0 {
c7d24a2d TT	232	compatible = "fsl,mpc8610-dma-channel",
	233	"fsl,eloplus-dma-channel";
	234	cell-index = <0>;
6e050d4e	235	reg = <0x0 0x80>;
c7d24a2d	236	interrupt-parent = <&mpic>;
6e050d4e JL	237	interrupts = <20 2>;
	238	};
	239	dma-channel@1 {
c7d24a2d TT	240	compatible = "fsl,mpc8610-dma-channel",
	241	"fsl,eloplus-dma-channel";
	242	cell-index = <1>;
6e050d4e	243	reg = <0x80 0x80>;
c7d24a2d	244	interrupt-parent = <&mpic>;
6e050d4e JL	245	interrupts = <21 2>;
	246	};
	247	dma-channel@2 {
c7d24a2d TT	248	compatible = "fsl,mpc8610-dma-channel",
	249	"fsl,eloplus-dma-channel";
	250	cell-index = <2>;
6e050d4e	251	reg = <0x100 0x80>;
c7d24a2d	252	interrupt-parent = <&mpic>;
6e050d4e JL	253	interrupts = <22 2>;
	254	};
	255	dma-channel@3 {
c7d24a2d TT	256	compatible = "fsl,mpc8610-dma-channel",
	257	"fsl,eloplus-dma-channel";
	258	cell-index = <3>;
6e050d4e	259	reg = <0x180 0x80>;
c7d24a2d	260	interrupt-parent = <&mpic>;
6e050d4e JL	261	interrupts = <23 2>;
	262	};
	263	};
c7d24a2d	264
6e050d4e JL	265	dma@c300 {
	266	#address-cells = <1>;
	267	#size-cells = <1>;
9c8b28c2	268	compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
6e050d4e JL	269	cell-index = <1>;
	270	reg = <0xc300 0x4>; /* DMA general status register */
	271	ranges = <0x0 0xc100 0x200>;
c7d24a2d	272
6e050d4e	273	dma-channel@0 {
c7d24a2d	274	compatible = "fsl,mpc8610-dma-channel",
9c8b28c2	275	"fsl,eloplus-dma-channel";
c7d24a2d	276	cell-index = <0>;
6e050d4e	277	reg = <0x0 0x80>;
c7d24a2d	278	interrupt-parent = <&mpic>;
6e050d4e JL	279	interrupts = <60 2>;
	280	};
	281	dma-channel@1 {
c7d24a2d	282	compatible = "fsl,mpc8610-dma-channel",
9c8b28c2	283	"fsl,eloplus-dma-channel";
c7d24a2d	284	cell-index = <1>;
6e050d4e	285	reg = <0x80 0x80>;
c7d24a2d	286	interrupt-parent = <&mpic>;
6e050d4e JL	287	interrupts = <61 2>;
	288	};
	289	dma-channel@2 {
c7d24a2d	290	compatible = "fsl,mpc8610-dma-channel",
9c8b28c2	291	"fsl,eloplus-dma-channel";
c7d24a2d	292	cell-index = <2>;
6e050d4e	293	reg = <0x100 0x80>;
c7d24a2d	294	interrupt-parent = <&mpic>;
6e050d4e JL	295	interrupts = <62 2>;
	296	};
	297	dma-channel@3 {
c7d24a2d	298	compatible = "fsl,mpc8610-dma-channel",
9c8b28c2	299	"fsl,eloplus-dma-channel";
c7d24a2d	300	cell-index = <3>;
6e050d4e	301	reg = <0x180 0x80>;
c7d24a2d	302	interrupt-parent = <&mpic>;
6e050d4e JL	303	interrupts = <63 2>;
	304	};
	305	};
c7d24a2d	306
53f3945a XX	307	};
53f3945a XX	308
ea082fa9 KG	309	pci0: pci@e0008000 {
ea082fa9 KG	310	cell-index = <0>;
53f3945a XX	311	compatible = "fsl,mpc8610-pci";
	312	device_type = "pci";
	313	#interrupt-cells = <1>;
	314	#size-cells = <2>;
	315	#address-cells = <3>;
6e050d4e	316	reg = <0xe0008000 0x1000>;
53f3945a	317	bus-range = <0 0>;
6e050d4e JL	318	ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
	319	0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
	320	clock-frequency = <33333333>;
53f3945a	321	interrupt-parent = <&mpic>;
6e050d4e JL	322	interrupts = <24 2>;
6e050d4e JL	323	interrupt-map-mask = <0xf800 0 0 7>;
53f3945a XX	324	interrupt-map = <
53f3945a XX	325	/* IDSEL 0x11 */
6e050d4e JL	326	0x8800 0 0 1 &mpic 4 1
	327	0x8800 0 0 2 &mpic 5 1
	328	0x8800 0 0 3 &mpic 6 1
	329	0x8800 0 0 4 &mpic 7 1
53f3945a XX	330
53f3945a XX	331	/* IDSEL 0x12 */
6e050d4e JL	332	0x9000 0 0 1 &mpic 5 1
	333	0x9000 0 0 2 &mpic 6 1
	334	0x9000 0 0 3 &mpic 7 1
	335	0x9000 0 0 4 &mpic 4 1
53f3945a XX	336	>;
	337	};
	338
ea082fa9 KG	339	pci1: pcie@e000a000 {
ea082fa9 KG	340	cell-index = <1>;
53f3945a XX	341	compatible = "fsl,mpc8641-pcie";
	342	device_type = "pci";
	343	#interrupt-cells = <1>;
	344	#size-cells = <2>;
	345	#address-cells = <3>;
6e050d4e	346	reg = <0xe000a000 0x1000>;
53f3945a	347	bus-range = <1 3>;
6e050d4e JL	348	ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
	349	0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
	350	clock-frequency = <33333333>;
53f3945a	351	interrupt-parent = <&mpic>;
6e050d4e JL	352	interrupts = <26 2>;
6e050d4e JL	353	interrupt-map-mask = <0xf800 0 0 7>;
53f3945a XX	354
	355	interrupt-map = <
	356	/* IDSEL 0x1b */
6e050d4e	357	0xd800 0 0 1 &mpic 2 1
53f3945a XX	358
53f3945a XX	359	/* IDSEL 0x1c*/
6e050d4e JL	360	0xe000 0 0 1 &mpic 1 1
	361	0xe000 0 0 2 &mpic 1 1
	362	0xe000 0 0 3 &mpic 1 1
	363	0xe000 0 0 4 &mpic 1 1
53f3945a XX	364
53f3945a XX	365	/* IDSEL 0x1f */
deabeabf	366	0xf800 0 0 1 &mpic 3 2
6e050d4e	367	0xf800 0 0 2 &mpic 0 1
53f3945a XX	368	>;
	369
	370	pcie@0 {
	371	reg = <0 0 0 0 0>;
	372	#size-cells = <2>;
	373	#address-cells = <3>;
	374	device_type = "pci";
6e050d4e JL	375	ranges = <0x02000000 0x0 0xa0000000
	376	0x02000000 0x0 0xa0000000
	377	0x0 0x10000000
	378	0x01000000 0x0 0x00000000
	379	0x01000000 0x0 0x00000000
	380	0x0 0x00100000>;
53f3945a XX	381	uli1575@0 {
	382	reg = <0 0 0 0 0>;
	383	#size-cells = <2>;
	384	#address-cells = <3>;
6e050d4e JL	385	ranges = <0x02000000 0x0 0xa0000000
	386	0x02000000 0x0 0xa0000000
	387	0x0 0x10000000
	388	0x01000000 0x0 0x00000000
	389	0x01000000 0x0 0x00000000
	390	0x0 0x00100000>;
53f3945a XX	391	};
	392	};
	393	};
e598477a AV	394
	395	pci2: pcie@e0009000 {
	396	#address-cells = <3>;
	397	#size-cells = <2>;
	398	#interrupt-cells = <1>;
	399	device_type = "pci";
	400	compatible = "fsl,mpc8641-pcie";
	401	reg = <0xe0009000 0x00001000>;
	402	ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
	403	0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
	404	bus-range = <0 255>;
	405	interrupt-map-mask = <0xf800 0 0 7>;
	406	interrupt-map = <0x0000 0 0 1 &mpic 4 1
	407	0x0000 0 0 2 &mpic 5 1
	408	0x0000 0 0 3 &mpic 6 1
	409	0x0000 0 0 4 &mpic 7 1>;
	410	interrupt-parent = <&mpic>;
	411	interrupts = <25 2>;
	412	clock-frequency = <33333333>;
	413	};
53f3945a	414	};