[deliverable/linux.git] / arch / powerpc / boot / dts / mpc8610_hpcd.dts

/*
 * MPC8610 HPCD Device Tree Source
 *
 * Copyright 2007-2008 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under the terms of the GNU General Public License Version 2 as published
 * by the Free Software Foundation.
 */

/dts-v1/;

/ {
	model = "MPC8610HPCD";
	compatible = "fsl,MPC8610HPCD";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
		pci1 = &pci1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8610@0 {
			device_type = "cpu";
			reg = <0>;
			d-cache-line-size = <32>;
			i-cache-line-size = <32>;
			d-cache-size = <32768>;		// L1
			i-cache-size = <32768>;		// L1
			timebase-frequency = <0>;	// From uboot
			bus-frequency = <0>;		// From uboot
			clock-frequency = <0>;		// From uboot
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x20000000>;	// 512M at 0x0
	};

	soc@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		#interrupt-cells = <2>;
		device_type = "soc";
		compatible = "fsl,mpc8610-immr", "simple-bus";
		ranges = <0x0 0xe0000000 0x00100000>;
		reg = <0xe0000000 0x1000>;
		bus-frequency = <0>;

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;

			cs4270:codec@4f {
				compatible = "cirrus,cs4270";
				reg = <0x4f>;
				/* MCLK source is a stand-alone oscillator */
				clock-frequency = <12288000>;
			};
		};

		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4500 0x100>;
			clock-frequency = <0>;
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4600 0x100>;
			clock-frequency = <0>;
			interrupts = <28 2>;
			interrupt-parent = <&mpic>;
		};

		mpic: interrupt-controller@40000 {
			clock-frequency = <0>;
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x40000 0x40000>;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
			big-endian;
		};

		global-utilities@e0000 {
			compatible = "fsl,mpc8610-guts";
			reg = <0xe0000 0x1000>;
			fsl,has-rstcr;
		};

		i2s@16000 {
			compatible = "fsl,mpc8610-ssi";
			cell-index = <0>;
			reg = <0x16000 0x100>;
			interrupt-parent = <&mpic>;
			interrupts = <62 2>;
			fsl,mode = "i2s-slave";
			codec-handle = <&cs4270>;
		};

		ssi@16100 {
			compatible = "fsl,mpc8610-ssi";
			cell-index = <1>;
			reg = <0x16100 0x100>;
			interrupt-parent = <&mpic>;
			interrupts = <63 2>;
		};

		dma@21300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
			cell-index = <0>;
			reg = <0x21300 0x4>; /* DMA general status register */
			ranges = <0x0 0x21100 0x200>;

			dma-channel@0 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,eloplus-dma-channel";
				cell-index = <0>;
				reg = <0x0 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <20 2>;
			};
			dma-channel@1 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,eloplus-dma-channel";
				cell-index = <1>;
				reg = <0x80 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <21 2>;
			};
			dma-channel@2 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,eloplus-dma-channel";
				cell-index = <2>;
				reg = <0x100 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <22 2>;
			};
			dma-channel@3 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,eloplus-dma-channel";
				cell-index = <3>;
				reg = <0x180 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <23 2>;
			};
		};

		dma@c300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8610-dma", "fsl,mpc8540-dma";
			cell-index = <1>;
			reg = <0xc300 0x4>; /* DMA general status register */
			ranges = <0x0 0xc100 0x200>;

			dma-channel@0 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,mpc8540-dma-channel";
				cell-index = <0>;
				reg = <0x0 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <60 2>;
			};
			dma-channel@1 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,mpc8540-dma-channel";
				cell-index = <1>;
				reg = <0x80 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <61 2>;
			};
			dma-channel@2 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,mpc8540-dma-channel";
				cell-index = <2>;
				reg = <0x100 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <62 2>;
			};
			dma-channel@3 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,mpc8540-dma-channel";
				cell-index = <3>;
				reg = <0x180 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <63 2>;
			};
		};

	};

	pci0: pci@e0008000 {
		cell-index = <0>;
		compatible = "fsl,mpc8610-pci";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0008000 0x1000>;
		bus-range = <0 0>;
		ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
			  0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <24 2>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <
			/* IDSEL 0x11 */
			0x8800 0 0 1 &mpic 4 1
			0x8800 0 0 2 &mpic 5 1
			0x8800 0 0 3 &mpic 6 1
			0x8800 0 0 4 &mpic 7 1

			/* IDSEL 0x12 */
			0x9000 0 0 1 &mpic 5 1
			0x9000 0 0 2 &mpic 6 1
			0x9000 0 0 3 &mpic 7 1
			0x9000 0 0 4 &mpic 4 1
			>;
	};

	pci1: pcie@e000a000 {
		cell-index = <1>;
		compatible = "fsl,mpc8641-pcie";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe000a000 0x1000>;
		bus-range = <1 3>;
		ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
			  0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <26 2>;
		interrupt-map-mask = <0xf800 0 0 7>;

		interrupt-map = <
			/* IDSEL 0x1b */
			0xd800 0 0 1 &mpic 2 1

			/* IDSEL 0x1c*/
			0xe000 0 0 1 &mpic 1 1
			0xe000 0 0 2 &mpic 1 1
			0xe000 0 0 3 &mpic 1 1
			0xe000 0 0 4 &mpic 1 1

			/* IDSEL 0x1f */
			0xf800 0 0 1 &mpic 3 0
			0xf800 0 0 2 &mpic 0 1
		>;

		pcie@0 {
			reg = <0 0 0 0 0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x02000000 0x0 0xa0000000
				  0x02000000 0x0 0xa0000000
				  0x0 0x10000000
				  0x01000000 0x0 0x00000000
				  0x01000000 0x0 0x00000000
				  0x0 0x00100000>;
			uli1575@0 {
				reg = <0 0 0 0 0>;
				#size-cells = <2>;
				#address-cells = <3>;
				ranges = <0x02000000 0x0 0xa0000000
					  0x02000000 0x0 0xa0000000
					  0x0 0x10000000
					  0x01000000 0x0 0x00000000
					  0x01000000 0x0 0x00000000
					  0x0 0x00100000>;
			};
		};
	};
};
Commit	Line	Data
53f3945a XX	1	/*
	2	* MPC8610 HPCD Device Tree Source
	3	*
c7d24a2d	4	* Copyright 2007-2008 Freescale Semiconductor Inc.
53f3945a XX	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License Version 2 as published
	8	* by the Free Software Foundation.
	9	*/
	10
6e050d4e	11	/dts-v1/;
53f3945a XX	12
	13	/ {
	14	model = "MPC8610HPCD";
	15	compatible = "fsl,MPC8610HPCD";
	16	#address-cells = <1>;
	17	#size-cells = <1>;
	18
ea082fa9 KG	19	aliases {
	20	serial0 = &serial0;
	21	serial1 = &serial1;
	22	pci0 = &pci0;
	23	pci1 = &pci1;
	24	};
	25
53f3945a XX	26	cpus {
	27	#address-cells = <1>;
	28	#size-cells = <0>;
	29
	30	PowerPC,8610@0 {
	31	device_type = "cpu";
	32	reg = <0>;
6e050d4e JL	33	d-cache-line-size = <32>;
	34	i-cache-line-size = <32>;
	35	d-cache-size = <32768>; // L1
	36	i-cache-size = <32768>; // L1
	37	timebase-frequency = <0>; // From uboot
53f3945a XX	38	bus-frequency = <0>; // From uboot
	39	clock-frequency = <0>; // From uboot
	40	};
	41	};
	42
	43	memory {
	44	device_type = "memory";
6e050d4e	45	reg = <0x00000000 0x20000000>; // 512M at 0x0
53f3945a XX	46	};
	47
	48	soc@e0000000 {
	49	#address-cells = <1>;
	50	#size-cells = <1>;
	51	#interrupt-cells = <2>;
	52	device_type = "soc";
c7d24a2d	53	compatible = "fsl,mpc8610-immr", "simple-bus";
6e050d4e JL	54	ranges = <0x0 0xe0000000 0x00100000>;
6e050d4e JL	55	reg = <0xe0000000 0x1000>;
53f3945a XX	56	bus-frequency = <0>;
	57
	58	i2c@3000 {
53f3945a XX	59	#address-cells = <1>;
53f3945a XX	60	#size-cells = <0>;
ec9686c4 KG	61	cell-index = <0>;
ec9686c4 KG	62	compatible = "fsl-i2c";
6e050d4e JL	63	reg = <0x3000 0x100>;
6e050d4e JL	64	interrupts = <43 2>;
53f3945a XX	65	interrupt-parent = <&mpic>;
53f3945a XX	66	dfsrr;
c7d24a2d	67
6e050d4e	68	cs4270:codec@4f {
c7d24a2d	69	compatible = "cirrus,cs4270";
6e050d4e	70	reg = <0x4f>;
c7d24a2d	71	/* MCLK source is a stand-alone oscillator */
6e050d4e JL	72	clock-frequency = <12288000>;
6e050d4e JL	73	};
53f3945a XX	74	};
	75
	76	i2c@3100 {
53f3945a XX	77	#address-cells = <1>;
53f3945a XX	78	#size-cells = <0>;
ec9686c4 KG	79	cell-index = <1>;
ec9686c4 KG	80	compatible = "fsl-i2c";
6e050d4e JL	81	reg = <0x3100 0x100>;
6e050d4e JL	82	interrupts = <43 2>;
53f3945a XX	83	interrupt-parent = <&mpic>;
	84	dfsrr;
	85	};
	86
ea082fa9 KG	87	serial0: serial@4500 {
ea082fa9 KG	88	cell-index = <0>;
53f3945a XX	89	device_type = "serial";
53f3945a XX	90	compatible = "ns16550";
6e050d4e	91	reg = <0x4500 0x100>;
53f3945a	92	clock-frequency = <0>;
6e050d4e	93	interrupts = <42 2>;
53f3945a XX	94	interrupt-parent = <&mpic>;
	95	};
	96
ea082fa9 KG	97	serial1: serial@4600 {
ea082fa9 KG	98	cell-index = <1>;
53f3945a XX	99	device_type = "serial";
53f3945a XX	100	compatible = "ns16550";
6e050d4e	101	reg = <0x4600 0x100>;
53f3945a	102	clock-frequency = <0>;
6e050d4e	103	interrupts = <28 2>;
53f3945a XX	104	interrupt-parent = <&mpic>;
	105	};
	106
53f3945a XX	107	mpic: interrupt-controller@40000 {
	108	clock-frequency = <0>;
	109	interrupt-controller;
	110	#address-cells = <0>;
	111	#interrupt-cells = <2>;
6e050d4e	112	reg = <0x40000 0x40000>;
53f3945a XX	113	compatible = "chrp,open-pic";
	114	device_type = "open-pic";
	115	big-endian;
	116	};
	117
	118	global-utilities@e0000 {
	119	compatible = "fsl,mpc8610-guts";
6e050d4e	120	reg = <0xe0000 0x1000>;
53f3945a XX	121	fsl,has-rstcr;
53f3945a XX	122	};
c7d24a2d TT	123
	124	i2s@16000 {
	125	compatible = "fsl,mpc8610-ssi";
	126	cell-index = <0>;
6e050d4e	127	reg = <0x16000 0x100>;
c7d24a2d	128	interrupt-parent = <&mpic>;
6e050d4e	129	interrupts = <62 2>;
c7d24a2d TT	130	fsl,mode = "i2s-slave";
	131	codec-handle = <&cs4270>;
	132	};
	133
	134	ssi@16100 {
	135	compatible = "fsl,mpc8610-ssi";
	136	cell-index = <1>;
6e050d4e	137	reg = <0x16100 0x100>;
c7d24a2d	138	interrupt-parent = <&mpic>;
6e050d4e	139	interrupts = <63 2>;
c7d24a2d TT	140	};
c7d24a2d TT	141
6e050d4e JL	142	dma@21300 {
	143	#address-cells = <1>;
	144	#size-cells = <1>;
	145	compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
	146	cell-index = <0>;
	147	reg = <0x21300 0x4>; /* DMA general status register */
	148	ranges = <0x0 0x21100 0x200>;
c7d24a2d	149
6e050d4e	150	dma-channel@0 {
c7d24a2d TT	151	compatible = "fsl,mpc8610-dma-channel",
	152	"fsl,eloplus-dma-channel";
	153	cell-index = <0>;
6e050d4e	154	reg = <0x0 0x80>;
c7d24a2d	155	interrupt-parent = <&mpic>;
6e050d4e JL	156	interrupts = <20 2>;
	157	};
	158	dma-channel@1 {
c7d24a2d TT	159	compatible = "fsl,mpc8610-dma-channel",
	160	"fsl,eloplus-dma-channel";
	161	cell-index = <1>;
6e050d4e	162	reg = <0x80 0x80>;
c7d24a2d	163	interrupt-parent = <&mpic>;
6e050d4e JL	164	interrupts = <21 2>;
	165	};
	166	dma-channel@2 {
c7d24a2d TT	167	compatible = "fsl,mpc8610-dma-channel",
	168	"fsl,eloplus-dma-channel";
	169	cell-index = <2>;
6e050d4e	170	reg = <0x100 0x80>;
c7d24a2d	171	interrupt-parent = <&mpic>;
6e050d4e JL	172	interrupts = <22 2>;
	173	};
	174	dma-channel@3 {
c7d24a2d TT	175	compatible = "fsl,mpc8610-dma-channel",
	176	"fsl,eloplus-dma-channel";
	177	cell-index = <3>;
6e050d4e	178	reg = <0x180 0x80>;
c7d24a2d	179	interrupt-parent = <&mpic>;
6e050d4e JL	180	interrupts = <23 2>;
	181	};
	182	};
c7d24a2d	183
6e050d4e JL	184	dma@c300 {
	185	#address-cells = <1>;
	186	#size-cells = <1>;
	187	compatible = "fsl,mpc8610-dma", "fsl,mpc8540-dma";
	188	cell-index = <1>;
	189	reg = <0xc300 0x4>; /* DMA general status register */
	190	ranges = <0x0 0xc100 0x200>;
c7d24a2d	191
6e050d4e	192	dma-channel@0 {
c7d24a2d TT	193	compatible = "fsl,mpc8610-dma-channel",
	194	"fsl,mpc8540-dma-channel";
	195	cell-index = <0>;
6e050d4e	196	reg = <0x0 0x80>;
c7d24a2d	197	interrupt-parent = <&mpic>;
6e050d4e JL	198	interrupts = <60 2>;
	199	};
	200	dma-channel@1 {
c7d24a2d TT	201	compatible = "fsl,mpc8610-dma-channel",
	202	"fsl,mpc8540-dma-channel";
	203	cell-index = <1>;
6e050d4e	204	reg = <0x80 0x80>;
c7d24a2d	205	interrupt-parent = <&mpic>;
6e050d4e JL	206	interrupts = <61 2>;
	207	};
	208	dma-channel@2 {
c7d24a2d TT	209	compatible = "fsl,mpc8610-dma-channel",
	210	"fsl,mpc8540-dma-channel";
	211	cell-index = <2>;
6e050d4e	212	reg = <0x100 0x80>;
c7d24a2d	213	interrupt-parent = <&mpic>;
6e050d4e JL	214	interrupts = <62 2>;
	215	};
	216	dma-channel@3 {
c7d24a2d TT	217	compatible = "fsl,mpc8610-dma-channel",
	218	"fsl,mpc8540-dma-channel";
	219	cell-index = <3>;
6e050d4e	220	reg = <0x180 0x80>;
c7d24a2d	221	interrupt-parent = <&mpic>;
6e050d4e JL	222	interrupts = <63 2>;
	223	};
	224	};
c7d24a2d	225
53f3945a XX	226	};
53f3945a XX	227
ea082fa9 KG	228	pci0: pci@e0008000 {
ea082fa9 KG	229	cell-index = <0>;
53f3945a XX	230	compatible = "fsl,mpc8610-pci";
	231	device_type = "pci";
	232	#interrupt-cells = <1>;
	233	#size-cells = <2>;
	234	#address-cells = <3>;
6e050d4e	235	reg = <0xe0008000 0x1000>;
53f3945a	236	bus-range = <0 0>;
6e050d4e JL	237	ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
	238	0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
	239	clock-frequency = <33333333>;
53f3945a	240	interrupt-parent = <&mpic>;
6e050d4e JL	241	interrupts = <24 2>;
6e050d4e JL	242	interrupt-map-mask = <0xf800 0 0 7>;
53f3945a XX	243	interrupt-map = <
53f3945a XX	244	/* IDSEL 0x11 */
6e050d4e JL	245	0x8800 0 0 1 &mpic 4 1
	246	0x8800 0 0 2 &mpic 5 1
	247	0x8800 0 0 3 &mpic 6 1
	248	0x8800 0 0 4 &mpic 7 1
53f3945a XX	249
53f3945a XX	250	/* IDSEL 0x12 */
6e050d4e JL	251	0x9000 0 0 1 &mpic 5 1
	252	0x9000 0 0 2 &mpic 6 1
	253	0x9000 0 0 3 &mpic 7 1
	254	0x9000 0 0 4 &mpic 4 1
53f3945a XX	255	>;
	256	};
	257
ea082fa9 KG	258	pci1: pcie@e000a000 {
ea082fa9 KG	259	cell-index = <1>;
53f3945a XX	260	compatible = "fsl,mpc8641-pcie";
	261	device_type = "pci";
	262	#interrupt-cells = <1>;
	263	#size-cells = <2>;
	264	#address-cells = <3>;
6e050d4e	265	reg = <0xe000a000 0x1000>;
53f3945a	266	bus-range = <1 3>;
6e050d4e JL	267	ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
	268	0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
	269	clock-frequency = <33333333>;
53f3945a	270	interrupt-parent = <&mpic>;
6e050d4e JL	271	interrupts = <26 2>;
6e050d4e JL	272	interrupt-map-mask = <0xf800 0 0 7>;
53f3945a XX	273
	274	interrupt-map = <
	275	/* IDSEL 0x1b */
6e050d4e	276	0xd800 0 0 1 &mpic 2 1
53f3945a XX	277
53f3945a XX	278	/* IDSEL 0x1c*/
6e050d4e JL	279	0xe000 0 0 1 &mpic 1 1
	280	0xe000 0 0 2 &mpic 1 1
	281	0xe000 0 0 3 &mpic 1 1
	282	0xe000 0 0 4 &mpic 1 1
53f3945a XX	283
53f3945a XX	284	/* IDSEL 0x1f */
6e050d4e JL	285	0xf800 0 0 1 &mpic 3 0
6e050d4e JL	286	0xf800 0 0 2 &mpic 0 1
53f3945a XX	287	>;
	288
	289	pcie@0 {
	290	reg = <0 0 0 0 0>;
	291	#size-cells = <2>;
	292	#address-cells = <3>;
	293	device_type = "pci";
6e050d4e JL	294	ranges = <0x02000000 0x0 0xa0000000
	295	0x02000000 0x0 0xa0000000
	296	0x0 0x10000000
	297	0x01000000 0x0 0x00000000
	298	0x01000000 0x0 0x00000000
	299	0x0 0x00100000>;
53f3945a XX	300	uli1575@0 {
	301	reg = <0 0 0 0 0>;
	302	#size-cells = <2>;
	303	#address-cells = <3>;
6e050d4e JL	304	ranges = <0x02000000 0x0 0xa0000000
	305	0x02000000 0x0 0xa0000000
	306	0x0 0x10000000
	307	0x01000000 0x0 0x00000000
	308	0x01000000 0x0 0x00000000
	309	0x0 0x00100000>;
53f3945a XX	310	};
	311	};
	312	};
	313	};