[deliverable/linux.git] / arch / powerpc / boot / dts / mpc8610_hpcd.dts

/*
 * MPC8610 HPCD Device Tree Source
 *
 * Copyright 2007-2008 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under the terms of the GNU General Public License Version 2 as published
 * by the Free Software Foundation.
 */

/dts-v1/;

/ {
	model = "MPC8610HPCD";
	compatible = "fsl,MPC8610HPCD";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
		pci1 = &pci1;
		pci2 = &pci2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8610@0 {
			device_type = "cpu";
			reg = <0>;
			d-cache-line-size = <32>;
			i-cache-line-size = <32>;
			d-cache-size = <32768>;		// L1
			i-cache-size = <32768>;		// L1
			timebase-frequency = <0>;	// From uboot
			bus-frequency = <0>;		// From uboot
			clock-frequency = <0>;		// From uboot
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x20000000>;	// 512M at 0x0
	};

	localbus@e0005000 {
		#address-cells = <2>;
		#size-cells = <1>;
		compatible = "fsl,mpc8610-elbc", "fsl,elbc", "simple-bus";
		reg = <0xe0005000 0x1000>;
		interrupts = <19 2>;
		interrupt-parent = <&mpic>;
		ranges = <0 0 0xf8000000 0x08000000
			  1 0 0xf0000000 0x08000000
			  2 0 0xe8400000 0x00008000
			  4 0 0xe8440000 0x00008000
			  5 0 0xe8480000 0x00008000
			  6 0 0xe84c0000 0x00008000
			  3 0 0xe8000000 0x00000020>;

		flash@0,0 {
			compatible = "cfi-flash";
			reg = <0 0 0x8000000>;
			bank-width = <2>;
			device-width = <1>;
		};

		flash@1,0 {
			compatible = "cfi-flash";
			reg = <1 0 0x8000000>;
			bank-width = <2>;
			device-width = <1>;
		};

		flash@2,0 {
			compatible = "fsl,mpc8610-fcm-nand",
				     "fsl,elbc-fcm-nand";
			reg = <2 0 0x8000>;
		};

		flash@4,0 {
			compatible = "fsl,mpc8610-fcm-nand",
				     "fsl,elbc-fcm-nand";
			reg = <4 0 0x8000>;
		};

		flash@5,0 {
			compatible = "fsl,mpc8610-fcm-nand",
				     "fsl,elbc-fcm-nand";
			reg = <5 0 0x8000>;
		};

		flash@6,0 {
			compatible = "fsl,mpc8610-fcm-nand",
				     "fsl,elbc-fcm-nand";
			reg = <6 0 0x8000>;
		};

		board-control@3,0 {
			compatible = "fsl,fpga-pixis";
			reg = <3 0 0x20>;
		};
	};

	soc@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		#interrupt-cells = <2>;
		device_type = "soc";
		compatible = "fsl,mpc8610-immr", "simple-bus";
		ranges = <0x0 0xe0000000 0x00100000>;
		bus-frequency = <0>;

		mcm-law@0 {
			compatible = "fsl,mcm-law";
			reg = <0x0 0x1000>;
			fsl,num-laws = <10>;
		};

		mcm@1000 {
			compatible = "fsl,mpc8610-mcm", "fsl,mcm";
			reg = <0x1000 0x1000>;
			interrupts = <17 2>;
			interrupt-parent = <&mpic>;
		};

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;

			cs4270:codec@4f {
				compatible = "cirrus,cs4270";
				reg = <0x4f>;
				/* MCLK source is a stand-alone oscillator */
				clock-frequency = <12288000>;
			};
		};

		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4500 0x100>;
			clock-frequency = <0>;
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4600 0x100>;
			clock-frequency = <0>;
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		display@2c000 {
			compatible = "fsl,diu";
			reg = <0x2c000 100>;
			interrupts = <72 2>;
			interrupt-parent = <&mpic>;
		};

		mpic: interrupt-controller@40000 {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x40000 0x40000>;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
		};

		msi@41600 {
			compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
			reg = <0x41600 0x80>;
			msi-available-ranges = <0 0x100>;
			interrupts = <
				0xe0 0
				0xe1 0
				0xe2 0
				0xe3 0
				0xe4 0
				0xe5 0
				0xe6 0
				0xe7 0>;
			interrupt-parent = <&mpic>;
		};

		global-utilities@e0000 {
			compatible = "fsl,mpc8610-guts";
			reg = <0xe0000 0x1000>;
			fsl,has-rstcr;
		};

		wdt@e4000 {
			compatible = "fsl,mpc8610-wdt";
			reg = <0xe4000 0x100>;
		};

		ssi@16000 {
			compatible = "fsl,mpc8610-ssi";
			cell-index = <0>;
			reg = <0x16000 0x100>;
			interrupt-parent = <&mpic>;
			interrupts = <62 2>;
			fsl,mode = "i2s-slave";
			codec-handle = <&cs4270>;
			fsl,playback-dma = <&dma00>;
			fsl,capture-dma = <&dma01>;
			fsl,fifo-depth = <8>;
		};

		ssi@16100 {
			compatible = "fsl,mpc8610-ssi";
			cell-index = <1>;
			reg = <0x16100 0x100>;
			interrupt-parent = <&mpic>;
			interrupts = <63 2>;
			fsl,fifo-depth = <8>;
		};

		dma@21300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
			cell-index = <0>;
			reg = <0x21300 0x4>; /* DMA general status register */
			ranges = <0x0 0x21100 0x200>;

			dma00: dma-channel@0 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,ssi-dma-channel";
				cell-index = <0>;
				reg = <0x0 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <20 2>;
			};
			dma01: dma-channel@1 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,ssi-dma-channel";
				cell-index = <1>;
				reg = <0x80 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <21 2>;
			};
			dma-channel@2 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,eloplus-dma-channel";
				cell-index = <2>;
				reg = <0x100 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <22 2>;
			};
			dma-channel@3 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,eloplus-dma-channel";
				cell-index = <3>;
				reg = <0x180 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <23 2>;
			};
		};

		dma@c300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
			cell-index = <1>;
			reg = <0xc300 0x4>; /* DMA general status register */
			ranges = <0x0 0xc100 0x200>;

			dma-channel@0 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,eloplus-dma-channel";
				cell-index = <0>;
				reg = <0x0 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <76 2>;
			};
			dma-channel@1 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,eloplus-dma-channel";
				cell-index = <1>;
				reg = <0x80 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <77 2>;
			};
			dma-channel@2 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,eloplus-dma-channel";
				cell-index = <2>;
				reg = <0x100 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <78 2>;
			};
			dma-channel@3 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,eloplus-dma-channel";
				cell-index = <3>;
				reg = <0x180 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <79 2>;
			};
		};

	};

	pci0: pci@e0008000 {
		compatible = "fsl,mpc8610-pci";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0008000 0x1000>;
		bus-range = <0 0>;
		ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
			  0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <24 2>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <
			/* IDSEL 0x11 */
			0x8800 0 0 1 &mpic 4 1
			0x8800 0 0 2 &mpic 5 1
			0x8800 0 0 3 &mpic 6 1
			0x8800 0 0 4 &mpic 7 1

			/* IDSEL 0x12 */
			0x9000 0 0 1 &mpic 5 1
			0x9000 0 0 2 &mpic 6 1
			0x9000 0 0 3 &mpic 7 1
			0x9000 0 0 4 &mpic 4 1
			>;
	};

	pci1: pcie@e000a000 {
		compatible = "fsl,mpc8641-pcie";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe000a000 0x1000>;
		bus-range = <1 3>;
		ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
			  0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <26 2>;
		interrupt-map-mask = <0xf800 0 0 7>;

		interrupt-map = <
			/* IDSEL 0x1b */
			0xd800 0 0 1 &mpic 2 1

			/* IDSEL 0x1c*/
			0xe000 0 0 1 &mpic 1 1
			0xe000 0 0 2 &mpic 1 1
			0xe000 0 0 3 &mpic 1 1
			0xe000 0 0 4 &mpic 1 1

			/* IDSEL 0x1f */
			0xf800 0 0 1 &mpic 3 2
			0xf800 0 0 2 &mpic 0 1
		>;

		pcie@0 {
			reg = <0 0 0 0 0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x02000000 0x0 0xa0000000
				  0x02000000 0x0 0xa0000000
				  0x0 0x10000000
				  0x01000000 0x0 0x00000000
				  0x01000000 0x0 0x00000000
				  0x0 0x00100000>;
			uli1575@0 {
				reg = <0 0 0 0 0>;
				#size-cells = <2>;
				#address-cells = <3>;
				ranges = <0x02000000 0x0 0xa0000000
					  0x02000000 0x0 0xa0000000
					  0x0 0x10000000
					  0x01000000 0x0 0x00000000
					  0x01000000 0x0 0x00000000
					  0x0 0x00100000>;

				isa@1e {
					device_type = "isa";
					#size-cells = <1>;
					#address-cells = <2>;
					reg = <0xf000 0 0 0 0>;
					ranges = <1 0 0x01000000 0 0
						  0x00001000>;

					rtc@70 {
						compatible = "pnpPNP,b00";
						reg = <1 0x70 2>;
					};
				};
			};
		};
	};

	pci2: pcie@e0009000 {
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		device_type = "pci";
		compatible = "fsl,mpc8641-pcie";
		reg = <0xe0009000 0x00001000>;
		ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
			  0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
		bus-range = <0 255>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <0x0000 0 0 1 &mpic 4 1
				 0x0000 0 0 2 &mpic 5 1
				 0x0000 0 0 3 &mpic 6 1
				 0x0000 0 0 4 &mpic 7 1>;
		interrupt-parent = <&mpic>;
		interrupts = <25 2>;
		clock-frequency = <33333333>;
	};
};
Commit	Line	Data
53f3945a XX	1	/*
	2	* MPC8610 HPCD Device Tree Source
	3	*
c7d24a2d	4	* Copyright 2007-2008 Freescale Semiconductor Inc.
53f3945a XX	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License Version 2 as published
	8	* by the Free Software Foundation.
	9	*/
	10
6e050d4e	11	/dts-v1/;
53f3945a XX	12
	13	/ {
	14	model = "MPC8610HPCD";
	15	compatible = "fsl,MPC8610HPCD";
	16	#address-cells = <1>;
	17	#size-cells = <1>;
	18
ea082fa9 KG	19	aliases {
	20	serial0 = &serial0;
	21	serial1 = &serial1;
	22	pci0 = &pci0;
	23	pci1 = &pci1;
e598477a	24	pci2 = &pci2;
ea082fa9 KG	25	};
ea082fa9 KG	26
53f3945a XX	27	cpus {
	28	#address-cells = <1>;
	29	#size-cells = <0>;
	30
	31	PowerPC,8610@0 {
	32	device_type = "cpu";
	33	reg = <0>;
6e050d4e JL	34	d-cache-line-size = <32>;
	35	i-cache-line-size = <32>;
	36	d-cache-size = <32768>; // L1
	37	i-cache-size = <32768>; // L1
	38	timebase-frequency = <0>; // From uboot
53f3945a XX	39	bus-frequency = <0>; // From uboot
	40	clock-frequency = <0>; // From uboot
	41	};
	42	};
	43
	44	memory {
	45	device_type = "memory";
6e050d4e	46	reg = <0x00000000 0x20000000>; // 512M at 0x0
53f3945a XX	47	};
53f3945a XX	48
34b4a873 AV	49	localbus@e0005000 {
	50	#address-cells = <2>;
	51	#size-cells = <1>;
	52	compatible = "fsl,mpc8610-elbc", "fsl,elbc", "simple-bus";
	53	reg = <0xe0005000 0x1000>;
	54	interrupts = <19 2>;
	55	interrupt-parent = <&mpic>;
	56	ranges = <0 0 0xf8000000 0x08000000
	57	1 0 0xf0000000 0x08000000
	58	2 0 0xe8400000 0x00008000
	59	4 0 0xe8440000 0x00008000
	60	5 0 0xe8480000 0x00008000
	61	6 0 0xe84c0000 0x00008000
	62	3 0 0xe8000000 0x00000020>;
	63
	64	flash@0,0 {
	65	compatible = "cfi-flash";
	66	reg = <0 0 0x8000000>;
	67	bank-width = <2>;
	68	device-width = <1>;
	69	};
	70
	71	flash@1,0 {
	72	compatible = "cfi-flash";
	73	reg = <1 0 0x8000000>;
	74	bank-width = <2>;
	75	device-width = <1>;
	76	};
	77
	78	flash@2,0 {
	79	compatible = "fsl,mpc8610-fcm-nand",
	80	"fsl,elbc-fcm-nand";
	81	reg = <2 0 0x8000>;
	82	};
	83
	84	flash@4,0 {
	85	compatible = "fsl,mpc8610-fcm-nand",
	86	"fsl,elbc-fcm-nand";
	87	reg = <4 0 0x8000>;
	88	};
	89
	90	flash@5,0 {
	91	compatible = "fsl,mpc8610-fcm-nand",
	92	"fsl,elbc-fcm-nand";
	93	reg = <5 0 0x8000>;
	94	};
	95
	96	flash@6,0 {
	97	compatible = "fsl,mpc8610-fcm-nand",
	98	"fsl,elbc-fcm-nand";
	99	reg = <6 0 0x8000>;
	100	};
	101
	102	board-control@3,0 {
	103	compatible = "fsl,fpga-pixis";
	104	reg = <3 0 0x20>;
	105	};
9b53a9e2 YS	106	};
9b53a9e2 YS	107
53f3945a XX	108	soc@e0000000 {
	109	#address-cells = <1>;
	110	#size-cells = <1>;
	111	#interrupt-cells = <2>;
	112	device_type = "soc";
c7d24a2d	113	compatible = "fsl,mpc8610-immr", "simple-bus";
6e050d4e	114	ranges = <0x0 0xe0000000 0x00100000>;
53f3945a XX	115	bus-frequency = <0>;
53f3945a XX	116
da385780 KG	117	mcm-law@0 {
	118	compatible = "fsl,mcm-law";
	119	reg = <0x0 0x1000>;
	120	fsl,num-laws = <10>;
	121	};
	122
	123	mcm@1000 {
	124	compatible = "fsl,mpc8610-mcm", "fsl,mcm";
	125	reg = <0x1000 0x1000>;
	126	interrupts = <17 2>;
	127	interrupt-parent = <&mpic>;
	128	};
	129
53f3945a	130	i2c@3000 {
53f3945a XX	131	#address-cells = <1>;
53f3945a XX	132	#size-cells = <0>;
ec9686c4 KG	133	cell-index = <0>;
ec9686c4 KG	134	compatible = "fsl-i2c";
6e050d4e JL	135	reg = <0x3000 0x100>;
6e050d4e JL	136	interrupts = <43 2>;
53f3945a XX	137	interrupt-parent = <&mpic>;
53f3945a XX	138	dfsrr;
c7d24a2d	139
6e050d4e	140	cs4270:codec@4f {
c7d24a2d	141	compatible = "cirrus,cs4270";
6e050d4e	142	reg = <0x4f>;
c7d24a2d	143	/* MCLK source is a stand-alone oscillator */
6e050d4e JL	144	clock-frequency = <12288000>;
6e050d4e JL	145	};
53f3945a XX	146	};
	147
	148	i2c@3100 {
53f3945a XX	149	#address-cells = <1>;
53f3945a XX	150	#size-cells = <0>;
ec9686c4 KG	151	cell-index = <1>;
ec9686c4 KG	152	compatible = "fsl-i2c";
6e050d4e JL	153	reg = <0x3100 0x100>;
6e050d4e JL	154	interrupts = <43 2>;
53f3945a XX	155	interrupt-parent = <&mpic>;
	156	dfsrr;
	157	};
	158
ea082fa9 KG	159	serial0: serial@4500 {
ea082fa9 KG	160	cell-index = <0>;
53f3945a XX	161	device_type = "serial";
53f3945a XX	162	compatible = "ns16550";
6e050d4e	163	reg = <0x4500 0x100>;
53f3945a	164	clock-frequency = <0>;
6e050d4e	165	interrupts = <42 2>;
53f3945a XX	166	interrupt-parent = <&mpic>;
	167	};
	168
ea082fa9 KG	169	serial1: serial@4600 {
ea082fa9 KG	170	cell-index = <1>;
53f3945a XX	171	device_type = "serial";
53f3945a XX	172	compatible = "ns16550";
6e050d4e	173	reg = <0x4600 0x100>;
53f3945a	174	clock-frequency = <0>;
aecb2b6e	175	interrupts = <42 2>;
53f3945a XX	176	interrupt-parent = <&mpic>;
	177	};
	178
9b53a9e2 YS	179	display@2c000 {
	180	compatible = "fsl,diu";
	181	reg = <0x2c000 100>;
	182	interrupts = <72 2>;
	183	interrupt-parent = <&mpic>;
	184	};
	185
53f3945a	186	mpic: interrupt-controller@40000 {
53f3945a XX	187	interrupt-controller;
	188	#address-cells = <0>;
	189	#interrupt-cells = <2>;
6e050d4e	190	reg = <0x40000 0x40000>;
53f3945a XX	191	compatible = "chrp,open-pic";
53f3945a XX	192	device_type = "open-pic";
53f3945a XX	193	};
53f3945a XX	194
0023352f JJ	195	msi@41600 {
	196	compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
	197	reg = <0x41600 0x80>;
	198	msi-available-ranges = <0 0x100>;
	199	interrupts = <
	200	0xe0 0
	201	0xe1 0
	202	0xe2 0
	203	0xe3 0
	204	0xe4 0
	205	0xe5 0
	206	0xe6 0
	207	0xe7 0>;
	208	interrupt-parent = <&mpic>;
	209	};
	210
53f3945a XX	211	global-utilities@e0000 {
53f3945a XX	212	compatible = "fsl,mpc8610-guts";
6e050d4e	213	reg = <0xe0000 0x1000>;
53f3945a XX	214	fsl,has-rstcr;
53f3945a XX	215	};
c7d24a2d	216
775587b6 AV	217	wdt@e4000 {
	218	compatible = "fsl,mpc8610-wdt";
	219	reg = <0xe4000 0x100>;
	220	};
	221
c2fe5944	222	ssi@16000 {
c7d24a2d TT	223	compatible = "fsl,mpc8610-ssi";
c7d24a2d TT	224	cell-index = <0>;
6e050d4e	225	reg = <0x16000 0x100>;
c7d24a2d	226	interrupt-parent = <&mpic>;
6e050d4e	227	interrupts = <62 2>;
c7d24a2d TT	228	fsl,mode = "i2s-slave";
c7d24a2d TT	229	codec-handle = <&cs4270>;
c2fe5944 TT	230	fsl,playback-dma = <&dma00>;
c2fe5944 TT	231	fsl,capture-dma = <&dma01>;
0bcd783c	232	fsl,fifo-depth = <8>;
c7d24a2d TT	233	};
	234
	235	ssi@16100 {
	236	compatible = "fsl,mpc8610-ssi";
	237	cell-index = <1>;
6e050d4e	238	reg = <0x16100 0x100>;
c7d24a2d	239	interrupt-parent = <&mpic>;
6e050d4e	240	interrupts = <63 2>;
0bcd783c	241	fsl,fifo-depth = <8>;
c7d24a2d TT	242	};
c7d24a2d TT	243
6e050d4e JL	244	dma@21300 {
	245	#address-cells = <1>;
	246	#size-cells = <1>;
	247	compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
	248	cell-index = <0>;
	249	reg = <0x21300 0x4>; /* DMA general status register */
	250	ranges = <0x0 0x21100 0x200>;
c7d24a2d	251
c2fe5944	252	dma00: dma-channel@0 {
c7d24a2d	253	compatible = "fsl,mpc8610-dma-channel",
7de0c22b	254	"fsl,ssi-dma-channel";
c7d24a2d	255	cell-index = <0>;
6e050d4e	256	reg = <0x0 0x80>;
c7d24a2d	257	interrupt-parent = <&mpic>;
6e050d4e JL	258	interrupts = <20 2>;
6e050d4e JL	259	};
c2fe5944	260	dma01: dma-channel@1 {
c7d24a2d	261	compatible = "fsl,mpc8610-dma-channel",
7de0c22b	262	"fsl,ssi-dma-channel";
c7d24a2d	263	cell-index = <1>;
6e050d4e	264	reg = <0x80 0x80>;
c7d24a2d	265	interrupt-parent = <&mpic>;
6e050d4e JL	266	interrupts = <21 2>;
	267	};
	268	dma-channel@2 {
c7d24a2d TT	269	compatible = "fsl,mpc8610-dma-channel",
	270	"fsl,eloplus-dma-channel";
	271	cell-index = <2>;
6e050d4e	272	reg = <0x100 0x80>;
c7d24a2d	273	interrupt-parent = <&mpic>;
6e050d4e JL	274	interrupts = <22 2>;
	275	};
	276	dma-channel@3 {
c7d24a2d TT	277	compatible = "fsl,mpc8610-dma-channel",
	278	"fsl,eloplus-dma-channel";
	279	cell-index = <3>;
6e050d4e	280	reg = <0x180 0x80>;
c7d24a2d	281	interrupt-parent = <&mpic>;
6e050d4e JL	282	interrupts = <23 2>;
	283	};
	284	};
c7d24a2d	285
6e050d4e JL	286	dma@c300 {
	287	#address-cells = <1>;
	288	#size-cells = <1>;
9c8b28c2	289	compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
6e050d4e JL	290	cell-index = <1>;
	291	reg = <0xc300 0x4>; /* DMA general status register */
	292	ranges = <0x0 0xc100 0x200>;
c7d24a2d	293
6e050d4e	294	dma-channel@0 {
c7d24a2d	295	compatible = "fsl,mpc8610-dma-channel",
9c8b28c2	296	"fsl,eloplus-dma-channel";
c7d24a2d	297	cell-index = <0>;
6e050d4e	298	reg = <0x0 0x80>;
c7d24a2d	299	interrupt-parent = <&mpic>;
612f9d33	300	interrupts = <76 2>;
6e050d4e JL	301	};
6e050d4e JL	302	dma-channel@1 {
c7d24a2d	303	compatible = "fsl,mpc8610-dma-channel",
9c8b28c2	304	"fsl,eloplus-dma-channel";
c7d24a2d	305	cell-index = <1>;
6e050d4e	306	reg = <0x80 0x80>;
c7d24a2d	307	interrupt-parent = <&mpic>;
612f9d33	308	interrupts = <77 2>;
6e050d4e JL	309	};
6e050d4e JL	310	dma-channel@2 {
c7d24a2d	311	compatible = "fsl,mpc8610-dma-channel",
9c8b28c2	312	"fsl,eloplus-dma-channel";
c7d24a2d	313	cell-index = <2>;
6e050d4e	314	reg = <0x100 0x80>;
c7d24a2d	315	interrupt-parent = <&mpic>;
612f9d33	316	interrupts = <78 2>;
6e050d4e JL	317	};
6e050d4e JL	318	dma-channel@3 {
c7d24a2d	319	compatible = "fsl,mpc8610-dma-channel",
9c8b28c2	320	"fsl,eloplus-dma-channel";
c7d24a2d	321	cell-index = <3>;
6e050d4e	322	reg = <0x180 0x80>;
c7d24a2d	323	interrupt-parent = <&mpic>;
612f9d33	324	interrupts = <79 2>;
6e050d4e JL	325	};
6e050d4e JL	326	};
c7d24a2d	327
53f3945a XX	328	};
53f3945a XX	329
ea082fa9	330	pci0: pci@e0008000 {
53f3945a XX	331	compatible = "fsl,mpc8610-pci";
	332	device_type = "pci";
	333	#interrupt-cells = <1>;
	334	#size-cells = <2>;
	335	#address-cells = <3>;
6e050d4e	336	reg = <0xe0008000 0x1000>;
53f3945a	337	bus-range = <0 0>;
6e050d4e JL	338	ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
	339	0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
	340	clock-frequency = <33333333>;
53f3945a	341	interrupt-parent = <&mpic>;
6e050d4e JL	342	interrupts = <24 2>;
6e050d4e JL	343	interrupt-map-mask = <0xf800 0 0 7>;
53f3945a XX	344	interrupt-map = <
53f3945a XX	345	/* IDSEL 0x11 */
6e050d4e JL	346	0x8800 0 0 1 &mpic 4 1
	347	0x8800 0 0 2 &mpic 5 1
	348	0x8800 0 0 3 &mpic 6 1
	349	0x8800 0 0 4 &mpic 7 1
53f3945a XX	350
53f3945a XX	351	/* IDSEL 0x12 */
6e050d4e JL	352	0x9000 0 0 1 &mpic 5 1
	353	0x9000 0 0 2 &mpic 6 1
	354	0x9000 0 0 3 &mpic 7 1
	355	0x9000 0 0 4 &mpic 4 1
53f3945a XX	356	>;
	357	};
	358
ea082fa9	359	pci1: pcie@e000a000 {
53f3945a XX	360	compatible = "fsl,mpc8641-pcie";
	361	device_type = "pci";
	362	#interrupt-cells = <1>;
	363	#size-cells = <2>;
	364	#address-cells = <3>;
6e050d4e	365	reg = <0xe000a000 0x1000>;
53f3945a	366	bus-range = <1 3>;
6e050d4e JL	367	ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
	368	0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
	369	clock-frequency = <33333333>;
53f3945a	370	interrupt-parent = <&mpic>;
6e050d4e JL	371	interrupts = <26 2>;
6e050d4e JL	372	interrupt-map-mask = <0xf800 0 0 7>;
53f3945a XX	373
	374	interrupt-map = <
	375	/* IDSEL 0x1b */
6e050d4e	376	0xd800 0 0 1 &mpic 2 1
53f3945a XX	377
53f3945a XX	378	/* IDSEL 0x1c*/
6e050d4e JL	379	0xe000 0 0 1 &mpic 1 1
	380	0xe000 0 0 2 &mpic 1 1
	381	0xe000 0 0 3 &mpic 1 1
	382	0xe000 0 0 4 &mpic 1 1
53f3945a XX	383
53f3945a XX	384	/* IDSEL 0x1f */
deabeabf	385	0xf800 0 0 1 &mpic 3 2
6e050d4e	386	0xf800 0 0 2 &mpic 0 1
53f3945a XX	387	>;
	388
	389	pcie@0 {
	390	reg = <0 0 0 0 0>;
	391	#size-cells = <2>;
	392	#address-cells = <3>;
	393	device_type = "pci";
6e050d4e JL	394	ranges = <0x02000000 0x0 0xa0000000
	395	0x02000000 0x0 0xa0000000
	396	0x0 0x10000000
	397	0x01000000 0x0 0x00000000
	398	0x01000000 0x0 0x00000000
	399	0x0 0x00100000>;
53f3945a XX	400	uli1575@0 {
	401	reg = <0 0 0 0 0>;
	402	#size-cells = <2>;
	403	#address-cells = <3>;
6e050d4e JL	404	ranges = <0x02000000 0x0 0xa0000000
	405	0x02000000 0x0 0xa0000000
	406	0x0 0x10000000
	407	0x01000000 0x0 0x00000000
	408	0x01000000 0x0 0x00000000
	409	0x0 0x00100000>;
a47fda93 AV	410
	411	isa@1e {
	412	device_type = "isa";
	413	#size-cells = <1>;
	414	#address-cells = <2>;
	415	reg = <0xf000 0 0 0 0>;
	416	ranges = <1 0 0x01000000 0 0
	417	0x00001000>;
	418
	419	rtc@70 {
	420	compatible = "pnpPNP,b00";
	421	reg = <1 0x70 2>;
	422	};
	423	};
53f3945a XX	424	};
	425	};
	426	};
e598477a AV	427
	428	pci2: pcie@e0009000 {
	429	#address-cells = <3>;
	430	#size-cells = <2>;
	431	#interrupt-cells = <1>;
	432	device_type = "pci";
	433	compatible = "fsl,mpc8641-pcie";
	434	reg = <0xe0009000 0x00001000>;
	435	ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
	436	0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
	437	bus-range = <0 255>;
	438	interrupt-map-mask = <0xf800 0 0 7>;
	439	interrupt-map = <0x0000 0 0 1 &mpic 4 1
	440	0x0000 0 0 2 &mpic 5 1
	441	0x0000 0 0 3 &mpic 6 1
	442	0x0000 0 0 4 &mpic 7 1>;
	443	interrupt-parent = <&mpic>;
	444	interrupts = <25 2>;
	445	clock-frequency = <33333333>;
	446	};
53f3945a	447	};