[deliverable/linux.git] / arch / powerpc / boot / dts / mpc8610_hpcd.dts

/*
 * MPC8610 HPCD Device Tree Source
 *
 * Copyright 2007-2008 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under the terms of the GNU General Public License Version 2 as published
 * by the Free Software Foundation.
 */

/dts-v1/;

/ {
	model = "MPC8610HPCD";
	compatible = "fsl,MPC8610HPCD";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
		pci1 = &pci1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8610@0 {
			device_type = "cpu";
			reg = <0>;
			d-cache-line-size = <32>;
			i-cache-line-size = <32>;
			d-cache-size = <32768>;		// L1
			i-cache-size = <32768>;		// L1
			timebase-frequency = <0>;	// From uboot
			bus-frequency = <0>;		// From uboot
			clock-frequency = <0>;		// From uboot
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x20000000>;	// 512M at 0x0
	};

	board-control@e8000000 {
		compatible = "fsl,fpga-pixis";
		reg = <0xe8000000 32>;		// pixis at 0xe8000000
	};

	soc@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		#interrupt-cells = <2>;
		device_type = "soc";
		compatible = "fsl,mpc8610-immr", "simple-bus";
		ranges = <0x0 0xe0000000 0x00100000>;
		reg = <0xe0000000 0x1000>;
		bus-frequency = <0>;

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;

			cs4270:codec@4f {
				compatible = "cirrus,cs4270";
				reg = <0x4f>;
				/* MCLK source is a stand-alone oscillator */
				clock-frequency = <12288000>;
			};
		};

		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4500 0x100>;
			clock-frequency = <0>;
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4600 0x100>;
			clock-frequency = <0>;
			interrupts = <28 2>;
			interrupt-parent = <&mpic>;
		};

		display@2c000 {
			compatible = "fsl,diu";
			reg = <0x2c000 100>;
			interrupts = <72 2>;
			interrupt-parent = <&mpic>;
		};

		mpic: interrupt-controller@40000 {
			clock-frequency = <0>;
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x40000 0x40000>;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
			big-endian;
		};

		global-utilities@e0000 {
			compatible = "fsl,mpc8610-guts";
			reg = <0xe0000 0x1000>;
			fsl,has-rstcr;
		};

		i2s@16000 {
			compatible = "fsl,mpc8610-ssi";
			cell-index = <0>;
			reg = <0x16000 0x100>;
			interrupt-parent = <&mpic>;
			interrupts = <62 2>;
			fsl,mode = "i2s-slave";
			codec-handle = <&cs4270>;
		};

		ssi@16100 {
			compatible = "fsl,mpc8610-ssi";
			cell-index = <1>;
			reg = <0x16100 0x100>;
			interrupt-parent = <&mpic>;
			interrupts = <63 2>;
		};

		dma@21300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
			cell-index = <0>;
			reg = <0x21300 0x4>; /* DMA general status register */
			ranges = <0x0 0x21100 0x200>;

			dma-channel@0 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,eloplus-dma-channel";
				cell-index = <0>;
				reg = <0x0 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <20 2>;
			};
			dma-channel@1 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,eloplus-dma-channel";
				cell-index = <1>;
				reg = <0x80 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <21 2>;
			};
			dma-channel@2 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,eloplus-dma-channel";
				cell-index = <2>;
				reg = <0x100 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <22 2>;
			};
			dma-channel@3 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,eloplus-dma-channel";
				cell-index = <3>;
				reg = <0x180 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <23 2>;
			};
		};

		dma@c300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8610-dma", "fsl,mpc8540-dma";
			cell-index = <1>;
			reg = <0xc300 0x4>; /* DMA general status register */
			ranges = <0x0 0xc100 0x200>;

			dma-channel@0 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,mpc8540-dma-channel";
				cell-index = <0>;
				reg = <0x0 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <60 2>;
			};
			dma-channel@1 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,mpc8540-dma-channel";
				cell-index = <1>;
				reg = <0x80 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <61 2>;
			};
			dma-channel@2 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,mpc8540-dma-channel";
				cell-index = <2>;
				reg = <0x100 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <62 2>;
			};
			dma-channel@3 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,mpc8540-dma-channel";
				cell-index = <3>;
				reg = <0x180 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <63 2>;
			};
		};

	};

	pci0: pci@e0008000 {
		cell-index = <0>;
		compatible = "fsl,mpc8610-pci";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0008000 0x1000>;
		bus-range = <0 0>;
		ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
			  0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <24 2>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <
			/* IDSEL 0x11 */
			0x8800 0 0 1 &mpic 4 1
			0x8800 0 0 2 &mpic 5 1
			0x8800 0 0 3 &mpic 6 1
			0x8800 0 0 4 &mpic 7 1

			/* IDSEL 0x12 */
			0x9000 0 0 1 &mpic 5 1
			0x9000 0 0 2 &mpic 6 1
			0x9000 0 0 3 &mpic 7 1
			0x9000 0 0 4 &mpic 4 1
			>;
	};

	pci1: pcie@e000a000 {
		cell-index = <1>;
		compatible = "fsl,mpc8641-pcie";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe000a000 0x1000>;
		bus-range = <1 3>;
		ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
			  0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <26 2>;
		interrupt-map-mask = <0xf800 0 0 7>;

		interrupt-map = <
			/* IDSEL 0x1b */
			0xd800 0 0 1 &mpic 2 1

			/* IDSEL 0x1c*/
			0xe000 0 0 1 &mpic 1 1
			0xe000 0 0 2 &mpic 1 1
			0xe000 0 0 3 &mpic 1 1
			0xe000 0 0 4 &mpic 1 1

			/* IDSEL 0x1f */
			0xf800 0 0 1 &mpic 3 0
			0xf800 0 0 2 &mpic 0 1
		>;

		pcie@0 {
			reg = <0 0 0 0 0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x02000000 0x0 0xa0000000
				  0x02000000 0x0 0xa0000000
				  0x0 0x10000000
				  0x01000000 0x0 0x00000000
				  0x01000000 0x0 0x00000000
				  0x0 0x00100000>;
			uli1575@0 {
				reg = <0 0 0 0 0>;
				#size-cells = <2>;
				#address-cells = <3>;
				ranges = <0x02000000 0x0 0xa0000000
					  0x02000000 0x0 0xa0000000
					  0x0 0x10000000
					  0x01000000 0x0 0x00000000
					  0x01000000 0x0 0x00000000
					  0x0 0x00100000>;
			};
		};
	};
};
Commit	Line	Data
53f3945a XX	1	/*
	2	* MPC8610 HPCD Device Tree Source
	3	*
c7d24a2d	4	* Copyright 2007-2008 Freescale Semiconductor Inc.
53f3945a XX	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License Version 2 as published
	8	* by the Free Software Foundation.
	9	*/
	10
6e050d4e	11	/dts-v1/;
53f3945a XX	12
	13	/ {
	14	model = "MPC8610HPCD";
	15	compatible = "fsl,MPC8610HPCD";
	16	#address-cells = <1>;
	17	#size-cells = <1>;
	18
ea082fa9 KG	19	aliases {
	20	serial0 = &serial0;
	21	serial1 = &serial1;
	22	pci0 = &pci0;
	23	pci1 = &pci1;
	24	};
	25
53f3945a XX	26	cpus {
	27	#address-cells = <1>;
	28	#size-cells = <0>;
	29
	30	PowerPC,8610@0 {
	31	device_type = "cpu";
	32	reg = <0>;
6e050d4e JL	33	d-cache-line-size = <32>;
	34	i-cache-line-size = <32>;
	35	d-cache-size = <32768>; // L1
	36	i-cache-size = <32768>; // L1
	37	timebase-frequency = <0>; // From uboot
53f3945a XX	38	bus-frequency = <0>; // From uboot
	39	clock-frequency = <0>; // From uboot
	40	};
	41	};
	42
	43	memory {
	44	device_type = "memory";
6e050d4e	45	reg = <0x00000000 0x20000000>; // 512M at 0x0
53f3945a XX	46	};
53f3945a XX	47
9b53a9e2 YS	48	board-control@e8000000 {
	49	compatible = "fsl,fpga-pixis";
	50	reg = <0xe8000000 32>; // pixis at 0xe8000000
	51	};
	52
53f3945a XX	53	soc@e0000000 {
	54	#address-cells = <1>;
	55	#size-cells = <1>;
	56	#interrupt-cells = <2>;
	57	device_type = "soc";
c7d24a2d	58	compatible = "fsl,mpc8610-immr", "simple-bus";
6e050d4e JL	59	ranges = <0x0 0xe0000000 0x00100000>;
6e050d4e JL	60	reg = <0xe0000000 0x1000>;
53f3945a XX	61	bus-frequency = <0>;
	62
	63	i2c@3000 {
53f3945a XX	64	#address-cells = <1>;
53f3945a XX	65	#size-cells = <0>;
ec9686c4 KG	66	cell-index = <0>;
ec9686c4 KG	67	compatible = "fsl-i2c";
6e050d4e JL	68	reg = <0x3000 0x100>;
6e050d4e JL	69	interrupts = <43 2>;
53f3945a XX	70	interrupt-parent = <&mpic>;
53f3945a XX	71	dfsrr;
c7d24a2d	72
6e050d4e	73	cs4270:codec@4f {
c7d24a2d	74	compatible = "cirrus,cs4270";
6e050d4e	75	reg = <0x4f>;
c7d24a2d	76	/* MCLK source is a stand-alone oscillator */
6e050d4e JL	77	clock-frequency = <12288000>;
6e050d4e JL	78	};
53f3945a XX	79	};
	80
	81	i2c@3100 {
53f3945a XX	82	#address-cells = <1>;
53f3945a XX	83	#size-cells = <0>;
ec9686c4 KG	84	cell-index = <1>;
ec9686c4 KG	85	compatible = "fsl-i2c";
6e050d4e JL	86	reg = <0x3100 0x100>;
6e050d4e JL	87	interrupts = <43 2>;
53f3945a XX	88	interrupt-parent = <&mpic>;
	89	dfsrr;
	90	};
	91
ea082fa9 KG	92	serial0: serial@4500 {
ea082fa9 KG	93	cell-index = <0>;
53f3945a XX	94	device_type = "serial";
53f3945a XX	95	compatible = "ns16550";
6e050d4e	96	reg = <0x4500 0x100>;
53f3945a	97	clock-frequency = <0>;
6e050d4e	98	interrupts = <42 2>;
53f3945a XX	99	interrupt-parent = <&mpic>;
	100	};
	101
ea082fa9 KG	102	serial1: serial@4600 {
ea082fa9 KG	103	cell-index = <1>;
53f3945a XX	104	device_type = "serial";
53f3945a XX	105	compatible = "ns16550";
6e050d4e	106	reg = <0x4600 0x100>;
53f3945a	107	clock-frequency = <0>;
6e050d4e	108	interrupts = <28 2>;
53f3945a XX	109	interrupt-parent = <&mpic>;
	110	};
	111
9b53a9e2 YS	112	display@2c000 {
	113	compatible = "fsl,diu";
	114	reg = <0x2c000 100>;
	115	interrupts = <72 2>;
	116	interrupt-parent = <&mpic>;
	117	};
	118
53f3945a XX	119	mpic: interrupt-controller@40000 {
	120	clock-frequency = <0>;
	121	interrupt-controller;
	122	#address-cells = <0>;
	123	#interrupt-cells = <2>;
6e050d4e	124	reg = <0x40000 0x40000>;
53f3945a XX	125	compatible = "chrp,open-pic";
	126	device_type = "open-pic";
	127	big-endian;
	128	};
	129
	130	global-utilities@e0000 {
	131	compatible = "fsl,mpc8610-guts";
6e050d4e	132	reg = <0xe0000 0x1000>;
53f3945a XX	133	fsl,has-rstcr;
53f3945a XX	134	};
c7d24a2d TT	135
	136	i2s@16000 {
	137	compatible = "fsl,mpc8610-ssi";
	138	cell-index = <0>;
6e050d4e	139	reg = <0x16000 0x100>;
c7d24a2d	140	interrupt-parent = <&mpic>;
6e050d4e	141	interrupts = <62 2>;
c7d24a2d TT	142	fsl,mode = "i2s-slave";
	143	codec-handle = <&cs4270>;
	144	};
	145
	146	ssi@16100 {
	147	compatible = "fsl,mpc8610-ssi";
	148	cell-index = <1>;
6e050d4e	149	reg = <0x16100 0x100>;
c7d24a2d	150	interrupt-parent = <&mpic>;
6e050d4e	151	interrupts = <63 2>;
c7d24a2d TT	152	};
c7d24a2d TT	153
6e050d4e JL	154	dma@21300 {
	155	#address-cells = <1>;
	156	#size-cells = <1>;
	157	compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
	158	cell-index = <0>;
	159	reg = <0x21300 0x4>; /* DMA general status register */
	160	ranges = <0x0 0x21100 0x200>;
c7d24a2d	161
6e050d4e	162	dma-channel@0 {
c7d24a2d TT	163	compatible = "fsl,mpc8610-dma-channel",
	164	"fsl,eloplus-dma-channel";
	165	cell-index = <0>;
6e050d4e	166	reg = <0x0 0x80>;
c7d24a2d	167	interrupt-parent = <&mpic>;
6e050d4e JL	168	interrupts = <20 2>;
	169	};
	170	dma-channel@1 {
c7d24a2d TT	171	compatible = "fsl,mpc8610-dma-channel",
	172	"fsl,eloplus-dma-channel";
	173	cell-index = <1>;
6e050d4e	174	reg = <0x80 0x80>;
c7d24a2d	175	interrupt-parent = <&mpic>;
6e050d4e JL	176	interrupts = <21 2>;
	177	};
	178	dma-channel@2 {
c7d24a2d TT	179	compatible = "fsl,mpc8610-dma-channel",
	180	"fsl,eloplus-dma-channel";
	181	cell-index = <2>;
6e050d4e	182	reg = <0x100 0x80>;
c7d24a2d	183	interrupt-parent = <&mpic>;
6e050d4e JL	184	interrupts = <22 2>;
	185	};
	186	dma-channel@3 {
c7d24a2d TT	187	compatible = "fsl,mpc8610-dma-channel",
	188	"fsl,eloplus-dma-channel";
	189	cell-index = <3>;
6e050d4e	190	reg = <0x180 0x80>;
c7d24a2d	191	interrupt-parent = <&mpic>;
6e050d4e JL	192	interrupts = <23 2>;
	193	};
	194	};
c7d24a2d	195
6e050d4e JL	196	dma@c300 {
	197	#address-cells = <1>;
	198	#size-cells = <1>;
	199	compatible = "fsl,mpc8610-dma", "fsl,mpc8540-dma";
	200	cell-index = <1>;
	201	reg = <0xc300 0x4>; /* DMA general status register */
	202	ranges = <0x0 0xc100 0x200>;
c7d24a2d	203
6e050d4e	204	dma-channel@0 {
c7d24a2d TT	205	compatible = "fsl,mpc8610-dma-channel",
	206	"fsl,mpc8540-dma-channel";
	207	cell-index = <0>;
6e050d4e	208	reg = <0x0 0x80>;
c7d24a2d	209	interrupt-parent = <&mpic>;
6e050d4e JL	210	interrupts = <60 2>;
	211	};
	212	dma-channel@1 {
c7d24a2d TT	213	compatible = "fsl,mpc8610-dma-channel",
	214	"fsl,mpc8540-dma-channel";
	215	cell-index = <1>;
6e050d4e	216	reg = <0x80 0x80>;
c7d24a2d	217	interrupt-parent = <&mpic>;
6e050d4e JL	218	interrupts = <61 2>;
	219	};
	220	dma-channel@2 {
c7d24a2d TT	221	compatible = "fsl,mpc8610-dma-channel",
	222	"fsl,mpc8540-dma-channel";
	223	cell-index = <2>;
6e050d4e	224	reg = <0x100 0x80>;
c7d24a2d	225	interrupt-parent = <&mpic>;
6e050d4e JL	226	interrupts = <62 2>;
	227	};
	228	dma-channel@3 {
c7d24a2d TT	229	compatible = "fsl,mpc8610-dma-channel",
	230	"fsl,mpc8540-dma-channel";
	231	cell-index = <3>;
6e050d4e	232	reg = <0x180 0x80>;
c7d24a2d	233	interrupt-parent = <&mpic>;
6e050d4e JL	234	interrupts = <63 2>;
	235	};
	236	};
c7d24a2d	237
53f3945a XX	238	};
53f3945a XX	239
ea082fa9 KG	240	pci0: pci@e0008000 {
ea082fa9 KG	241	cell-index = <0>;
53f3945a XX	242	compatible = "fsl,mpc8610-pci";
	243	device_type = "pci";
	244	#interrupt-cells = <1>;
	245	#size-cells = <2>;
	246	#address-cells = <3>;
6e050d4e	247	reg = <0xe0008000 0x1000>;
53f3945a	248	bus-range = <0 0>;
6e050d4e JL	249	ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
	250	0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
	251	clock-frequency = <33333333>;
53f3945a	252	interrupt-parent = <&mpic>;
6e050d4e JL	253	interrupts = <24 2>;
6e050d4e JL	254	interrupt-map-mask = <0xf800 0 0 7>;
53f3945a XX	255	interrupt-map = <
53f3945a XX	256	/* IDSEL 0x11 */
6e050d4e JL	257	0x8800 0 0 1 &mpic 4 1
	258	0x8800 0 0 2 &mpic 5 1
	259	0x8800 0 0 3 &mpic 6 1
	260	0x8800 0 0 4 &mpic 7 1
53f3945a XX	261
53f3945a XX	262	/* IDSEL 0x12 */
6e050d4e JL	263	0x9000 0 0 1 &mpic 5 1
	264	0x9000 0 0 2 &mpic 6 1
	265	0x9000 0 0 3 &mpic 7 1
	266	0x9000 0 0 4 &mpic 4 1
53f3945a XX	267	>;
	268	};
	269
ea082fa9 KG	270	pci1: pcie@e000a000 {
ea082fa9 KG	271	cell-index = <1>;
53f3945a XX	272	compatible = "fsl,mpc8641-pcie";
	273	device_type = "pci";
	274	#interrupt-cells = <1>;
	275	#size-cells = <2>;
	276	#address-cells = <3>;
6e050d4e	277	reg = <0xe000a000 0x1000>;
53f3945a	278	bus-range = <1 3>;
6e050d4e JL	279	ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
	280	0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
	281	clock-frequency = <33333333>;
53f3945a	282	interrupt-parent = <&mpic>;
6e050d4e JL	283	interrupts = <26 2>;
6e050d4e JL	284	interrupt-map-mask = <0xf800 0 0 7>;
53f3945a XX	285
	286	interrupt-map = <
	287	/* IDSEL 0x1b */
6e050d4e	288	0xd800 0 0 1 &mpic 2 1
53f3945a XX	289
53f3945a XX	290	/* IDSEL 0x1c*/
6e050d4e JL	291	0xe000 0 0 1 &mpic 1 1
	292	0xe000 0 0 2 &mpic 1 1
	293	0xe000 0 0 3 &mpic 1 1
	294	0xe000 0 0 4 &mpic 1 1
53f3945a XX	295
53f3945a XX	296	/* IDSEL 0x1f */
6e050d4e JL	297	0xf800 0 0 1 &mpic 3 0
6e050d4e JL	298	0xf800 0 0 2 &mpic 0 1
53f3945a XX	299	>;
	300
	301	pcie@0 {
	302	reg = <0 0 0 0 0>;
	303	#size-cells = <2>;
	304	#address-cells = <3>;
	305	device_type = "pci";
6e050d4e JL	306	ranges = <0x02000000 0x0 0xa0000000
	307	0x02000000 0x0 0xa0000000
	308	0x0 0x10000000
	309	0x01000000 0x0 0x00000000
	310	0x01000000 0x0 0x00000000
	311	0x0 0x00100000>;
53f3945a XX	312	uli1575@0 {
	313	reg = <0 0 0 0 0>;
	314	#size-cells = <2>;
	315	#address-cells = <3>;
6e050d4e JL	316	ranges = <0x02000000 0x0 0xa0000000
	317	0x02000000 0x0 0xa0000000
	318	0x0 0x10000000
	319	0x01000000 0x0 0x00000000
	320	0x01000000 0x0 0x00000000
	321	0x0 0x00100000>;
53f3945a XX	322	};
	323	};
	324	};
	325	};