Commit | Line | Data |
---|---|---|
53f3945a XX |
1 | /* |
2 | * MPC8610 HPCD Device Tree Source | |
3 | * | |
c7d24a2d | 4 | * Copyright 2007-2008 Freescale Semiconductor Inc. |
53f3945a XX |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License Version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | */ | |
10 | ||
6e050d4e | 11 | /dts-v1/; |
53f3945a XX |
12 | |
13 | / { | |
14 | model = "MPC8610HPCD"; | |
15 | compatible = "fsl,MPC8610HPCD"; | |
16 | #address-cells = <1>; | |
17 | #size-cells = <1>; | |
18 | ||
ea082fa9 KG |
19 | aliases { |
20 | serial0 = &serial0; | |
21 | serial1 = &serial1; | |
22 | pci0 = &pci0; | |
23 | pci1 = &pci1; | |
e598477a | 24 | pci2 = &pci2; |
ea082fa9 KG |
25 | }; |
26 | ||
53f3945a XX |
27 | cpus { |
28 | #address-cells = <1>; | |
29 | #size-cells = <0>; | |
30 | ||
31 | PowerPC,8610@0 { | |
32 | device_type = "cpu"; | |
33 | reg = <0>; | |
6e050d4e JL |
34 | d-cache-line-size = <32>; |
35 | i-cache-line-size = <32>; | |
36 | d-cache-size = <32768>; // L1 | |
37 | i-cache-size = <32768>; // L1 | |
38 | timebase-frequency = <0>; // From uboot | |
53f3945a XX |
39 | bus-frequency = <0>; // From uboot |
40 | clock-frequency = <0>; // From uboot | |
41 | }; | |
42 | }; | |
43 | ||
44 | memory { | |
45 | device_type = "memory"; | |
6e050d4e | 46 | reg = <0x00000000 0x20000000>; // 512M at 0x0 |
53f3945a XX |
47 | }; |
48 | ||
34b4a873 AV |
49 | localbus@e0005000 { |
50 | #address-cells = <2>; | |
51 | #size-cells = <1>; | |
52 | compatible = "fsl,mpc8610-elbc", "fsl,elbc", "simple-bus"; | |
53 | reg = <0xe0005000 0x1000>; | |
54 | interrupts = <19 2>; | |
55 | interrupt-parent = <&mpic>; | |
56 | ranges = <0 0 0xf8000000 0x08000000 | |
57 | 1 0 0xf0000000 0x08000000 | |
58 | 2 0 0xe8400000 0x00008000 | |
59 | 4 0 0xe8440000 0x00008000 | |
60 | 5 0 0xe8480000 0x00008000 | |
61 | 6 0 0xe84c0000 0x00008000 | |
62 | 3 0 0xe8000000 0x00000020>; | |
63 | ||
64 | flash@0,0 { | |
65 | compatible = "cfi-flash"; | |
66 | reg = <0 0 0x8000000>; | |
67 | bank-width = <2>; | |
68 | device-width = <1>; | |
69 | }; | |
70 | ||
71 | flash@1,0 { | |
72 | compatible = "cfi-flash"; | |
73 | reg = <1 0 0x8000000>; | |
74 | bank-width = <2>; | |
75 | device-width = <1>; | |
76 | }; | |
77 | ||
78 | flash@2,0 { | |
79 | compatible = "fsl,mpc8610-fcm-nand", | |
80 | "fsl,elbc-fcm-nand"; | |
81 | reg = <2 0 0x8000>; | |
82 | }; | |
83 | ||
84 | flash@4,0 { | |
85 | compatible = "fsl,mpc8610-fcm-nand", | |
86 | "fsl,elbc-fcm-nand"; | |
87 | reg = <4 0 0x8000>; | |
88 | }; | |
89 | ||
90 | flash@5,0 { | |
91 | compatible = "fsl,mpc8610-fcm-nand", | |
92 | "fsl,elbc-fcm-nand"; | |
93 | reg = <5 0 0x8000>; | |
94 | }; | |
95 | ||
96 | flash@6,0 { | |
97 | compatible = "fsl,mpc8610-fcm-nand", | |
98 | "fsl,elbc-fcm-nand"; | |
99 | reg = <6 0 0x8000>; | |
100 | }; | |
101 | ||
102 | board-control@3,0 { | |
103 | compatible = "fsl,fpga-pixis"; | |
104 | reg = <3 0 0x20>; | |
105 | }; | |
9b53a9e2 YS |
106 | }; |
107 | ||
53f3945a XX |
108 | soc@e0000000 { |
109 | #address-cells = <1>; | |
110 | #size-cells = <1>; | |
111 | #interrupt-cells = <2>; | |
112 | device_type = "soc"; | |
c7d24a2d | 113 | compatible = "fsl,mpc8610-immr", "simple-bus"; |
6e050d4e JL |
114 | ranges = <0x0 0xe0000000 0x00100000>; |
115 | reg = <0xe0000000 0x1000>; | |
53f3945a XX |
116 | bus-frequency = <0>; |
117 | ||
118 | i2c@3000 { | |
53f3945a XX |
119 | #address-cells = <1>; |
120 | #size-cells = <0>; | |
ec9686c4 KG |
121 | cell-index = <0>; |
122 | compatible = "fsl-i2c"; | |
6e050d4e JL |
123 | reg = <0x3000 0x100>; |
124 | interrupts = <43 2>; | |
53f3945a XX |
125 | interrupt-parent = <&mpic>; |
126 | dfsrr; | |
c7d24a2d | 127 | |
6e050d4e | 128 | cs4270:codec@4f { |
c7d24a2d | 129 | compatible = "cirrus,cs4270"; |
6e050d4e | 130 | reg = <0x4f>; |
c7d24a2d | 131 | /* MCLK source is a stand-alone oscillator */ |
6e050d4e JL |
132 | clock-frequency = <12288000>; |
133 | }; | |
53f3945a XX |
134 | }; |
135 | ||
136 | i2c@3100 { | |
53f3945a XX |
137 | #address-cells = <1>; |
138 | #size-cells = <0>; | |
ec9686c4 KG |
139 | cell-index = <1>; |
140 | compatible = "fsl-i2c"; | |
6e050d4e JL |
141 | reg = <0x3100 0x100>; |
142 | interrupts = <43 2>; | |
53f3945a XX |
143 | interrupt-parent = <&mpic>; |
144 | dfsrr; | |
145 | }; | |
146 | ||
ea082fa9 KG |
147 | serial0: serial@4500 { |
148 | cell-index = <0>; | |
53f3945a XX |
149 | device_type = "serial"; |
150 | compatible = "ns16550"; | |
6e050d4e | 151 | reg = <0x4500 0x100>; |
53f3945a | 152 | clock-frequency = <0>; |
6e050d4e | 153 | interrupts = <42 2>; |
53f3945a XX |
154 | interrupt-parent = <&mpic>; |
155 | }; | |
156 | ||
ea082fa9 KG |
157 | serial1: serial@4600 { |
158 | cell-index = <1>; | |
53f3945a XX |
159 | device_type = "serial"; |
160 | compatible = "ns16550"; | |
6e050d4e | 161 | reg = <0x4600 0x100>; |
53f3945a | 162 | clock-frequency = <0>; |
aecb2b6e | 163 | interrupts = <42 2>; |
53f3945a XX |
164 | interrupt-parent = <&mpic>; |
165 | }; | |
166 | ||
9b53a9e2 YS |
167 | display@2c000 { |
168 | compatible = "fsl,diu"; | |
169 | reg = <0x2c000 100>; | |
170 | interrupts = <72 2>; | |
171 | interrupt-parent = <&mpic>; | |
172 | }; | |
173 | ||
53f3945a | 174 | mpic: interrupt-controller@40000 { |
53f3945a XX |
175 | interrupt-controller; |
176 | #address-cells = <0>; | |
177 | #interrupt-cells = <2>; | |
6e050d4e | 178 | reg = <0x40000 0x40000>; |
53f3945a XX |
179 | compatible = "chrp,open-pic"; |
180 | device_type = "open-pic"; | |
53f3945a XX |
181 | }; |
182 | ||
0023352f JJ |
183 | msi@41600 { |
184 | compatible = "fsl,mpc8610-msi", "fsl,mpic-msi"; | |
185 | reg = <0x41600 0x80>; | |
186 | msi-available-ranges = <0 0x100>; | |
187 | interrupts = < | |
188 | 0xe0 0 | |
189 | 0xe1 0 | |
190 | 0xe2 0 | |
191 | 0xe3 0 | |
192 | 0xe4 0 | |
193 | 0xe5 0 | |
194 | 0xe6 0 | |
195 | 0xe7 0>; | |
196 | interrupt-parent = <&mpic>; | |
197 | }; | |
198 | ||
53f3945a XX |
199 | global-utilities@e0000 { |
200 | compatible = "fsl,mpc8610-guts"; | |
6e050d4e | 201 | reg = <0xe0000 0x1000>; |
53f3945a XX |
202 | fsl,has-rstcr; |
203 | }; | |
c7d24a2d | 204 | |
775587b6 AV |
205 | wdt@e4000 { |
206 | compatible = "fsl,mpc8610-wdt"; | |
207 | reg = <0xe4000 0x100>; | |
208 | }; | |
209 | ||
c7d24a2d TT |
210 | i2s@16000 { |
211 | compatible = "fsl,mpc8610-ssi"; | |
212 | cell-index = <0>; | |
6e050d4e | 213 | reg = <0x16000 0x100>; |
c7d24a2d | 214 | interrupt-parent = <&mpic>; |
6e050d4e | 215 | interrupts = <62 2>; |
c7d24a2d TT |
216 | fsl,mode = "i2s-slave"; |
217 | codec-handle = <&cs4270>; | |
218 | }; | |
219 | ||
220 | ssi@16100 { | |
221 | compatible = "fsl,mpc8610-ssi"; | |
222 | cell-index = <1>; | |
6e050d4e | 223 | reg = <0x16100 0x100>; |
c7d24a2d | 224 | interrupt-parent = <&mpic>; |
6e050d4e | 225 | interrupts = <63 2>; |
c7d24a2d TT |
226 | }; |
227 | ||
6e050d4e JL |
228 | dma@21300 { |
229 | #address-cells = <1>; | |
230 | #size-cells = <1>; | |
231 | compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma"; | |
232 | cell-index = <0>; | |
233 | reg = <0x21300 0x4>; /* DMA general status register */ | |
234 | ranges = <0x0 0x21100 0x200>; | |
c7d24a2d | 235 | |
6e050d4e | 236 | dma-channel@0 { |
c7d24a2d TT |
237 | compatible = "fsl,mpc8610-dma-channel", |
238 | "fsl,eloplus-dma-channel"; | |
239 | cell-index = <0>; | |
6e050d4e | 240 | reg = <0x0 0x80>; |
c7d24a2d | 241 | interrupt-parent = <&mpic>; |
6e050d4e JL |
242 | interrupts = <20 2>; |
243 | }; | |
244 | dma-channel@1 { | |
c7d24a2d TT |
245 | compatible = "fsl,mpc8610-dma-channel", |
246 | "fsl,eloplus-dma-channel"; | |
247 | cell-index = <1>; | |
6e050d4e | 248 | reg = <0x80 0x80>; |
c7d24a2d | 249 | interrupt-parent = <&mpic>; |
6e050d4e JL |
250 | interrupts = <21 2>; |
251 | }; | |
252 | dma-channel@2 { | |
c7d24a2d TT |
253 | compatible = "fsl,mpc8610-dma-channel", |
254 | "fsl,eloplus-dma-channel"; | |
255 | cell-index = <2>; | |
6e050d4e | 256 | reg = <0x100 0x80>; |
c7d24a2d | 257 | interrupt-parent = <&mpic>; |
6e050d4e JL |
258 | interrupts = <22 2>; |
259 | }; | |
260 | dma-channel@3 { | |
c7d24a2d TT |
261 | compatible = "fsl,mpc8610-dma-channel", |
262 | "fsl,eloplus-dma-channel"; | |
263 | cell-index = <3>; | |
6e050d4e | 264 | reg = <0x180 0x80>; |
c7d24a2d | 265 | interrupt-parent = <&mpic>; |
6e050d4e JL |
266 | interrupts = <23 2>; |
267 | }; | |
268 | }; | |
c7d24a2d | 269 | |
6e050d4e JL |
270 | dma@c300 { |
271 | #address-cells = <1>; | |
272 | #size-cells = <1>; | |
9c8b28c2 | 273 | compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma"; |
6e050d4e JL |
274 | cell-index = <1>; |
275 | reg = <0xc300 0x4>; /* DMA general status register */ | |
276 | ranges = <0x0 0xc100 0x200>; | |
c7d24a2d | 277 | |
6e050d4e | 278 | dma-channel@0 { |
c7d24a2d | 279 | compatible = "fsl,mpc8610-dma-channel", |
9c8b28c2 | 280 | "fsl,eloplus-dma-channel"; |
c7d24a2d | 281 | cell-index = <0>; |
6e050d4e | 282 | reg = <0x0 0x80>; |
c7d24a2d | 283 | interrupt-parent = <&mpic>; |
6e050d4e JL |
284 | interrupts = <60 2>; |
285 | }; | |
286 | dma-channel@1 { | |
c7d24a2d | 287 | compatible = "fsl,mpc8610-dma-channel", |
9c8b28c2 | 288 | "fsl,eloplus-dma-channel"; |
c7d24a2d | 289 | cell-index = <1>; |
6e050d4e | 290 | reg = <0x80 0x80>; |
c7d24a2d | 291 | interrupt-parent = <&mpic>; |
6e050d4e JL |
292 | interrupts = <61 2>; |
293 | }; | |
294 | dma-channel@2 { | |
c7d24a2d | 295 | compatible = "fsl,mpc8610-dma-channel", |
9c8b28c2 | 296 | "fsl,eloplus-dma-channel"; |
c7d24a2d | 297 | cell-index = <2>; |
6e050d4e | 298 | reg = <0x100 0x80>; |
c7d24a2d | 299 | interrupt-parent = <&mpic>; |
6e050d4e JL |
300 | interrupts = <62 2>; |
301 | }; | |
302 | dma-channel@3 { | |
c7d24a2d | 303 | compatible = "fsl,mpc8610-dma-channel", |
9c8b28c2 | 304 | "fsl,eloplus-dma-channel"; |
c7d24a2d | 305 | cell-index = <3>; |
6e050d4e | 306 | reg = <0x180 0x80>; |
c7d24a2d | 307 | interrupt-parent = <&mpic>; |
6e050d4e JL |
308 | interrupts = <63 2>; |
309 | }; | |
310 | }; | |
c7d24a2d | 311 | |
53f3945a XX |
312 | }; |
313 | ||
ea082fa9 KG |
314 | pci0: pci@e0008000 { |
315 | cell-index = <0>; | |
53f3945a XX |
316 | compatible = "fsl,mpc8610-pci"; |
317 | device_type = "pci"; | |
318 | #interrupt-cells = <1>; | |
319 | #size-cells = <2>; | |
320 | #address-cells = <3>; | |
6e050d4e | 321 | reg = <0xe0008000 0x1000>; |
53f3945a | 322 | bus-range = <0 0>; |
6e050d4e JL |
323 | ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000 |
324 | 0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>; | |
325 | clock-frequency = <33333333>; | |
53f3945a | 326 | interrupt-parent = <&mpic>; |
6e050d4e JL |
327 | interrupts = <24 2>; |
328 | interrupt-map-mask = <0xf800 0 0 7>; | |
53f3945a XX |
329 | interrupt-map = < |
330 | /* IDSEL 0x11 */ | |
6e050d4e JL |
331 | 0x8800 0 0 1 &mpic 4 1 |
332 | 0x8800 0 0 2 &mpic 5 1 | |
333 | 0x8800 0 0 3 &mpic 6 1 | |
334 | 0x8800 0 0 4 &mpic 7 1 | |
53f3945a XX |
335 | |
336 | /* IDSEL 0x12 */ | |
6e050d4e JL |
337 | 0x9000 0 0 1 &mpic 5 1 |
338 | 0x9000 0 0 2 &mpic 6 1 | |
339 | 0x9000 0 0 3 &mpic 7 1 | |
340 | 0x9000 0 0 4 &mpic 4 1 | |
53f3945a XX |
341 | >; |
342 | }; | |
343 | ||
ea082fa9 KG |
344 | pci1: pcie@e000a000 { |
345 | cell-index = <1>; | |
53f3945a XX |
346 | compatible = "fsl,mpc8641-pcie"; |
347 | device_type = "pci"; | |
348 | #interrupt-cells = <1>; | |
349 | #size-cells = <2>; | |
350 | #address-cells = <3>; | |
6e050d4e | 351 | reg = <0xe000a000 0x1000>; |
53f3945a | 352 | bus-range = <1 3>; |
6e050d4e JL |
353 | ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 |
354 | 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>; | |
355 | clock-frequency = <33333333>; | |
53f3945a | 356 | interrupt-parent = <&mpic>; |
6e050d4e JL |
357 | interrupts = <26 2>; |
358 | interrupt-map-mask = <0xf800 0 0 7>; | |
53f3945a XX |
359 | |
360 | interrupt-map = < | |
361 | /* IDSEL 0x1b */ | |
6e050d4e | 362 | 0xd800 0 0 1 &mpic 2 1 |
53f3945a XX |
363 | |
364 | /* IDSEL 0x1c*/ | |
6e050d4e JL |
365 | 0xe000 0 0 1 &mpic 1 1 |
366 | 0xe000 0 0 2 &mpic 1 1 | |
367 | 0xe000 0 0 3 &mpic 1 1 | |
368 | 0xe000 0 0 4 &mpic 1 1 | |
53f3945a XX |
369 | |
370 | /* IDSEL 0x1f */ | |
deabeabf | 371 | 0xf800 0 0 1 &mpic 3 2 |
6e050d4e | 372 | 0xf800 0 0 2 &mpic 0 1 |
53f3945a XX |
373 | >; |
374 | ||
375 | pcie@0 { | |
376 | reg = <0 0 0 0 0>; | |
377 | #size-cells = <2>; | |
378 | #address-cells = <3>; | |
379 | device_type = "pci"; | |
6e050d4e JL |
380 | ranges = <0x02000000 0x0 0xa0000000 |
381 | 0x02000000 0x0 0xa0000000 | |
382 | 0x0 0x10000000 | |
383 | 0x01000000 0x0 0x00000000 | |
384 | 0x01000000 0x0 0x00000000 | |
385 | 0x0 0x00100000>; | |
53f3945a XX |
386 | uli1575@0 { |
387 | reg = <0 0 0 0 0>; | |
388 | #size-cells = <2>; | |
389 | #address-cells = <3>; | |
6e050d4e JL |
390 | ranges = <0x02000000 0x0 0xa0000000 |
391 | 0x02000000 0x0 0xa0000000 | |
392 | 0x0 0x10000000 | |
393 | 0x01000000 0x0 0x00000000 | |
394 | 0x01000000 0x0 0x00000000 | |
395 | 0x0 0x00100000>; | |
a47fda93 AV |
396 | |
397 | isa@1e { | |
398 | device_type = "isa"; | |
399 | #size-cells = <1>; | |
400 | #address-cells = <2>; | |
401 | reg = <0xf000 0 0 0 0>; | |
402 | ranges = <1 0 0x01000000 0 0 | |
403 | 0x00001000>; | |
404 | ||
405 | rtc@70 { | |
406 | compatible = "pnpPNP,b00"; | |
407 | reg = <1 0x70 2>; | |
408 | }; | |
409 | }; | |
53f3945a XX |
410 | }; |
411 | }; | |
412 | }; | |
e598477a AV |
413 | |
414 | pci2: pcie@e0009000 { | |
415 | #address-cells = <3>; | |
416 | #size-cells = <2>; | |
417 | #interrupt-cells = <1>; | |
418 | device_type = "pci"; | |
419 | compatible = "fsl,mpc8641-pcie"; | |
420 | reg = <0xe0009000 0x00001000>; | |
421 | ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000 | |
422 | 0x01000000 0 0x00000000 0xe2000000 0 0x00100000>; | |
423 | bus-range = <0 255>; | |
424 | interrupt-map-mask = <0xf800 0 0 7>; | |
425 | interrupt-map = <0x0000 0 0 1 &mpic 4 1 | |
426 | 0x0000 0 0 2 &mpic 5 1 | |
427 | 0x0000 0 0 3 &mpic 6 1 | |
428 | 0x0000 0 0 4 &mpic 7 1>; | |
429 | interrupt-parent = <&mpic>; | |
430 | interrupts = <25 2>; | |
431 | clock-frequency = <33333333>; | |
432 | }; | |
53f3945a | 433 | }; |