[deliverable/linux.git] / arch / powerpc / boot / dts / mpc8641_hpcn.dts

/*
 * MPC8641 HPCN Device Tree Source
 *
 * Copyright 2006 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/dts-v1/;

/ {
	model = "MPC8641HPCN";
	compatible = "fsl,mpc8641hpcn";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		ethernet2 = &enet2;
		ethernet3 = &enet3;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
		pci1 = &pci1;
/*
 * Only one of Rapid IO or PCI can be present due to HW limitations and
 * due to the fact that the 2 now share address space in the new memory
 * map.  The most likely case is that we have PCI, so comment out the
 * rapidio node.  Leave it here for reference.
 */
		/* rapidio0 = &rapidio0; */
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8641@0 {
			device_type = "cpu";
			reg = <0>;
			d-cache-line-size = <32>;
			i-cache-line-size = <32>;
			d-cache-size = <32768>;		// L1
			i-cache-size = <32768>;		// L1
			timebase-frequency = <0>;	// From uboot
			bus-frequency = <0>;		// From uboot
			clock-frequency = <0>;		// From uboot
		};
		PowerPC,8641@1 {
			device_type = "cpu";
			reg = <1>;
			d-cache-line-size = <32>;
			i-cache-line-size = <32>;
			d-cache-size = <32768>;
			i-cache-size = <32768>;
			timebase-frequency = <0>;	// From uboot
			bus-frequency = <0>;		// From uboot
			clock-frequency = <0>;		// From uboot
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x40000000>;	// 1G at 0x0
	};

	localbus@ffe05000 {
		#address-cells = <2>;
		#size-cells = <1>;
		compatible = "fsl,mpc8641-localbus", "simple-bus";
		reg = <0xffe05000 0x1000>;
		interrupts = <19 2>;
		interrupt-parent = <&mpic>;

		ranges = <0 0 0xef800000 0x00800000
			  2 0 0xffdf8000 0x00008000
			  3 0 0xffdf0000 0x00008000>;

		flash@0,0 {
			compatible = "cfi-flash";
			reg = <0 0 0x00800000>;
			bank-width = <2>;
			device-width = <2>;
			#address-cells = <1>;
			#size-cells = <1>;
			partition@0 {
				label = "kernel";
				reg = <0x00000000 0x00300000>;
			};
			partition@300000 {
				label = "firmware b";
				reg = <0x00300000 0x00100000>;
				read-only;
			};
			partition@400000 {
				label = "fs";
				reg = <0x00400000 0x00300000>;
			};
			partition@700000 {
				label = "firmware a";
				reg = <0x00700000 0x00100000>;
				read-only;
			};
		};
	};

	soc8641@ffe00000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		compatible = "simple-bus";
		ranges = <0x00000000 0xffe00000 0x00100000>;
		bus-frequency = <0>;

		mcm-law@0 {
			compatible = "fsl,mcm-law";
			reg = <0x0 0x1000>;
			fsl,num-laws = <10>;
		};

		mcm@1000 {
			compatible = "fsl,mpc8641-mcm", "fsl,mcm";
			reg = <0x1000 0x1000>;
			interrupts = <17 2>;
			interrupt-parent = <&mpic>;
		};

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		dma@21300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
			reg = <0x21300 0x4>;
			ranges = <0x0 0x21100 0x200>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,mpc8641-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x0 0x80>;
				cell-index = <0>;
				interrupt-parent = <&mpic>;
				interrupts = <20 2>;
			};
			dma-channel@80 {
				compatible = "fsl,mpc8641-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupt-parent = <&mpic>;
				interrupts = <21 2>;
			};
			dma-channel@100 {
				compatible = "fsl,mpc8641-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupt-parent = <&mpic>;
				interrupts = <22 2>;
			};
			dma-channel@180 {
				compatible = "fsl,mpc8641-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x180 0x80>;
				cell-index = <3>;
				interrupt-parent = <&mpic>;
				interrupts = <23 2>;
			};
		};

		enet0: ethernet@24000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <0>;
			device_type = "network";
			model = "TSEC";
			compatible = "gianfar";
			reg = <0x24000 0x1000>;
			ranges = <0x0 0x24000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <29 2 30  2 34 2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi0>;
			phy-handle = <&phy0>;
			phy-connection-type = "rgmii-id";

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-mdio";
				reg = <0x520 0x20>;

				phy0: ethernet-phy@0 {
					interrupt-parent = <&mpic>;
					interrupts = <10 1>;
					reg = <0>;
					device_type = "ethernet-phy";
				};
				phy1: ethernet-phy@1 {
					interrupt-parent = <&mpic>;
					interrupts = <10 1>;
					reg = <1>;
					device_type = "ethernet-phy";
				};
				phy2: ethernet-phy@2 {
					interrupt-parent = <&mpic>;
					interrupts = <10 1>;
					reg = <2>;
					device_type = "ethernet-phy";
				};
				phy3: ethernet-phy@3 {
					interrupt-parent = <&mpic>;
					interrupts = <10 1>;
					reg = <3>;
					device_type = "ethernet-phy";
				};
				tbi0: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		enet1: ethernet@25000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <1>;
			device_type = "network";
			model = "TSEC";
			compatible = "gianfar";
			reg = <0x25000 0x1000>;
			ranges = <0x0 0x25000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <35 2 36 2 40 2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi1>;
			phy-handle = <&phy1>;
			phy-connection-type = "rgmii-id";

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-tbi";
				reg = <0x520 0x20>;

				tbi1: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};
		
		enet2: ethernet@26000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <2>;
			device_type = "network";
			model = "TSEC";
			compatible = "gianfar";
			reg = <0x26000 0x1000>;
			ranges = <0x0 0x26000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <31 2 32 2 33 2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi2>;
			phy-handle = <&phy2>;
			phy-connection-type = "rgmii-id";

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-tbi";
				reg = <0x520 0x20>;

				tbi2: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		enet3: ethernet@27000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <3>;
			device_type = "network";
			model = "TSEC";
			compatible = "gianfar";
			reg = <0x27000 0x1000>;
			ranges = <0x0 0x27000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <37 2 38 2 39 2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi3>;
			phy-handle = <&phy3>;
			phy-connection-type = "rgmii-id";

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-tbi";
				reg = <0x520 0x20>;

				tbi3: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4500 0x100>;
			clock-frequency = <0>;
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4600 0x100>;
			clock-frequency = <0>;
			interrupts = <28 2>;
			interrupt-parent = <&mpic>;
		};

		mpic: pic@40000 {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x40000 0x40000>;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
		};

		global-utilities@e0000 {
			compatible = "fsl,mpc8641-guts";
			reg = <0xe0000 0x1000>;
			fsl,has-rstcr;
		};
	};

	pci0: pcie@ffe08000 {
		compatible = "fsl,mpc8641-pcie";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xffe08000 0x1000>;
		bus-range = <0x0 0xff>;
		ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
			  0x01000000 0x0 0x00000000 0xffc00000 0x0 0x00010000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <24 2>;
		interrupt-map-mask = <0xff00 0 0 7>;
		interrupt-map = <
			/* IDSEL 0x11 func 0 - PCI slot 1 */
			0x8800 0 0 1 &mpic 2 1
			0x8800 0 0 2 &mpic 3 1
			0x8800 0 0 3 &mpic 4 1
			0x8800 0 0 4 &mpic 1 1

			/* IDSEL 0x11 func 1 - PCI slot 1 */
			0x8900 0 0 1 &mpic 2 1
			0x8900 0 0 2 &mpic 3 1
			0x8900 0 0 3 &mpic 4 1
			0x8900 0 0 4 &mpic 1 1

			/* IDSEL 0x11 func 2 - PCI slot 1 */
			0x8a00 0 0 1 &mpic 2 1
			0x8a00 0 0 2 &mpic 3 1
			0x8a00 0 0 3 &mpic 4 1
			0x8a00 0 0 4 &mpic 1 1

			/* IDSEL 0x11 func 3 - PCI slot 1 */
			0x8b00 0 0 1 &mpic 2 1
			0x8b00 0 0 2 &mpic 3 1
			0x8b00 0 0 3 &mpic 4 1
			0x8b00 0 0 4 &mpic 1 1

			/* IDSEL 0x11 func 4 - PCI slot 1 */
			0x8c00 0 0 1 &mpic 2 1
			0x8c00 0 0 2 &mpic 3 1
			0x8c00 0 0 3 &mpic 4 1
			0x8c00 0 0 4 &mpic 1 1

			/* IDSEL 0x11 func 5 - PCI slot 1 */
			0x8d00 0 0 1 &mpic 2 1
			0x8d00 0 0 2 &mpic 3 1
			0x8d00 0 0 3 &mpic 4 1
			0x8d00 0 0 4 &mpic 1 1

			/* IDSEL 0x11 func 6 - PCI slot 1 */
			0x8e00 0 0 1 &mpic 2 1
			0x8e00 0 0 2 &mpic 3 1
			0x8e00 0 0 3 &mpic 4 1
			0x8e00 0 0 4 &mpic 1 1

			/* IDSEL 0x11 func 7 - PCI slot 1 */
			0x8f00 0 0 1 &mpic 2 1
			0x8f00 0 0 2 &mpic 3 1
			0x8f00 0 0 3 &mpic 4 1
			0x8f00 0 0 4 &mpic 1 1

			/* IDSEL 0x12 func 0 - PCI slot 2 */
			0x9000 0 0 1 &mpic 3 1
			0x9000 0 0 2 &mpic 4 1
			0x9000 0 0 3 &mpic 1 1
			0x9000 0 0 4 &mpic 2 1

			/* IDSEL 0x12 func 1 - PCI slot 2 */
			0x9100 0 0 1 &mpic 3 1
			0x9100 0 0 2 &mpic 4 1
			0x9100 0 0 3 &mpic 1 1
			0x9100 0 0 4 &mpic 2 1

			/* IDSEL 0x12 func 2 - PCI slot 2 */
			0x9200 0 0 1 &mpic 3 1
			0x9200 0 0 2 &mpic 4 1
			0x9200 0 0 3 &mpic 1 1
			0x9200 0 0 4 &mpic 2 1

			/* IDSEL 0x12 func 3 - PCI slot 2 */
			0x9300 0 0 1 &mpic 3 1
			0x9300 0 0 2 &mpic 4 1
			0x9300 0 0 3 &mpic 1 1
			0x9300 0 0 4 &mpic 2 1

			/* IDSEL 0x12 func 4 - PCI slot 2 */
			0x9400 0 0 1 &mpic 3 1
			0x9400 0 0 2 &mpic 4 1
			0x9400 0 0 3 &mpic 1 1
			0x9400 0 0 4 &mpic 2 1

			/* IDSEL 0x12 func 5 - PCI slot 2 */
			0x9500 0 0 1 &mpic 3 1
			0x9500 0 0 2 &mpic 4 1
			0x9500 0 0 3 &mpic 1 1
			0x9500 0 0 4 &mpic 2 1

			/* IDSEL 0x12 func 6 - PCI slot 2 */
			0x9600 0 0 1 &mpic 3 1
			0x9600 0 0 2 &mpic 4 1
			0x9600 0 0 3 &mpic 1 1
			0x9600 0 0 4 &mpic 2 1

			/* IDSEL 0x12 func 7 - PCI slot 2 */
			0x9700 0 0 1 &mpic 3 1
			0x9700 0 0 2 &mpic 4 1
			0x9700 0 0 3 &mpic 1 1
			0x9700 0 0 4 &mpic 2 1

			// IDSEL 0x1c  USB
			0xe000 0 0 1 &i8259 12 2
			0xe100 0 0 2 &i8259 9 2
			0xe200 0 0 3 &i8259 10 2
			0xe300 0 0 4 &i8259 11 2

			// IDSEL 0x1d  Audio
			0xe800 0 0 1 &i8259 6 2

			// IDSEL 0x1e Legacy
			0xf000 0 0 1 &i8259 7 2
			0xf100 0 0 1 &i8259 7 2

			// IDSEL 0x1f IDE/SATA
			0xf800 0 0 1 &i8259 14 2
			0xf900 0 0 1 &i8259 5 2
			>;

		pcie@0 {
			reg = <0 0 0 0 0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x02000000 0x0 0x80000000
				  0x02000000 0x0 0x80000000
				  0x0 0x20000000

				  0x01000000 0x0 0x00000000
				  0x01000000 0x0 0x00000000
				  0x0 0x00010000>;
			uli1575@0 {
				reg = <0 0 0 0 0>;
				#size-cells = <2>;
				#address-cells = <3>;
				ranges = <0x02000000 0x0 0x80000000
					  0x02000000 0x0 0x80000000
					  0x0 0x20000000
					  0x01000000 0x0 0x00000000
					  0x01000000 0x0 0x00000000
					  0x0 0x00010000>;
				isa@1e {
					device_type = "isa";
					#interrupt-cells = <2>;
					#size-cells = <1>;
					#address-cells = <2>;
					reg = <0xf000 0 0 0 0>;
					ranges = <1 0 0x01000000 0 0
						  0x00001000>;
					interrupt-parent = <&i8259>;

					i8259: interrupt-controller@20 {
						reg = <1 0x20 2
						       1 0xa0 2
						       1 0x4d0 2>;
						interrupt-controller;
						device_type = "interrupt-controller";
						#address-cells = <0>;
						#interrupt-cells = <2>;
						compatible = "chrp,iic";
						interrupts = <9 2>;
						interrupt-parent = <&mpic>;
					};

					i8042@60 {
						#size-cells = <0>;
						#address-cells = <1>;
						reg = <1 0x60 1 1 0x64 1>;
						interrupts = <1 3 12 3>;
						interrupt-parent =
							<&i8259>;

						keyboard@0 {
							reg = <0>;
							compatible = "pnpPNP,303";
						};

						mouse@1 {
							reg = <1>;
							compatible = "pnpPNP,f03";
						};
					};

					rtc@70 {
						compatible =
							"pnpPNP,b00";
						reg = <1 0x70 2>;
					};

					gpio@400 {
						reg = <1 0x400 0x80>;
					};
				};
			};
		};

	};

	pci1: pcie@ffe09000 {
		compatible = "fsl,mpc8641-pcie";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xffe09000 0x1000>;
		bus-range = <0 0xff>;
		ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
			  0x01000000 0x0 0x00000000 0xffc10000 0x0 0x00010000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <25 2>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <
			/* IDSEL 0x0 */
			0x0000 0 0 1 &mpic 4 1
			0x0000 0 0 2 &mpic 5 1
			0x0000 0 0 3 &mpic 6 1
			0x0000 0 0 4 &mpic 7 1
			>;
		pcie@0 {
			reg = <0 0 0 0 0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x02000000 0x0 0xa0000000
				  0x02000000 0x0 0xa0000000
				  0x0 0x20000000

				  0x01000000 0x0 0x00000000
				  0x01000000 0x0 0x00000000
				  0x0 0x00010000>;
		};
	};
/*
	rapidio0: rapidio@ffec0000 {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "fsl,rapidio-delta";
		reg = <0xffec0000 0x20000>;
		ranges = <0 0 0x80000000 0 0x20000000>;
		interrupt-parent = <&mpic>;
		// err_irq bell_outb_irq bell_inb_irq
		//	msg1_tx_irq msg1_rx_irq	msg2_tx_irq msg2_rx_irq
		interrupts = <48 2 49 2 50 2 53 2 54 2 55 2 56 2>;
	};
*/

};
Commit	Line	Data
707ba16f JL	1	/*
	2	* MPC8641 HPCN Device Tree Source
	3	*
	4	* Copyright 2006 Freescale Semiconductor Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*/
	11
6e050d4e	12	/dts-v1/;
707ba16f JL	13
	14	/ {
	15	model = "MPC8641HPCN";
06f35b4b	16	compatible = "fsl,mpc8641hpcn";
707ba16f JL	17	#address-cells = <1>;
	18	#size-cells = <1>;
	19
1c1d1672 JL	20	aliases {
	21	ethernet0 = &enet0;
	22	ethernet1 = &enet1;
	23	ethernet2 = &enet2;
	24	ethernet3 = &enet3;
	25	serial0 = &serial0;
	26	serial1 = &serial1;
	27	pci0 = &pci0;
	28	pci1 = &pci1;
47f80a32 BB	29	/*
	30	* Only one of Rapid IO or PCI can be present due to HW limitations and
	31	* due to the fact that the 2 now share address space in the new memory
	32	* map. The most likely case is that we have PCI, so comment out the
	33	* rapidio node. Leave it here for reference.
	34	*/
	35	/* rapidio0 = &rapidio0; */
1c1d1672 JL	36	};
1c1d1672 JL	37
707ba16f	38	cpus {
707ba16f JL	39	#address-cells = <1>;
	40	#size-cells = <0>;
	41
	42	PowerPC,8641@0 {
	43	device_type = "cpu";
	44	reg = <0>;
6e050d4e JL	45	d-cache-line-size = <32>;
	46	i-cache-line-size = <32>;
	47	d-cache-size = <32768>; // L1
	48	i-cache-size = <32768>; // L1
	49	timebase-frequency = <0>; // From uboot
707ba16f JL	50	bus-frequency = <0>; // From uboot
707ba16f JL	51	clock-frequency = <0>; // From uboot
707ba16f JL	52	};
	53	PowerPC,8641@1 {
	54	device_type = "cpu";
	55	reg = <1>;
6e050d4e JL	56	d-cache-line-size = <32>;
	57	i-cache-line-size = <32>;
	58	d-cache-size = <32768>;
	59	i-cache-size = <32768>;
	60	timebase-frequency = <0>; // From uboot
707ba16f JL	61	bus-frequency = <0>; // From uboot
707ba16f JL	62	clock-frequency = <0>; // From uboot
707ba16f JL	63	};
	64	};
	65
	66	memory {
	67	device_type = "memory";
6e050d4e	68	reg = <0x00000000 0x40000000>; // 1G at 0x0
707ba16f JL	69	};
707ba16f JL	70
47f80a32	71	localbus@ffe05000 {
0ac247d5 WF	72	#address-cells = <2>;
	73	#size-cells = <1>;
	74	compatible = "fsl,mpc8641-localbus", "simple-bus";
47f80a32	75	reg = <0xffe05000 0x1000>;
6e050d4e	76	interrupts = <19 2>;
0ac247d5 WF	77	interrupt-parent = <&mpic>;
0ac247d5 WF	78
47f80a32 BB	79	ranges = <0 0 0xef800000 0x00800000
	80	2 0 0xffdf8000 0x00008000
	81	3 0 0xffdf0000 0x00008000>;
0ac247d5 WF	82
	83	flash@0,0 {
	84	compatible = "cfi-flash";
6e050d4e	85	reg = <0 0 0x00800000>;
0ac247d5 WF	86	bank-width = <2>;
	87	device-width = <2>;
	88	#address-cells = <1>;
	89	#size-cells = <1>;
	90	partition@0 {
	91	label = "kernel";
6e050d4e	92	reg = <0x00000000 0x00300000>;
0ac247d5 WF	93	};
	94	partition@300000 {
	95	label = "firmware b";
6e050d4e	96	reg = <0x00300000 0x00100000>;
0ac247d5 WF	97	read-only;
	98	};
	99	partition@400000 {
	100	label = "fs";
6e050d4e	101	reg = <0x00400000 0x00300000>;
0ac247d5 WF	102	};
	103	partition@700000 {
	104	label = "firmware a";
6e050d4e	105	reg = <0x00700000 0x00100000>;
0ac247d5 WF	106	read-only;
	107	};
	108	};
	109	};
	110
47f80a32	111	soc8641@ffe00000 {
707ba16f JL	112	#address-cells = <1>;
707ba16f JL	113	#size-cells = <1>;
707ba16f	114	device_type = "soc";
0ac247d5	115	compatible = "simple-bus";
47f80a32	116	ranges = <0x00000000 0xffe00000 0x00100000>;
707ba16f JL	117	bus-frequency = <0>;
707ba16f JL	118
da385780 KG	119	mcm-law@0 {
	120	compatible = "fsl,mcm-law";
	121	reg = <0x0 0x1000>;
	122	fsl,num-laws = <10>;
	123	};
	124
	125	mcm@1000 {
	126	compatible = "fsl,mpc8641-mcm", "fsl,mcm";
	127	reg = <0x1000 0x1000>;
	128	interrupts = <17 2>;
	129	interrupt-parent = <&mpic>;
	130	};
	131
707ba16f	132	i2c@3000 {
ec9686c4 KG	133	#address-cells = <1>;
	134	#size-cells = <0>;
	135	cell-index = <0>;
707ba16f	136	compatible = "fsl-i2c";
6e050d4e JL	137	reg = <0x3000 0x100>;
6e050d4e JL	138	interrupts = <43 2>;
6d9065d8	139	interrupt-parent = <&mpic>;
707ba16f JL	140	dfsrr;
	141	};
	142
	143	i2c@3100 {
ec9686c4 KG	144	#address-cells = <1>;
	145	#size-cells = <0>;
	146	cell-index = <1>;
707ba16f	147	compatible = "fsl-i2c";
6e050d4e JL	148	reg = <0x3100 0x100>;
6e050d4e JL	149	interrupts = <43 2>;
6d9065d8	150	interrupt-parent = <&mpic>;
707ba16f JL	151	dfsrr;
	152	};
	153
dee80553 KG	154	dma@21300 {
	155	#address-cells = <1>;
	156	#size-cells = <1>;
	157	compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
	158	reg = <0x21300 0x4>;
	159	ranges = <0x0 0x21100 0x200>;
	160	cell-index = <0>;
	161	dma-channel@0 {
	162	compatible = "fsl,mpc8641-dma-channel",
	163	"fsl,eloplus-dma-channel";
	164	reg = <0x0 0x80>;
	165	cell-index = <0>;
	166	interrupt-parent = <&mpic>;
	167	interrupts = <20 2>;
	168	};
	169	dma-channel@80 {
	170	compatible = "fsl,mpc8641-dma-channel",
	171	"fsl,eloplus-dma-channel";
	172	reg = <0x80 0x80>;
	173	cell-index = <1>;
	174	interrupt-parent = <&mpic>;
	175	interrupts = <21 2>;
	176	};
	177	dma-channel@100 {
	178	compatible = "fsl,mpc8641-dma-channel",
	179	"fsl,eloplus-dma-channel";
	180	reg = <0x100 0x80>;
	181	cell-index = <2>;
	182	interrupt-parent = <&mpic>;
	183	interrupts = <22 2>;
	184	};
	185	dma-channel@180 {
	186	compatible = "fsl,mpc8641-dma-channel",
	187	"fsl,eloplus-dma-channel";
	188	reg = <0x180 0x80>;
	189	cell-index = <3>;
	190	interrupt-parent = <&mpic>;
	191	interrupts = <23 2>;
	192	};
	193	};
	194
1c1d1672	195	enet0: ethernet@24000 {
d8bc55fb AV	196	#address-cells = <1>;
d8bc55fb AV	197	#size-cells = <1>;
e77b28eb	198	cell-index = <0>;
707ba16f JL	199	device_type = "network";
	200	model = "TSEC";
	201	compatible = "gianfar";
6e050d4e	202	reg = <0x24000 0x1000>;
d8bc55fb	203	ranges = <0x0 0x24000 0x1000>;
eae98266	204	local-mac-address = [ 00 00 00 00 00 00 ];
6e050d4e	205	interrupts = <29 2 30 2 34 2>;
6d9065d8	206	interrupt-parent = <&mpic>;
b31a1d8b	207	tbi-handle = <&tbi0>;
6d9065d8	208	phy-handle = <&phy0>;
cc65185d	209	phy-connection-type = "rgmii-id";
d8bc55fb AV	210
	211	mdio@520 {
	212	#address-cells = <1>;
	213	#size-cells = <0>;
	214	compatible = "fsl,gianfar-mdio";
	215	reg = <0x520 0x20>;
	216
	217	phy0: ethernet-phy@0 {
	218	interrupt-parent = <&mpic>;
	219	interrupts = <10 1>;
	220	reg = <0>;
	221	device_type = "ethernet-phy";
	222	};
	223	phy1: ethernet-phy@1 {
	224	interrupt-parent = <&mpic>;
	225	interrupts = <10 1>;
	226	reg = <1>;
	227	device_type = "ethernet-phy";
	228	};
	229	phy2: ethernet-phy@2 {
	230	interrupt-parent = <&mpic>;
	231	interrupts = <10 1>;
	232	reg = <2>;
	233	device_type = "ethernet-phy";
	234	};
	235	phy3: ethernet-phy@3 {
	236	interrupt-parent = <&mpic>;
	237	interrupts = <10 1>;
	238	reg = <3>;
	239	device_type = "ethernet-phy";
	240	};
	241	tbi0: tbi-phy@11 {
	242	reg = <0x11>;
	243	device_type = "tbi-phy";
	244	};
	245	};
707ba16f JL	246	};
707ba16f JL	247
1c1d1672	248	enet1: ethernet@25000 {
d8bc55fb AV	249	#address-cells = <1>;
d8bc55fb AV	250	#size-cells = <1>;
e77b28eb	251	cell-index = <1>;
707ba16f JL	252	device_type = "network";
	253	model = "TSEC";
	254	compatible = "gianfar";
6e050d4e	255	reg = <0x25000 0x1000>;
d8bc55fb	256	ranges = <0x0 0x25000 0x1000>;
eae98266	257	local-mac-address = [ 00 00 00 00 00 00 ];
6e050d4e	258	interrupts = <35 2 36 2 40 2>;
6d9065d8	259	interrupt-parent = <&mpic>;
b31a1d8b	260	tbi-handle = <&tbi1>;
6d9065d8	261	phy-handle = <&phy1>;
cc65185d	262	phy-connection-type = "rgmii-id";
d8bc55fb AV	263
	264	mdio@520 {
	265	#address-cells = <1>;
	266	#size-cells = <0>;
	267	compatible = "fsl,gianfar-tbi";
	268	reg = <0x520 0x20>;
	269
	270	tbi1: tbi-phy@11 {
	271	reg = <0x11>;
	272	device_type = "tbi-phy";
	273	};
	274	};
707ba16f JL	275	};
707ba16f JL	276
1c1d1672	277	enet2: ethernet@26000 {
d8bc55fb AV	278	#address-cells = <1>;
d8bc55fb AV	279	#size-cells = <1>;
e77b28eb	280	cell-index = <2>;
707ba16f JL	281	device_type = "network";
	282	model = "TSEC";
	283	compatible = "gianfar";
6e050d4e	284	reg = <0x26000 0x1000>;
d8bc55fb	285	ranges = <0x0 0x26000 0x1000>;
eae98266	286	local-mac-address = [ 00 00 00 00 00 00 ];
6e050d4e	287	interrupts = <31 2 32 2 33 2>;
6d9065d8	288	interrupt-parent = <&mpic>;
b31a1d8b	289	tbi-handle = <&tbi2>;
6d9065d8	290	phy-handle = <&phy2>;
cc65185d	291	phy-connection-type = "rgmii-id";
d8bc55fb AV	292
	293	mdio@520 {
	294	#address-cells = <1>;
	295	#size-cells = <0>;
	296	compatible = "fsl,gianfar-tbi";
	297	reg = <0x520 0x20>;
	298
	299	tbi2: tbi-phy@11 {
	300	reg = <0x11>;
	301	device_type = "tbi-phy";
	302	};
	303	};
707ba16f JL	304	};
707ba16f JL	305
1c1d1672	306	enet3: ethernet@27000 {
d8bc55fb AV	307	#address-cells = <1>;
d8bc55fb AV	308	#size-cells = <1>;
e77b28eb	309	cell-index = <3>;
707ba16f JL	310	device_type = "network";
	311	model = "TSEC";
	312	compatible = "gianfar";
6e050d4e	313	reg = <0x27000 0x1000>;
d8bc55fb	314	ranges = <0x0 0x27000 0x1000>;
eae98266	315	local-mac-address = [ 00 00 00 00 00 00 ];
6e050d4e	316	interrupts = <37 2 38 2 39 2>;
6d9065d8	317	interrupt-parent = <&mpic>;
b31a1d8b	318	tbi-handle = <&tbi3>;
6d9065d8	319	phy-handle = <&phy3>;
cc65185d	320	phy-connection-type = "rgmii-id";
d8bc55fb AV	321
	322	mdio@520 {
	323	#address-cells = <1>;
	324	#size-cells = <0>;
	325	compatible = "fsl,gianfar-tbi";
	326	reg = <0x520 0x20>;
	327
	328	tbi3: tbi-phy@11 {
	329	reg = <0x11>;
	330	device_type = "tbi-phy";
	331	};
	332	};
707ba16f	333	};
1c1d1672 JL	334
1c1d1672 JL	335	serial0: serial@4500 {
ea082fa9	336	cell-index = <0>;
707ba16f JL	337	device_type = "serial";
707ba16f JL	338	compatible = "ns16550";
6e050d4e	339	reg = <0x4500 0x100>;
707ba16f	340	clock-frequency = <0>;
6e050d4e	341	interrupts = <42 2>;
6d9065d8	342	interrupt-parent = <&mpic>;
707ba16f JL	343	};
707ba16f JL	344
1c1d1672	345	serial1: serial@4600 {
ea082fa9	346	cell-index = <1>;
707ba16f JL	347	device_type = "serial";
707ba16f JL	348	compatible = "ns16550";
6e050d4e	349	reg = <0x4600 0x100>;
707ba16f	350	clock-frequency = <0>;
6e050d4e	351	interrupts = <28 2>;
6d9065d8	352	interrupt-parent = <&mpic>;
707ba16f JL	353	};
707ba16f JL	354
1b3c5cda	355	mpic: pic@40000 {
1b3c5cda KG	356	interrupt-controller;
	357	#address-cells = <0>;
	358	#interrupt-cells = <2>;
6e050d4e	359	reg = <0x40000 0x40000>;
1b3c5cda KG	360	compatible = "chrp,open-pic";
1b3c5cda KG	361	device_type = "open-pic";
1b3c5cda	362	};
e1c1575f KG	363
	364	global-utilities@e0000 {
	365	compatible = "fsl,mpc8641-guts";
6e050d4e	366	reg = <0xe0000 0x1000>;
e1c1575f KG	367	fsl,has-rstcr;
e1c1575f KG	368	};
1b3c5cda	369	};
707ba16f	370
47f80a32	371	pci0: pcie@ffe08000 {
1b3c5cda KG	372	compatible = "fsl,mpc8641-pcie";
	373	device_type = "pci";
	374	#interrupt-cells = <1>;
	375	#size-cells = <2>;
	376	#address-cells = <3>;
47f80a32	377	reg = <0xffe08000 0x1000>;
6e050d4e JL	378	bus-range = <0x0 0xff>;
6e050d4e JL	379	ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
47f80a32	380	0x01000000 0x0 0x00000000 0xffc00000 0x0 0x00010000>;
6e050d4e	381	clock-frequency = <33333333>;
1b3c5cda	382	interrupt-parent = <&mpic>;
6e050d4e JL	383	interrupts = <24 2>;
6e050d4e JL	384	interrupt-map-mask = <0xff00 0 0 7>;
1b3c5cda	385	interrupt-map = <
bebfa06c	386	/* IDSEL 0x11 func 0 - PCI slot 1 */
6e050d4e JL	387	0x8800 0 0 1 &mpic 2 1
	388	0x8800 0 0 2 &mpic 3 1
	389	0x8800 0 0 3 &mpic 4 1
	390	0x8800 0 0 4 &mpic 1 1
bebfa06c KG	391
bebfa06c KG	392	/* IDSEL 0x11 func 1 - PCI slot 1 */
6e050d4e JL	393	0x8900 0 0 1 &mpic 2 1
	394	0x8900 0 0 2 &mpic 3 1
	395	0x8900 0 0 3 &mpic 4 1
	396	0x8900 0 0 4 &mpic 1 1
bebfa06c KG	397
bebfa06c KG	398	/* IDSEL 0x11 func 2 - PCI slot 1 */
6e050d4e JL	399	0x8a00 0 0 1 &mpic 2 1
	400	0x8a00 0 0 2 &mpic 3 1
	401	0x8a00 0 0 3 &mpic 4 1
	402	0x8a00 0 0 4 &mpic 1 1
bebfa06c KG	403
bebfa06c KG	404	/* IDSEL 0x11 func 3 - PCI slot 1 */
6e050d4e JL	405	0x8b00 0 0 1 &mpic 2 1
	406	0x8b00 0 0 2 &mpic 3 1
	407	0x8b00 0 0 3 &mpic 4 1
	408	0x8b00 0 0 4 &mpic 1 1
bebfa06c KG	409
bebfa06c KG	410	/* IDSEL 0x11 func 4 - PCI slot 1 */
6e050d4e JL	411	0x8c00 0 0 1 &mpic 2 1
	412	0x8c00 0 0 2 &mpic 3 1
	413	0x8c00 0 0 3 &mpic 4 1
	414	0x8c00 0 0 4 &mpic 1 1
bebfa06c KG	415
bebfa06c KG	416	/* IDSEL 0x11 func 5 - PCI slot 1 */
6e050d4e JL	417	0x8d00 0 0 1 &mpic 2 1
	418	0x8d00 0 0 2 &mpic 3 1
	419	0x8d00 0 0 3 &mpic 4 1
	420	0x8d00 0 0 4 &mpic 1 1
bebfa06c KG	421
bebfa06c KG	422	/* IDSEL 0x11 func 6 - PCI slot 1 */
6e050d4e JL	423	0x8e00 0 0 1 &mpic 2 1
	424	0x8e00 0 0 2 &mpic 3 1
	425	0x8e00 0 0 3 &mpic 4 1
	426	0x8e00 0 0 4 &mpic 1 1
bebfa06c KG	427
bebfa06c KG	428	/* IDSEL 0x11 func 7 - PCI slot 1 */
6e050d4e JL	429	0x8f00 0 0 1 &mpic 2 1
	430	0x8f00 0 0 2 &mpic 3 1
	431	0x8f00 0 0 3 &mpic 4 1
	432	0x8f00 0 0 4 &mpic 1 1
bebfa06c KG	433
bebfa06c KG	434	/* IDSEL 0x12 func 0 - PCI slot 2 */
6e050d4e JL	435	0x9000 0 0 1 &mpic 3 1
	436	0x9000 0 0 2 &mpic 4 1
	437	0x9000 0 0 3 &mpic 1 1
	438	0x9000 0 0 4 &mpic 2 1
bebfa06c KG	439
bebfa06c KG	440	/* IDSEL 0x12 func 1 - PCI slot 2 */
6e050d4e JL	441	0x9100 0 0 1 &mpic 3 1
	442	0x9100 0 0 2 &mpic 4 1
	443	0x9100 0 0 3 &mpic 1 1
	444	0x9100 0 0 4 &mpic 2 1
bebfa06c KG	445
bebfa06c KG	446	/* IDSEL 0x12 func 2 - PCI slot 2 */
6e050d4e JL	447	0x9200 0 0 1 &mpic 3 1
	448	0x9200 0 0 2 &mpic 4 1
	449	0x9200 0 0 3 &mpic 1 1
	450	0x9200 0 0 4 &mpic 2 1
bebfa06c KG	451
bebfa06c KG	452	/* IDSEL 0x12 func 3 - PCI slot 2 */
6e050d4e JL	453	0x9300 0 0 1 &mpic 3 1
	454	0x9300 0 0 2 &mpic 4 1
	455	0x9300 0 0 3 &mpic 1 1
	456	0x9300 0 0 4 &mpic 2 1
bebfa06c KG	457
bebfa06c KG	458	/* IDSEL 0x12 func 4 - PCI slot 2 */
6e050d4e JL	459	0x9400 0 0 1 &mpic 3 1
	460	0x9400 0 0 2 &mpic 4 1
	461	0x9400 0 0 3 &mpic 1 1
	462	0x9400 0 0 4 &mpic 2 1
bebfa06c KG	463
bebfa06c KG	464	/* IDSEL 0x12 func 5 - PCI slot 2 */
6e050d4e JL	465	0x9500 0 0 1 &mpic 3 1
	466	0x9500 0 0 2 &mpic 4 1
	467	0x9500 0 0 3 &mpic 1 1
	468	0x9500 0 0 4 &mpic 2 1
bebfa06c KG	469
bebfa06c KG	470	/* IDSEL 0x12 func 6 - PCI slot 2 */
6e050d4e JL	471	0x9600 0 0 1 &mpic 3 1
	472	0x9600 0 0 2 &mpic 4 1
	473	0x9600 0 0 3 &mpic 1 1
	474	0x9600 0 0 4 &mpic 2 1
bebfa06c KG	475
bebfa06c KG	476	/* IDSEL 0x12 func 7 - PCI slot 2 */
6e050d4e JL	477	0x9700 0 0 1 &mpic 3 1
	478	0x9700 0 0 2 &mpic 4 1
	479	0x9700 0 0 3 &mpic 1 1
	480	0x9700 0 0 4 &mpic 2 1
707ba16f	481
1b3c5cda	482	// IDSEL 0x1c USB
6e050d4e JL	483	0xe000 0 0 1 &i8259 12 2
	484	0xe100 0 0 2 &i8259 9 2
	485	0xe200 0 0 3 &i8259 10 2
ba1616d9	486	0xe300 0 0 4 &i8259 11 2
707ba16f	487
1b3c5cda	488	// IDSEL 0x1d Audio
6e050d4e	489	0xe800 0 0 1 &i8259 6 2
707ba16f	490
1b3c5cda	491	// IDSEL 0x1e Legacy
6e050d4e JL	492	0xf000 0 0 1 &i8259 7 2
6e050d4e JL	493	0xf100 0 0 1 &i8259 7 2
1b3c5cda KG	494
1b3c5cda KG	495	// IDSEL 0x1f IDE/SATA
6e050d4e JL	496	0xf800 0 0 1 &i8259 14 2
6e050d4e JL	497	0xf900 0 0 1 &i8259 5 2
1b3c5cda KG	498	>;
	499
	500	pcie@0 {
	501	reg = <0 0 0 0 0>;
	502	#size-cells = <2>;
	503	#address-cells = <3>;
	504	device_type = "pci";
6e050d4e JL	505	ranges = <0x02000000 0x0 0x80000000
	506	0x02000000 0x0 0x80000000
	507	0x0 0x20000000
1b3c5cda	508
6e050d4e JL	509	0x01000000 0x0 0x00000000
6e050d4e JL	510	0x01000000 0x0 0x00000000
47f80a32	511	0x0 0x00010000>;
dfac6faf WF	512	uli1575@0 {
	513	reg = <0 0 0 0 0>;
	514	#size-cells = <2>;
	515	#address-cells = <3>;
6e050d4e JL	516	ranges = <0x02000000 0x0 0x80000000
	517	0x02000000 0x0 0x80000000
	518	0x0 0x20000000
	519	0x01000000 0x0 0x00000000
	520	0x01000000 0x0 0x00000000
47f80a32	521	0x0 0x00010000>;
1b3c5cda KG	522	isa@1e {
	523	device_type = "isa";
	524	#interrupt-cells = <2>;
	525	#size-cells = <1>;
	526	#address-cells = <2>;
6e050d4e JL	527	reg = <0xf000 0 0 0 0>;
	528	ranges = <1 0 0x01000000 0 0
	529	0x00001000>;
1b3c5cda	530	interrupt-parent = <&i8259>;
dfac6faf	531
1b3c5cda	532	i8259: interrupt-controller@20 {
6e050d4e JL	533	reg = <1 0x20 2
	534	1 0xa0 2
	535	1 0x4d0 2>;
1b3c5cda KG	536	interrupt-controller;
	537	device_type = "interrupt-controller";
	538	#address-cells = <0>;
dfac6faf	539	#interrupt-cells = <2>;
1b3c5cda KG	540	compatible = "chrp,iic";
	541	interrupts = <9 2>;
	542	interrupt-parent = <&mpic>;
	543	};
dfac6faf	544
1b3c5cda KG	545	i8042@60 {
	546	#size-cells = <0>;
	547	#address-cells = <1>;
6e050d4e JL	548	reg = <1 0x60 1 1 0x64 1>;
6e050d4e JL	549	interrupts = <1 3 12 3>;
1b3c5cda KG	550	interrupt-parent =
1b3c5cda KG	551	<&i8259>;
dfac6faf	552
1b3c5cda KG	553	keyboard@0 {
	554	reg = <0>;
	555	compatible = "pnpPNP,303";
dfac6faf WF	556	};
dfac6faf WF	557
1b3c5cda KG	558	mouse@1 {
	559	reg = <1>;
	560	compatible = "pnpPNP,f03";
dfac6faf	561	};
1b3c5cda	562	};
dfac6faf	563
1b3c5cda KG	564	rtc@70 {
	565	compatible =
	566	"pnpPNP,b00";
6e050d4e	567	reg = <1 0x70 2>;
1b3c5cda KG	568	};
	569
	570	gpio@400 {
6e050d4e	571	reg = <1 0x400 0x80>;
dfac6faf WF	572	};
dfac6faf WF	573	};
707ba16f	574	};
707ba16f	575	};
e0e3c8d4	576
1b3c5cda KG	577	};
1b3c5cda KG	578
47f80a32	579	pci1: pcie@ffe09000 {
1b3c5cda KG	580	compatible = "fsl,mpc8641-pcie";
	581	device_type = "pci";
	582	#interrupt-cells = <1>;
	583	#size-cells = <2>;
	584	#address-cells = <3>;
47f80a32	585	reg = <0xffe09000 0x1000>;
6e050d4e JL	586	bus-range = <0 0xff>;
6e050d4e JL	587	ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
47f80a32	588	0x01000000 0x0 0x00000000 0xffc10000 0x0 0x00010000>;
6e050d4e	589	clock-frequency = <33333333>;
1b3c5cda	590	interrupt-parent = <&mpic>;
6e050d4e JL	591	interrupts = <25 2>;
6e050d4e JL	592	interrupt-map-mask = <0xf800 0 0 7>;
1b3c5cda KG	593	interrupt-map = <
1b3c5cda KG	594	/* IDSEL 0x0 */
6e050d4e JL	595	0x0000 0 0 1 &mpic 4 1
	596	0x0000 0 0 2 &mpic 5 1
	597	0x0000 0 0 3 &mpic 6 1
	598	0x0000 0 0 4 &mpic 7 1
1b3c5cda KG	599	>;
	600	pcie@0 {
	601	reg = <0 0 0 0 0>;
e0e3c8d4 ZW	602	#size-cells = <2>;
e0e3c8d4 ZW	603	#address-cells = <3>;
1b3c5cda	604	device_type = "pci";
6e050d4e JL	605	ranges = <0x02000000 0x0 0xa0000000
	606	0x02000000 0x0 0xa0000000
	607	0x0 0x20000000
e0e3c8d4	608
6e050d4e JL	609	0x01000000 0x0 0x00000000
6e050d4e JL	610	0x01000000 0x0 0x00000000
47f80a32	611	0x0 0x00010000>;
707ba16f JL	612	};
707ba16f JL	613	};
47f80a32 BB	614	/*
47f80a32 BB	615	rapidio0: rapidio@ffec0000 {
56fde1ff ZW	616	#address-cells = <2>;
	617	#size-cells = <2>;
	618	compatible = "fsl,rapidio-delta";
47f80a32 BB	619	reg = <0xffec0000 0x20000>;
47f80a32 BB	620	ranges = <0 0 0x80000000 0 0x20000000>;
56fde1ff	621	interrupt-parent = <&mpic>;
47f80a32 BB	622	// err_irq bell_outb_irq bell_inb_irq
47f80a32 BB	623	// msg1_tx_irq msg1_rx_irq msg2_tx_irq msg2_rx_irq
56fde1ff ZW	624	interrupts = <48 2 49 2 50 2 53 2 54 2 55 2 56 2>;
56fde1ff ZW	625	};
47f80a32 BB	626	*/
47f80a32 BB	627
707ba16f	628	};