[deliverable/linux.git] / arch / powerpc / boot / dts / p3041ds.dts

/*
 * P3041DS Device Tree Source
 *
 * Copyright 2010-2011 Freescale Semiconductor Inc.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of Freescale Semiconductor nor the
 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 *
 * ALTERNATIVELY, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") as published by the Free Software
 * Foundation, either version 2 of that License or (at your option) any
 * later version.
 *
 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/include/ "fsl/p3041si-pre.dtsi"

/ {
	model = "fsl,P3041DS";
	compatible = "fsl,P3041DS";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&mpic>;

	memory {
		device_type = "memory";
	};

	dcsr: dcsr@f00000000 {
		ranges = <0x00000000 0xf 0x00000000 0x01008000>;
	};

	soc: soc@ffe000000 {
		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
		reg = <0xf 0xfe000000 0 0x00001000>;
		spi@110000 {
			flash@0 {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "spansion,s25sl12801";
				reg = <0>;
				spi-max-frequency = <35000000>; /* input clock */
				partition@u-boot {
					label = "u-boot";
					reg = <0x00000000 0x00100000>;
					read-only;
				};
				partition@kernel {
					label = "kernel";
					reg = <0x00100000 0x00500000>;
					read-only;
				};
				partition@dtb {
					label = "dtb";
					reg = <0x00600000 0x00100000>;
					read-only;
				};
				partition@fs {
					label = "file system";
					reg = <0x00700000 0x00900000>;
				};
			};
		};

		i2c@118100 {
			eeprom@51 {
				compatible = "at24,24c256";
				reg = <0x51>;
			};
			eeprom@52 {
				compatible = "at24,24c256";
				reg = <0x52>;
			};
		};

		i2c@119100 {
			rtc@68 {
				compatible = "dallas,ds3232";
				reg = <0x68>;
				interrupts = <0x1 0x1 0 0>;
			};
			adt7461@4c {
				compatible = "adi,adt7461";
				reg = <0x4c>;
			};
		};
	};

	rio: rapidio@ffe0c0000 {
		reg = <0xf 0xfe0c0000 0 0x11000>;

		port1 {
			ranges = <0 0 0xc 0x20000000 0 0x10000000>;
		};
		port2 {
			ranges = <0 0 0xc 0x30000000 0 0x10000000>;
		};
	};

	lbc: localbus@ffe124000 {
		reg = <0xf 0xfe124000 0 0x1000>;
		ranges = <0 0 0xf 0xe8000000 0x08000000
			  2 0 0xf 0xffa00000 0x00040000
			  3 0 0xf 0xffdf0000 0x00008000>;

		flash@0,0 {
			compatible = "cfi-flash";
			reg = <0 0 0x08000000>;
			bank-width = <2>;
			device-width = <2>;
		};

		nand@2,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,elbc-fcm-nand";
			reg = <0x2 0x0 0x40000>;

			partition@0 {
				label = "NAND U-Boot Image";
				reg = <0x0 0x02000000>;
				read-only;
			};

			partition@2000000 {
				label = "NAND Root File System";
				reg = <0x02000000 0x10000000>;
			};

			partition@12000000 {
				label = "NAND Compressed RFS Image";
				reg = <0x12000000 0x08000000>;
			};

			partition@1a000000 {
				label = "NAND Linux Kernel Image";
				reg = <0x1a000000 0x04000000>;
			};

			partition@1e000000 {
				label = "NAND DTB Image";
				reg = <0x1e000000 0x01000000>;
			};

			partition@1f000000 {
				label = "NAND Writable User area";
				reg = <0x1f000000 0x21000000>;
			};
		};

		board-control@3,0 {
			compatible = "fsl,p3041ds-fpga", "fsl,fpga-ngpixis";
			reg = <3 0 0x30>;
		};
	};

	pci0: pcie@ffe200000 {
		reg = <0xf 0xfe200000 0 0x1000>;
		ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
			  0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
		pcie@0 {
			ranges = <0x02000000 0 0xe0000000
				  0x02000000 0 0xe0000000
				  0 0x20000000

				  0x01000000 0 0x00000000
				  0x01000000 0 0x00000000
				  0 0x00010000>;
		};
	};

	pci1: pcie@ffe201000 {
		reg = <0xf 0xfe201000 0 0x1000>;
		ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
			  0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
		pcie@0 {
			ranges = <0x02000000 0 0xe0000000
				  0x02000000 0 0xe0000000
				  0 0x20000000

				  0x01000000 0 0x00000000
				  0x01000000 0 0x00000000
				  0 0x00010000>;
		};
	};

	pci2: pcie@ffe202000 {
		reg = <0xf 0xfe202000 0 0x1000>;
		ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
			  0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
		pcie@0 {
			ranges = <0x02000000 0 0xe0000000
				  0x02000000 0 0xe0000000
				  0 0x20000000

				  0x01000000 0 0x00000000
				  0x01000000 0 0x00000000
				  0 0x00010000>;
		};
	};

	pci3: pcie@ffe203000 {
		reg = <0xf 0xfe203000 0 0x1000>;
		ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
			  0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
		pcie@0 {
			ranges = <0x02000000 0 0xe0000000
				  0x02000000 0 0xe0000000
				  0 0x20000000

				  0x01000000 0 0x00000000
				  0x01000000 0 0x00000000
				  0 0x00010000>;
		};
	};
};

/include/ "fsl/p3041si-post.dtsi"
Commit	Line	Data
e181877d KG	1	/*
	2	* P3041DS Device Tree Source
	3	*
	4	* Copyright 2010-2011 Freescale Semiconductor Inc.
	5	*
	6	* Redistribution and use in source and binary forms, with or without
	7	* modification, are permitted provided that the following conditions are met:
	8	* * Redistributions of source code must retain the above copyright
	9	* notice, this list of conditions and the following disclaimer.
	10	* * Redistributions in binary form must reproduce the above copyright
	11	* notice, this list of conditions and the following disclaimer in the
	12	* documentation and/or other materials provided with the distribution.
	13	* * Neither the name of Freescale Semiconductor nor the
	14	* names of its contributors may be used to endorse or promote products
	15	* derived from this software without specific prior written permission.
	16	*
	17	*
	18	* ALTERNATIVELY, this software may be distributed under the terms of the
	19	* GNU General Public License ("GPL") as published by the Free Software
	20	* Foundation, either version 2 of that License or (at your option) any
	21	* later version.
	22	*
	23	* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
	24	* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	25	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	26	* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
	27	* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	28	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	29	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	30	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	31	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	32	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	33	*/
	34
b4c3804d	35	/include/ "fsl/p3041si-pre.dtsi"
e181877d KG	36
	37	/ {
	38	model = "fsl,P3041DS";
	39	compatible = "fsl,P3041DS";
	40	#address-cells = <2>;
	41	#size-cells = <2>;
	42	interrupt-parent = <&mpic>;
	43
e181877d KG	44	memory {
	45	device_type = "memory";
	46	};
	47
b9df0223 SG	48	dcsr: dcsr@f00000000 {
	49	ranges = <0x00000000 0xf 0x00000000 0x01008000>;
	50	};
	51
e181877d	52	soc: soc@ffe000000 {
b4c3804d KG	53	ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
b4c3804d KG	54	reg = <0xf 0xfe000000 0 0x00001000>;
e181877d	55	spi@110000 {
e181877d KG	56	flash@0 {
	57	#address-cells = <1>;
	58	#size-cells = <1>;
	59	compatible = "spansion,s25sl12801";
	60	reg = <0>;
e1bd5d8b	61	spi-max-frequency = <35000000>; /* input clock */
e181877d KG	62	partition@u-boot {
	63	label = "u-boot";
	64	reg = <0x00000000 0x00100000>;
	65	read-only;
	66	};
	67	partition@kernel {
	68	label = "kernel";
	69	reg = <0x00100000 0x00500000>;
	70	read-only;
	71	};
	72	partition@dtb {
	73	label = "dtb";
	74	reg = <0x00600000 0x00100000>;
	75	read-only;
	76	};
	77	partition@fs {
	78	label = "file system";
	79	reg = <0x00700000 0x00900000>;
	80	};
	81	};
	82	};
	83
e181877d	84	i2c@118100 {
e181877d KG	85	eeprom@51 {
	86	compatible = "at24,24c256";
	87	reg = <0x51>;
	88	};
	89	eeprom@52 {
	90	compatible = "at24,24c256";
	91	reg = <0x52>;
	92	};
	93	};
	94
e181877d	95	i2c@119100 {
e181877d KG	96	rtc@68 {
	97	compatible = "dallas,ds3232";
	98	reg = <0x68>;
	99	interrupts = <0x1 0x1 0 0>;
	100	};
17ae4f0a JH	101	adt7461@4c {
	102	compatible = "adi,adt7461";
	103	reg = <0x4c>;
	104	};
e181877d	105	};
e181877d KG	106	};
e181877d KG	107
54986964 KG	108	rio: rapidio@ffe0c0000 {
	109	reg = <0xf 0xfe0c0000 0 0x11000>;
	110
	111	port1 {
	112	ranges = <0 0 0xc 0x20000000 0 0x10000000>;
	113	};
	114	port2 {
	115	ranges = <0 0 0xc 0x30000000 0 0x10000000>;
	116	};
	117	};
	118
b4c3804d	119	lbc: localbus@ffe124000 {
e181877d	120	reg = <0xf 0xfe124000 0 0x1000>;
e181877d	121	ranges = <0 0 0xf 0xe8000000 0x08000000
04243c4d	122	2 0 0xf 0xffa00000 0x00040000
e181877d KG	123	3 0 0xf 0xffdf0000 0x00008000>;
	124
	125	flash@0,0 {
	126	compatible = "cfi-flash";
	127	reg = <0 0 0x08000000>;
	128	bank-width = <2>;
	129	device-width = <2>;
	130	};
	131
04243c4d LX	132	nand@2,0 {
	133	#address-cells = <1>;
	134	#size-cells = <1>;
	135	compatible = "fsl,elbc-fcm-nand";
	136	reg = <0x2 0x0 0x40000>;
	137
	138	partition@0 {
	139	label = "NAND U-Boot Image";
	140	reg = <0x0 0x02000000>;
	141	read-only;
	142	};
	143
	144	partition@2000000 {
	145	label = "NAND Root File System";
	146	reg = <0x02000000 0x10000000>;
	147	};
	148
	149	partition@12000000 {
	150	label = "NAND Compressed RFS Image";
	151	reg = <0x12000000 0x08000000>;
	152	};
	153
	154	partition@1a000000 {
	155	label = "NAND Linux Kernel Image";
	156	reg = <0x1a000000 0x04000000>;
	157	};
	158
	159	partition@1e000000 {
	160	label = "NAND DTB Image";
	161	reg = <0x1e000000 0x01000000>;
	162	};
	163
	164	partition@1f000000 {
	165	label = "NAND Writable User area";
	166	reg = <0x1f000000 0x21000000>;
	167	};
	168	};
	169
e181877d	170	board-control@3,0 {
499ccb27 TT	171	compatible = "fsl,p3041ds-fpga", "fsl,fpga-ngpixis";
499ccb27 TT	172	reg = <3 0 0x30>;
e181877d KG	173	};
	174	};
	175
	176	pci0: pcie@ffe200000 {
e181877d	177	reg = <0xf 0xfe200000 0 0x1000>;
e181877d KG	178	ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
e181877d KG	179	0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
e181877d	180	pcie@0 {
e181877d KG	181	ranges = <0x02000000 0 0xe0000000
	182	0x02000000 0 0xe0000000
	183	0 0x20000000
	184
	185	0x01000000 0 0x00000000
	186	0x01000000 0 0x00000000
	187	0 0x00010000>;
	188	};
	189	};
	190
	191	pci1: pcie@ffe201000 {
e181877d	192	reg = <0xf 0xfe201000 0 0x1000>;
e181877d KG	193	ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
e181877d KG	194	0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
e181877d	195	pcie@0 {
e181877d KG	196	ranges = <0x02000000 0 0xe0000000
	197	0x02000000 0 0xe0000000
	198	0 0x20000000
	199
	200	0x01000000 0 0x00000000
	201	0x01000000 0 0x00000000
	202	0 0x00010000>;
	203	};
	204	};
	205
	206	pci2: pcie@ffe202000 {
e181877d	207	reg = <0xf 0xfe202000 0 0x1000>;
e181877d KG	208	ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
e181877d KG	209	0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
e181877d	210	pcie@0 {
e181877d KG	211	ranges = <0x02000000 0 0xe0000000
	212	0x02000000 0 0xe0000000
	213	0 0x20000000
	214
	215	0x01000000 0 0x00000000
	216	0x01000000 0 0x00000000
	217	0 0x00010000>;
	218	};
	219	};
	220
	221	pci3: pcie@ffe203000 {
e181877d	222	reg = <0xf 0xfe203000 0 0x1000>;
e181877d KG	223	ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
e181877d KG	224	0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
e181877d	225	pcie@0 {
e181877d KG	226	ranges = <0x02000000 0 0xe0000000
	227	0x02000000 0 0xe0000000
	228	0 0x20000000
	229
	230	0x01000000 0 0x00000000
	231	0x01000000 0 0x00000000
	232	0 0x00010000>;
	233	};
	234	};
	235	};
b4c3804d KG	236
b4c3804d KG	237	/include/ "fsl/p3041si-post.dtsi"