[deliverable/linux.git] / arch / powerpc / boot / dts / p3060qds.dts

/*
 * P3060QDS Device Tree Source
 *
 * Copyright 2011 Freescale Semiconductor Inc.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of Freescale Semiconductor nor the
 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 *
 * ALTERNATIVELY, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") as published by the Free Software
 * Foundation, either version 2 of that License or (at your option) any
 * later version.
 *
 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/include/ "fsl/p3060si-pre.dtsi"

/ {
	model = "fsl,P3060QDS";
	compatible = "fsl,P3060QDS";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&mpic>;

	memory {
		device_type = "memory";
	};

	dcsr: dcsr@f00000000 {
		ranges = <0x00000000 0xf 0x00000000 0x01008000>;
	};

	soc: soc@ffe000000 {
		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
		reg = <0xf 0xfe000000 0 0x00001000>;
		spi@110000 {
			flash@0 {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "spansion,s25sl12801";
				reg = <0>;
				spi-max-frequency = <40000000>; /* input clock */
				partition@u-boot {
					label = "u-boot";
					reg = <0x00000000 0x00100000>;
					read-only;
				};
				partition@kernel {
					label = "kernel";
					reg = <0x00100000 0x00500000>;
					read-only;
				};
				partition@dtb {
					label = "dtb";
					reg = <0x00600000 0x00100000>;
					read-only;
				};
				partition@fs {
					label = "file system";
					reg = <0x00700000 0x00900000>;
				};
			};
			flash@1 {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "spansion,en25q32b";
				reg = <1>;
				spi-max-frequency = <40000000>; /* input clock */
				partition@spi1 {
					label = "spi1";
					reg = <0x00000000 0x00400000>;
				};
			};
			flash@2 {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "atmel,at45db081d";
				reg = <2>;
				spi-max-frequency = <40000000>; /* input clock */
				partition@spi1 {
					label = "spi2";
					reg = <0x00000000 0x00100000>;
				};
			};
			flash@3 {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "spansion,sst25wf040";
				reg = <3>;
				spi-max-frequency = <40000000>; /* input clock */
				partition@spi3 {
					label = "spi3";
					reg = <0x00000000 0x00080000>;
				};
			};
		};

		i2c@118000 {
			eeprom@51 {
				compatible = "at24,24c256";
				reg = <0x51>;
			};
			eeprom@53 {
				compatible = "at24,24c256";
				reg = <0x53>;
			};
			rtc@68 {
				compatible = "dallas,ds3232";
				reg = <0x68>;
				interrupts = <0x1 0x1 0 0>;
			};
		};

		usb0: usb@210000 {
			phy_type = "ulpi";
		};

		usb1: usb@211000 {
			dr_mode = "host";
			phy_type = "ulpi";
		};
	};

	rio: rapidio@ffe0c0000 {
		reg = <0xf 0xfe0c0000 0 0x11000>;

		port1 {
			ranges = <0 0 0xc 0x20000000 0 0x10000000>;
		};
		port2 {
			ranges = <0 0 0xc 0x30000000 0 0x10000000>;
		};
	};

	lbc: localbus@ffe124000 {
		reg = <0xf 0xfe124000 0 0x1000>;
		ranges = <0 0 0xf 0xe8000000 0x08000000
			  2 0 0xf 0xffa00000 0x00040000
			  3 0 0xf 0xffdf0000 0x00008000>;

		flash@0,0 {
			compatible = "cfi-flash";
			reg = <0 0 0x08000000>;
			bank-width = <2>;
			device-width = <2>;
		};

		nand@2,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,elbc-fcm-nand";
			reg = <0x2 0x0 0x40000>;

			partition@0 {
				label = "NAND U-Boot Image";
				reg = <0x0 0x02000000>;
				read-only;
			};

			partition@2000000 {
				label = "NAND Root File System";
				reg = <0x02000000 0x10000000>;
			};

			partition@12000000 {
				label = "NAND Compressed RFS Image";
				reg = <0x12000000 0x08000000>;
			};

			partition@1a000000 {
				label = "NAND Linux Kernel Image";
				reg = <0x1a000000 0x04000000>;
			};

			partition@1e000000 {
				label = "NAND DTB Image";
				reg = <0x1e000000 0x01000000>;
			};

			partition@1f000000 {
				label = "NAND Writable User area";
				reg = <0x1f000000 0x21000000>;
			};
		};

		board-control@3,0 {
			compatible = "fsl,p3060qds-fpga", "fsl,fpga-qixis";
			reg = <3 0 0x100>;
		};
	};

	pci0: pcie@ffe200000 {
		reg = <0xf 0xfe200000 0 0x1000>;
		ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
			  0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
		pcie@0 {
			ranges = <0x02000000 0 0xe0000000
				  0x02000000 0 0xe0000000
				  0 0x20000000

				  0x01000000 0 0x00000000
				  0x01000000 0 0x00000000
				  0 0x00010000>;
		};
	};

	pci1: pcie@ffe201000 {
		reg = <0xf 0xfe201000 0 0x1000>;
		ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
			  0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
		pcie@0 {
			ranges = <0x02000000 0 0xe0000000
				  0x02000000 0 0xe0000000
				  0 0x20000000

				  0x01000000 0 0x00000000
				  0x01000000 0 0x00000000
				  0 0x00010000>;
		};
	};
};

/include/ "fsl/p3060si-post.dtsi"
Commit	Line	Data
96cc017c SL	1	/*
	2	* P3060QDS Device Tree Source
	3	*
	4	* Copyright 2011 Freescale Semiconductor Inc.
	5	*
	6	* Redistribution and use in source and binary forms, with or without
	7	* modification, are permitted provided that the following conditions are met:
	8	* * Redistributions of source code must retain the above copyright
	9	* notice, this list of conditions and the following disclaimer.
	10	* * Redistributions in binary form must reproduce the above copyright
	11	* notice, this list of conditions and the following disclaimer in the
	12	* documentation and/or other materials provided with the distribution.
	13	* * Neither the name of Freescale Semiconductor nor the
	14	* names of its contributors may be used to endorse or promote products
	15	* derived from this software without specific prior written permission.
	16	*
	17	*
	18	* ALTERNATIVELY, this software may be distributed under the terms of the
	19	* GNU General Public License ("GPL") as published by the Free Software
	20	* Foundation, either version 2 of that License or (at your option) any
	21	* later version.
	22	*
	23	* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
	24	* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	25	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	26	* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
	27	* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	28	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	29	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	30	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	31	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	32	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	33	*/
	34
8389c823	35	/include/ "fsl/p3060si-pre.dtsi"
96cc017c SL	36
	37	/ {
	38	model = "fsl,P3060QDS";
	39	compatible = "fsl,P3060QDS";
	40	#address-cells = <2>;
	41	#size-cells = <2>;
	42	interrupt-parent = <&mpic>;
	43
	44	memory {
	45	device_type = "memory";
	46	};
	47
	48	dcsr: dcsr@f00000000 {
	49	ranges = <0x00000000 0xf 0x00000000 0x01008000>;
	50	};
	51
	52	soc: soc@ffe000000 {
8389c823 KG	53	ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
8389c823 KG	54	reg = <0xf 0xfe000000 0 0x00001000>;
96cc017c SL	55	spi@110000 {
	56	flash@0 {
	57	#address-cells = <1>;
	58	#size-cells = <1>;
	59	compatible = "spansion,s25sl12801";
	60	reg = <0>;
	61	spi-max-frequency = <40000000>; /* input clock */
	62	partition@u-boot {
	63	label = "u-boot";
	64	reg = <0x00000000 0x00100000>;
	65	read-only;
	66	};
	67	partition@kernel {
	68	label = "kernel";
	69	reg = <0x00100000 0x00500000>;
	70	read-only;
	71	};
	72	partition@dtb {
	73	label = "dtb";
	74	reg = <0x00600000 0x00100000>;
	75	read-only;
	76	};
	77	partition@fs {
	78	label = "file system";
	79	reg = <0x00700000 0x00900000>;
	80	};
	81	};
	82	flash@1 {
	83	#address-cells = <1>;
	84	#size-cells = <1>;
	85	compatible = "spansion,en25q32b";
	86	reg = <1>;
	87	spi-max-frequency = <40000000>; /* input clock */
	88	partition@spi1 {
	89	label = "spi1";
	90	reg = <0x00000000 0x00400000>;
	91	};
	92	};
	93	flash@2 {
	94	#address-cells = <1>;
	95	#size-cells = <1>;
	96	compatible = "atmel,at45db081d";
	97	reg = <2>;
	98	spi-max-frequency = <40000000>; /* input clock */
	99	partition@spi1 {
	100	label = "spi2";
	101	reg = <0x00000000 0x00100000>;
	102	};
	103	};
	104	flash@3 {
	105	#address-cells = <1>;
	106	#size-cells = <1>;
	107	compatible = "spansion,sst25wf040";
	108	reg = <3>;
	109	spi-max-frequency = <40000000>; /* input clock */
	110	partition@spi3 {
	111	label = "spi3";
	112	reg = <0x00000000 0x00080000>;
	113	};
	114	};
	115	};
	116
	117	i2c@118000 {
	118	eeprom@51 {
119	compatible = "at24,24c256";
120	reg = <0x51>;
121	};
122	eeprom@53 {
123	compatible = "at24,24c256";
124	reg = <0x53>;
125	};
126	rtc@68 {
127	compatible = "dallas,ds3232";
128	reg = <0x68>;
129	interrupts = <0x1 0x1 0 0>;
130	};
131	};
132
133	usb0: usb@210000 {
134	phy_type = "ulpi";
135	};
136
137	usb1: usb@211000 {
138	dr_mode = "host";
139	phy_type = "ulpi";
140	};
141	};
142
8389c823	143	rio: rapidio@ffe0c0000 {
96cc017c SL	144	reg = <0xf 0xfe0c0000 0 0x11000>;
	145
	146	port1 {
	147	ranges = <0 0 0xc 0x20000000 0 0x10000000>;
	148	};
	149	port2 {
	150	ranges = <0 0 0xc 0x30000000 0 0x10000000>;
	151	};
	152	};
	153
8389c823	154	lbc: localbus@ffe124000 {
96cc017c SL	155	reg = <0xf 0xfe124000 0 0x1000>;
	156	ranges = <0 0 0xf 0xe8000000 0x08000000
	157	2 0 0xf 0xffa00000 0x00040000
	158	3 0 0xf 0xffdf0000 0x00008000>;
	159
	160	flash@0,0 {
	161	compatible = "cfi-flash";
	162	reg = <0 0 0x08000000>;
	163	bank-width = <2>;
	164	device-width = <2>;
	165	};
	166
	167	nand@2,0 {
	168	#address-cells = <1>;
	169	#size-cells = <1>;
	170	compatible = "fsl,elbc-fcm-nand";
	171	reg = <0x2 0x0 0x40000>;
	172
	173	partition@0 {
	174	label = "NAND U-Boot Image";
	175	reg = <0x0 0x02000000>;
	176	read-only;
	177	};
	178
	179	partition@2000000 {
	180	label = "NAND Root File System";
	181	reg = <0x02000000 0x10000000>;
	182	};
	183
	184	partition@12000000 {
	185	label = "NAND Compressed RFS Image";
	186	reg = <0x12000000 0x08000000>;
	187	};
	188
	189	partition@1a000000 {
	190	label = "NAND Linux Kernel Image";
	191	reg = <0x1a000000 0x04000000>;
	192	};
	193
	194	partition@1e000000 {
	195	label = "NAND DTB Image";
	196	reg = <0x1e000000 0x01000000>;
	197	};
	198
	199	partition@1f000000 {
	200	label = "NAND Writable User area";
	201	reg = <0x1f000000 0x21000000>;
	202	};
	203	};
	204
	205	board-control@3,0 {
	206	compatible = "fsl,p3060qds-fpga", "fsl,fpga-qixis";
	207	reg = <3 0 0x100>;
	208	};
	209	};
	210
	211	pci0: pcie@ffe200000 {
	212	reg = <0xf 0xfe200000 0 0x1000>;
	213	ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
	214	0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
	215	pcie@0 {
	216	ranges = <0x02000000 0 0xe0000000
	217	0x02000000 0 0xe0000000
	218	0 0x20000000
219
220	0x01000000 0 0x00000000
221	0x01000000 0 0x00000000
222	0 0x00010000>;
223	};
224	};
225
226	pci1: pcie@ffe201000 {
227	reg = <0xf 0xfe201000 0 0x1000>;
228	ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
229	0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
230	pcie@0 {
231	ranges = <0x02000000 0 0xe0000000
232	0x02000000 0 0xe0000000
233	0 0x20000000
234
235	0x01000000 0 0x00000000
236	0x01000000 0 0x00000000
237	0 0x00010000>;
238	};
239	};
240	};
8389c823 KG	241
8389c823 KG	242	/include/ "fsl/p3060si-post.dtsi"