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106757b3 | 1 | /* |
2 | * phyCORE-MPC5200B-tiny (pcm030) board Device Tree Source | |
3 | * | |
4 | * Copyright 2006 Pengutronix | |
5 | * Sascha Hauer <s.hauer@pengutronix.de> | |
6 | * Copyright 2007 Pengutronix | |
7 | * Juergen Beisert <j.beisert@pengutronix.de> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License as published by the | |
11 | * Free Software Foundation; either version 2 of the License, or (at your | |
12 | * option) any later version. | |
13 | */ | |
14 | ||
15 | /dts-v1/; | |
16 | ||
17 | / { | |
18 | model = "phytec,pcm030"; | |
19 | compatible = "phytec,pcm030"; | |
20 | #address-cells = <1>; | |
21 | #size-cells = <1>; | |
b8842451 | 22 | interrupt-parent = <&mpc5200_pic>; |
106757b3 | 23 | |
24 | cpus { | |
25 | #address-cells = <1>; | |
26 | #size-cells = <0>; | |
27 | ||
28 | PowerPC,5200@0 { | |
29 | device_type = "cpu"; | |
30 | reg = <0>; | |
31 | d-cache-line-size = <32>; | |
32 | i-cache-line-size = <32>; | |
b8842451 GL |
33 | d-cache-size = <0x4000>; // L1, 16K |
34 | i-cache-size = <0x4000>; // L1, 16K | |
35 | timebase-frequency = <0>; // from bootloader | |
36 | bus-frequency = <0>; // from bootloader | |
37 | clock-frequency = <0>; // from bootloader | |
106757b3 | 38 | }; |
39 | }; | |
40 | ||
41 | memory { | |
42 | device_type = "memory"; | |
b8842451 | 43 | reg = <0x00000000 0x04000000>; // 64MB |
106757b3 | 44 | }; |
45 | ||
46 | soc5200@f0000000 { | |
47 | #address-cells = <1>; | |
48 | #size-cells = <1>; | |
49 | compatible = "fsl,mpc5200b-immr"; | |
b8842451 GL |
50 | ranges = <0 0xf0000000 0x0000c000>; |
51 | bus-frequency = <0>; // from bootloader | |
52 | system-frequency = <0>; // from bootloader | |
106757b3 | 53 | |
54 | cdm@200 { | |
55 | compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm"; | |
56 | reg = <0x200 0x38>; | |
57 | }; | |
58 | ||
59 | mpc5200_pic: interrupt-controller@500 { | |
b8842451 | 60 | // 5200 interrupts are encoded into two levels; |
106757b3 | 61 | interrupt-controller; |
62 | #interrupt-cells = <3>; | |
106757b3 | 63 | compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; |
64 | reg = <0x500 0x80>; | |
65 | }; | |
66 | ||
b8842451 | 67 | timer@600 { // General Purpose Timer |
106757b3 | 68 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
106757b3 | 69 | reg = <0x600 0x10>; |
b8842451 | 70 | interrupts = <1 9 0>; |
106757b3 | 71 | fsl,has-wdt; |
72 | }; | |
73 | ||
b8842451 | 74 | timer@610 { // General Purpose Timer |
106757b3 | 75 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
106757b3 | 76 | reg = <0x610 0x10>; |
b8842451 | 77 | interrupts = <1 10 0>; |
106757b3 | 78 | }; |
79 | ||
b8842451 | 80 | gpt2: timer@620 { // General Purpose Timer in GPIO mode |
106757b3 | 81 | compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; |
106757b3 | 82 | reg = <0x620 0x10>; |
b8842451 | 83 | interrupts = <1 11 0>; |
106757b3 | 84 | gpio-controller; |
85 | #gpio-cells = <2>; | |
86 | }; | |
87 | ||
b8842451 | 88 | gpt3: timer@630 { // General Purpose Timer in GPIO mode |
106757b3 | 89 | compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; |
106757b3 | 90 | reg = <0x630 0x10>; |
b8842451 | 91 | interrupts = <1 12 0>; |
106757b3 | 92 | gpio-controller; |
93 | #gpio-cells = <2>; | |
94 | }; | |
95 | ||
b8842451 | 96 | gpt4: timer@640 { // General Purpose Timer in GPIO mode |
106757b3 | 97 | compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; |
106757b3 | 98 | reg = <0x640 0x10>; |
b8842451 | 99 | interrupts = <1 13 0>; |
106757b3 | 100 | gpio-controller; |
101 | #gpio-cells = <2>; | |
102 | }; | |
103 | ||
b8842451 | 104 | gpt5: timer@650 { // General Purpose Timer in GPIO mode |
106757b3 | 105 | compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; |
106757b3 | 106 | reg = <0x650 0x10>; |
b8842451 | 107 | interrupts = <1 14 0>; |
106757b3 | 108 | gpio-controller; |
109 | #gpio-cells = <2>; | |
110 | }; | |
111 | ||
b8842451 | 112 | gpt6: timer@660 { // General Purpose Timer in GPIO mode |
106757b3 | 113 | compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; |
106757b3 | 114 | reg = <0x660 0x10>; |
b8842451 | 115 | interrupts = <1 15 0>; |
106757b3 | 116 | gpio-controller; |
117 | #gpio-cells = <2>; | |
118 | }; | |
119 | ||
b8842451 | 120 | gpt7: timer@670 { // General Purpose Timer in GPIO mode |
106757b3 | 121 | compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; |
106757b3 | 122 | reg = <0x670 0x10>; |
b8842451 | 123 | interrupts = <1 16 0>; |
106757b3 | 124 | gpio-controller; |
125 | #gpio-cells = <2>; | |
126 | }; | |
127 | ||
128 | rtc@800 { // Real time clock | |
129 | compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; | |
106757b3 | 130 | reg = <0x800 0x100>; |
b8842451 | 131 | interrupts = <1 5 0 1 6 0>; |
106757b3 | 132 | }; |
133 | ||
134 | can@900 { | |
135 | compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; | |
b8842451 | 136 | interrupts = <2 17 0>; |
106757b3 | 137 | reg = <0x900 0x80>; |
138 | }; | |
139 | ||
140 | can@980 { | |
141 | compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; | |
b8842451 | 142 | interrupts = <2 18 0>; |
106757b3 | 143 | reg = <0x980 0x80>; |
144 | }; | |
145 | ||
146 | gpio_simple: gpio@b00 { | |
147 | compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; | |
148 | reg = <0xb00 0x40>; | |
b8842451 | 149 | interrupts = <1 7 0>; |
106757b3 | 150 | gpio-controller; |
151 | #gpio-cells = <2>; | |
152 | }; | |
153 | ||
b8842451 | 154 | gpio_wkup: gpio@c00 { |
106757b3 | 155 | compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; |
156 | reg = <0xc00 0x40>; | |
b8842451 | 157 | interrupts = <1 8 0 0 3 0>; |
106757b3 | 158 | gpio-controller; |
159 | #gpio-cells = <2>; | |
160 | }; | |
161 | ||
162 | spi@f00 { | |
163 | compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; | |
164 | reg = <0xf00 0x20>; | |
b8842451 | 165 | interrupts = <2 13 0 2 14 0>; |
106757b3 | 166 | }; |
167 | ||
168 | usb@1000 { | |
169 | compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; | |
170 | reg = <0x1000 0xff>; | |
b8842451 | 171 | interrupts = <2 6 0>; |
106757b3 | 172 | }; |
173 | ||
174 | dma-controller@1200 { | |
106757b3 | 175 | compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; |
176 | reg = <0x1200 0x80>; | |
b8842451 GL |
177 | interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 |
178 | 3 4 0 3 5 0 3 6 0 3 7 0 | |
179 | 3 8 0 3 9 0 3 10 0 3 11 0 | |
180 | 3 12 0 3 13 0 3 14 0 3 15 0>; | |
106757b3 | 181 | }; |
182 | ||
183 | xlb@1f00 { | |
184 | compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; | |
185 | reg = <0x1f00 0x100>; | |
186 | }; | |
187 | ||
188 | ac97@2000 { /* PSC1 in ac97 mode */ | |
106757b3 | 189 | compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97"; |
190 | cell-index = <0>; | |
191 | reg = <0x2000 0x100>; | |
b8842451 | 192 | interrupts = <2 1 0>; |
106757b3 | 193 | }; |
194 | ||
195 | /* PSC2 port is used by CAN1/2 */ | |
196 | ||
197 | serial@2400 { /* PSC3 in UART mode */ | |
106757b3 | 198 | compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; |
106757b3 | 199 | cell-index = <2>; |
200 | reg = <0x2400 0x100>; | |
b8842451 | 201 | interrupts = <2 3 0>; |
106757b3 | 202 | }; |
203 | ||
204 | /* PSC4 is ??? */ | |
205 | ||
206 | /* PSC5 is ??? */ | |
207 | ||
208 | serial@2c00 { /* PSC6 in UART mode */ | |
106757b3 | 209 | compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; |
106757b3 | 210 | cell-index = <5>; |
211 | reg = <0x2c00 0x100>; | |
b8842451 | 212 | interrupts = <2 4 0>; |
106757b3 | 213 | }; |
214 | ||
215 | ethernet@3000 { | |
106757b3 | 216 | compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; |
217 | reg = <0x3000 0x400>; | |
b8842451 GL |
218 | local-mac-address = [ 00 00 00 00 00 00 ]; |
219 | interrupts = <2 5 0>; | |
106757b3 | 220 | phy-handle = <&phy0>; |
221 | }; | |
222 | ||
223 | mdio@3000 { | |
224 | #address-cells = <1>; | |
225 | #size-cells = <0>; | |
b8842451 GL |
226 | compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio"; |
227 | reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts | |
228 | interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. | |
229 | ||
230 | phy0: ethernet-phy@0 { | |
231 | reg = <0>; | |
106757b3 | 232 | }; |
233 | }; | |
234 | ||
235 | ata@3a00 { | |
106757b3 | 236 | compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; |
237 | reg = <0x3a00 0x100>; | |
b8842451 | 238 | interrupts = <2 7 0>; |
106757b3 | 239 | }; |
240 | ||
241 | i2c@3d00 { | |
242 | #address-cells = <1>; | |
243 | #size-cells = <0>; | |
244 | compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; | |
106757b3 | 245 | reg = <0x3d00 0x40>; |
b8842451 | 246 | interrupts = <2 15 0>; |
106757b3 | 247 | fsl5200-clocking; |
248 | }; | |
249 | ||
250 | i2c@3d40 { | |
251 | #address-cells = <1>; | |
252 | #size-cells = <0>; | |
253 | compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; | |
106757b3 | 254 | reg = <0x3d40 0x40>; |
b8842451 | 255 | interrupts = <2 16 0>; |
106757b3 | 256 | fsl5200-clocking; |
257 | rtc@51 { | |
106757b3 | 258 | compatible = "nxp,pcf8563"; |
259 | reg = <0x51>; | |
260 | }; | |
261 | /* FIXME: EEPROM */ | |
262 | }; | |
263 | ||
264 | sram@8000 { | |
b8842451 | 265 | compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram"; |
106757b3 | 266 | reg = <0x8000 0x4000>; |
267 | }; | |
268 | ||
269 | /* This is only an example device to show the usage of gpios. It maps all available | |
270 | * gpios to the "gpio-provider" device. | |
271 | */ | |
272 | gpio { | |
273 | compatible = "gpio-provider"; | |
274 | ||
275 | /* mpc52xx exp.con patchfield */ | |
276 | gpios = <&gpio_wkup 0 0 /* GPIO_WKUP_7 11d jp13-3 */ | |
277 | &gpio_wkup 1 0 /* GPIO_WKUP_6 14c */ | |
278 | &gpio_wkup 6 0 /* PSC2_4 43c x5-11 */ | |
279 | &gpio_simple 2 0 /* IRDA_1 24c x7-6 set GPS_PORT_CONFIG[IRDA] = 0 */ | |
280 | &gpio_simple 3 0 /* IRDA_0 x8-5 set GPS_PORT_CONFIG[IRDA] = 0 */ | |
281 | &gpt2 0 0 /* timer2 12d x4-4 */ | |
282 | &gpt3 0 0 /* timer3 13d x6-4 */ | |
283 | &gpt4 0 0 /* timer4 61c x2-16 */ | |
284 | &gpt5 0 0 /* timer5 44c x7-11 */ | |
285 | &gpt6 0 0 /* timer6 60c x8-15 */ | |
286 | &gpt7 0 0 /* timer7 36a x17-9 */ | |
287 | >; | |
288 | }; | |
289 | }; | |
290 | ||
291 | pci@f0000d00 { | |
292 | #interrupt-cells = <1>; | |
293 | #size-cells = <2>; | |
294 | #address-cells = <3>; | |
295 | device_type = "pci"; | |
296 | compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci"; | |
297 | reg = <0xf0000d00 0x100>; | |
b8842451 GL |
298 | interrupt-map-mask = <0xf800 0 0 7>; |
299 | interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot | |
300 | 0xc000 0 0 2 &mpc5200_pic 1 1 3 | |
301 | 0xc000 0 0 3 &mpc5200_pic 1 2 3 | |
302 | 0xc000 0 0 4 &mpc5200_pic 1 3 3 | |
303 | ||
304 | 0xc800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot | |
305 | 0xc800 0 0 2 &mpc5200_pic 1 2 3 | |
306 | 0xc800 0 0 3 &mpc5200_pic 1 3 3 | |
307 | 0xc800 0 0 4 &mpc5200_pic 0 0 3>; | |
106757b3 | 308 | clock-frequency = <0>; // From boot loader |
b8842451 | 309 | interrupts = <2 8 0 2 9 0 2 10 0>; |
106757b3 | 310 | bus-range = <0 0>; |
b8842451 GL |
311 | ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 |
312 | 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 | |
313 | 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>; | |
106757b3 | 314 | }; |
315 | }; |