[deliverable/linux.git] / arch / powerpc / boot / dts / prpmc2800.dts

/* Device Tree Source for Motorola PrPMC2800
 *
 * Author: Mark A. Greer <mgreer@mvista.com>
 *
 * 2007 (c) MontaVista, Software, Inc.  This file is licensed under
 * the terms of the GNU General Public License version 2.  This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 *
 * Property values that are labeled as "Default" will be updated by bootwrapper
 * if it can determine the exact PrPMC type.
 */

/dts-v1/;

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	model = "PrPMC280/PrPMC2800"; /* Default */
	compatible = "motorola,PrPMC2800";
	coherency-off;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,7447 {
			device_type = "cpu";
			reg = <0>;
			clock-frequency = <733333333>;	/* Default */
			bus-frequency = <133333333>;
			timebase-frequency = <33333333>;
			i-cache-line-size = <32>;
			d-cache-line-size = <32>;
			i-cache-size = <32768>;
			d-cache-size = <32768>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x20000000>;			/* Default (512MB) */
	};

	system-controller@f1000000 { /* Marvell Discovery mv64360 */
		#address-cells = <1>;
		#size-cells = <1>;
		model = "mv64360";			/* Default */
		compatible = "marvell,mv64360";
		clock-frequency = <133333333>;
		reg = <0xf1000000 0x10000>;
		virtual-reg = <0xf1000000>;
		ranges = <0x88000000 0x88000000 0x1000000 /* PCI 0 I/O Space */
			  0x80000000 0x80000000 0x8000000 /* PCI 0 MEM Space */
			  0xa0000000 0xa0000000 0x4000000 /* User FLASH */
			  0x00000000 0xf1000000 0x0010000 /* Bridge's regs */
			  0xf2000000 0xf2000000 0x0040000>;/* Integrated SRAM */

		flash@a0000000 {
			device_type = "rom";
			compatible = "direct-mapped";
			reg = <0xa0000000 0x4000000>; /* Default (64MB) */
			probe-type = "CFI";
			bank-width = <4>;
			partitions = <0x00000000 0x00100000 /* RO */
				      0x00100000 0x00040001 /* RW */
				      0x00140000 0x00400000 /* RO */
				      0x00540000 0x039c0000 /* RO */
				      0x03f00000 0x00100000>; /* RO */
			partition-names = "FW Image A", "FW Config Data", "Kernel Image", "Filesystem", "FW Image B";
		};

		mdio {
			#address-cells = <1>;
			#size-cells = <0>;
			device_type = "mdio";
			compatible = "marvell,mv64360-mdio";
			PHY0: ethernet-phy@1 {
				compatible = "broadcom,bcm5421";
				interrupts = <76>;	/* GPP 12 */
				interrupt-parent = <&PIC>;
				reg = <1>;
			};
			PHY1: ethernet-phy@3 {
				compatible = "broadcom,bcm5421";
				interrupts = <76>;	/* GPP 12 */
				interrupt-parent = <&PIC>;
				reg = <3>;
			};
		};

		ethernet-group@2000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "marvell,mv64360-eth-group";
			reg = <0x2000 0x2000>;
			ethernet@0 {
				device_type = "network";
				compatible = "marvell,mv64360-eth";
				reg = <0>;
				interrupts = <32>;
				interrupt-parent = <&PIC>;
				phy = <&PHY0>;
				local-mac-address = [ 00 00 00 00 00 00 ];
			};
			ethernet@1 {
				device_type = "network";
				compatible = "marvell,mv64360-eth";
				reg = <1>;
				interrupts = <33>;
				interrupt-parent = <&PIC>;
				phy = <&PHY1>;
				local-mac-address = [ 00 00 00 00 00 00 ];
			};
		};

		SDMA0: sdma@4000 {
			compatible = "marvell,mv64360-sdma";
			reg = <0x4000 0xc18>;
			virtual-reg = <0xf1004000>;
			interrupts = <36>;
			interrupt-parent = <&PIC>;
		};

		SDMA1: sdma@6000 {
			compatible = "marvell,mv64360-sdma";
			reg = <0x6000 0xc18>;
			virtual-reg = <0xf1006000>;
			interrupts = <38>;
			interrupt-parent = <&PIC>;
		};

		BRG0: brg@b200 {
			compatible = "marvell,mv64360-brg";
			reg = <0xb200 0x8>;
			clock-src = <8>;
			clock-frequency = <133333333>;
			current-speed = <9600>;
		};

		BRG1: brg@b208 {
			compatible = "marvell,mv64360-brg";
			reg = <0xb208 0x8>;
			clock-src = <8>;
			clock-frequency = <133333333>;
			current-speed = <9600>;
		};

		CUNIT: cunit@f200 {
			reg = <0xf200 0x200>;
		};

		MPSCROUTING: mpscrouting@b400 {
			reg = <0xb400 0xc>;
		};

		MPSCINTR: mpscintr@b800 {
			reg = <0xb800 0x100>;
			virtual-reg = <0xf100b800>;
		};

		MPSC0: mpsc@8000 {
			device_type = "serial";
			compatible = "marvell,mv64360-mpsc";
			reg = <0x8000 0x38>;
			virtual-reg = <0xf1008000>;
			sdma = <&SDMA0>;
			brg = <&BRG0>;
			cunit = <&CUNIT>;
			mpscrouting = <&MPSCROUTING>;
			mpscintr = <&MPSCINTR>;
			cell-index = <0>;
			interrupts = <40>;
			interrupt-parent = <&PIC>;
		};

		MPSC1: mpsc@9000 {
			device_type = "serial";
			compatible = "marvell,mv64360-mpsc";
			reg = <0x9000 0x38>;
			virtual-reg = <0xf1009000>;
			sdma = <&SDMA1>;
			brg = <&BRG1>;
			cunit = <&CUNIT>;
			mpscrouting = <&MPSCROUTING>;
			mpscintr = <&MPSCINTR>;
			cell-index = <1>;
			interrupts = <42>;
			interrupt-parent = <&PIC>;
		};

		wdt@b410 {			/* watchdog timer */
			compatible = "marvell,mv64360-wdt";
			reg = <0xb410 0x8>;
		};

		i2c@c000 {
			device_type = "i2c";
			compatible = "marvell,mv64360-i2c";
			reg = <0xc000 0x20>;
			virtual-reg = <0xf100c000>;
			interrupts = <37>;
			interrupt-parent = <&PIC>;
		};

		PIC: pic {
			#interrupt-cells = <1>;
			#address-cells = <0>;
			compatible = "marvell,mv64360-pic";
			reg = <0x0 0x88>;
			interrupt-controller;
		};

		mpp@f000 {
			compatible = "marvell,mv64360-mpp";
			reg = <0xf000 0x10>;
		};

		gpp@f100 {
			compatible = "marvell,mv64360-gpp";
			reg = <0xf100 0x20>;
		};

		pci@80000000 {
			#address-cells = <3>;
			#size-cells = <2>;
			#interrupt-cells = <1>;
			device_type = "pci";
			compatible = "marvell,mv64360-pci";
			reg = <0xcf8 0x8>;
			ranges = <0x01000000 0x0        0x0
					0x88000000 0x0 0x01000000
				  0x02000000 0x0 0x80000000
				  	0x80000000 0x0 0x08000000>;
			bus-range = <0 255>;
			clock-frequency = <66000000>;
			interrupt-pci-iack = <0xc34>;
			interrupt-parent = <&PIC>;
			interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
			interrupt-map = <
				/* IDSEL 0x0a */
				0x5000 0 0 1 &PIC 80
				0x5000 0 0 2 &PIC 81
				0x5000 0 0 3 &PIC 91
				0x5000 0 0 4 &PIC 93

				/* IDSEL 0x0b */
				0x5800 0 0 1 &PIC 91
				0x5800 0 0 2 &PIC 93
				0x5800 0 0 3 &PIC 80
				0x5800 0 0 4 &PIC 81

				/* IDSEL 0x0c */
				0x6000 0 0 1 &PIC 91
				0x6000 0 0 2 &PIC 93
				0x6000 0 0 3 &PIC 80
				0x6000 0 0 4 &PIC 81

				/* IDSEL 0x0d */
				0x6800 0 0 1 &PIC 93
				0x6800 0 0 2 &PIC 80
				0x6800 0 0 3 &PIC 81
				0x6800 0 0 4 &PIC 91
			>;
		};

		cpu-error@0070 {
			compatible = "marvell,mv64360-cpu-error";
			reg = <0x70 0x10 0x128 0x28>;
			interrupts = <3>;
			interrupt-parent = <&PIC>;
		};

		sram-ctrl@0380 {
			compatible = "marvell,mv64360-sram-ctrl";
			reg = <0x380 0x80>;
			interrupts = <13>;
			interrupt-parent = <&PIC>;
		};

		pci-error@1d40 {
			compatible = "marvell,mv64360-pci-error";
			reg = <0x1d40 0x40 0xc28 0x4>;
			interrupts = <12>;
			interrupt-parent = <&PIC>;
		};

		mem-ctrl@1400 {
			compatible = "marvell,mv64360-mem-ctrl";
			reg = <0x1400 0x60>;
			interrupts = <17>;
			interrupt-parent = <&PIC>;
		};
	};

	chosen {
		bootargs = "ip=on";
		linux,stdout-path = &MPSC0;
	};
};
Commit	Line	Data
3f456cc1 MG	1	/* Device Tree Source for Motorola PrPMC2800
	2	*
	3	* Author: Mark A. Greer <mgreer@mvista.com>
	4	*
	5	* 2007 (c) MontaVista, Software, Inc. This file is licensed under
	6	* the terms of the GNU General Public License version 2. This program
	7	* is licensed "as is" without any warranty of any kind, whether express
	8	* or implied.
	9	*
	10	* Property values that are labeled as "Default" will be updated by bootwrapper
	11	* if it can determine the exact PrPMC type.
3f456cc1 MG	12	*/
3f456cc1 MG	13
d528be50 MG	14	/dts-v1/;
d528be50 MG	15
3f456cc1 MG	16	/ {
	17	#address-cells = <1>;
	18	#size-cells = <1>;
	19	model = "PrPMC280/PrPMC2800"; /* Default */
	20	compatible = "motorola,PrPMC2800";
	21	coherency-off;
	22
	23	cpus {
	24	#address-cells = <1>;
	25	#size-cells = <0>;
	26
	27	PowerPC,7447 {
	28	device_type = "cpu";
	29	reg = <0>;
fb9d93de	30	clock-frequency = <733333333>; /* Default */
d528be50 MG	31	bus-frequency = <133333333>;
	32	timebase-frequency = <33333333>;
	33	i-cache-line-size = <32>;
	34	d-cache-line-size = <32>;
	35	i-cache-size = <32768>;
	36	d-cache-size = <32768>;
3f456cc1 MG	37	};
	38	};
	39
	40	memory {
	41	device_type = "memory";
d528be50	42	reg = <0x0 0x20000000>; /* Default (512MB) */
3f456cc1 MG	43	};
3f456cc1 MG	44
1791f91b	45	system-controller@f1000000 { /* Marvell Discovery mv64360 */
3f456cc1 MG	46	#address-cells = <1>;
3f456cc1 MG	47	#size-cells = <1>;
3f456cc1	48	model = "mv64360"; /* Default */
a1810b44	49	compatible = "marvell,mv64360";
d528be50 MG	50	clock-frequency = <133333333>;
	51	reg = <0xf1000000 0x10000>;
	52	virtual-reg = <0xf1000000>;
	53	ranges = <0x88000000 0x88000000 0x1000000 /* PCI 0 I/O Space */
	54	0x80000000 0x80000000 0x8000000 /* PCI 0 MEM Space */
	55	0xa0000000 0xa0000000 0x4000000 /* User FLASH */
	56	0x00000000 0xf1000000 0x0010000 /* Bridge's regs */
	57	0xf2000000 0xf2000000 0x0040000>;/* Integrated SRAM */
3f456cc1 MG	58
	59	flash@a0000000 {
	60	device_type = "rom";
	61	compatible = "direct-mapped";
d528be50	62	reg = <0xa0000000 0x4000000>; /* Default (64MB) */
3f456cc1 MG	63	probe-type = "CFI";
3f456cc1 MG	64	bank-width = <4>;
d528be50 MG	65	partitions = <0x00000000 0x00100000 /* RO */
	66	0x00100000 0x00040001 /* RW */
	67	0x00140000 0x00400000 /* RO */
	68	0x00540000 0x039c0000 /* RO */
	69	0x03f00000 0x00100000>; /* RO */
3f456cc1 MG	70	partition-names = "FW Image A", "FW Config Data", "Kernel Image", "Filesystem", "FW Image B";
	71	};
	72
	73	mdio {
	74	#address-cells = <1>;
	75	#size-cells = <0>;
	76	device_type = "mdio";
a1810b44	77	compatible = "marvell,mv64360-mdio";
d528be50	78	PHY0: ethernet-phy@1 {
3f456cc1	79	compatible = "broadcom,bcm5421";
d528be50 MG	80	interrupts = <76>; /* GPP 12 */
d528be50 MG	81	interrupt-parent = <&PIC>;
3f456cc1 MG	82	reg = <1>;
3f456cc1 MG	83	};
d528be50	84	PHY1: ethernet-phy@3 {
3f456cc1	85	compatible = "broadcom,bcm5421";
d528be50 MG	86	interrupts = <76>; /* GPP 12 */
d528be50 MG	87	interrupt-parent = <&PIC>;
3f456cc1 MG	88	reg = <3>;
	89	};
	90	};
	91
a0916bd6 DF	92	ethernet-group@2000 {
	93	#address-cells = <1>;
	94	#size-cells = <0>;
	95	compatible = "marvell,mv64360-eth-group";
d528be50	96	reg = <0x2000 0x2000>;
a0916bd6	97	ethernet@0 {
3f456cc1	98	device_type = "network";
a1810b44	99	compatible = "marvell,mv64360-eth";
a0916bd6	100	reg = <0>;
d528be50 MG	101	interrupts = <32>;
	102	interrupt-parent = <&PIC>;
	103	phy = <&PHY0>;
3f456cc1 MG	104	local-mac-address = [ 00 00 00 00 00 00 ];
3f456cc1 MG	105	};
a0916bd6	106	ethernet@1 {
3f456cc1	107	device_type = "network";
a1810b44	108	compatible = "marvell,mv64360-eth";
a0916bd6	109	reg = <1>;
d528be50 MG	110	interrupts = <33>;
	111	interrupt-parent = <&PIC>;
	112	phy = <&PHY1>;
3f456cc1 MG	113	local-mac-address = [ 00 00 00 00 00 00 ];
	114	};
	115	};
	116
d528be50	117	SDMA0: sdma@4000 {
a1810b44	118	compatible = "marvell,mv64360-sdma";
d528be50 MG	119	reg = <0x4000 0xc18>;
d528be50 MG	120	virtual-reg = <0xf1004000>;
d528be50 MG	121	interrupts = <36>;
d528be50 MG	122	interrupt-parent = <&PIC>;
3f456cc1 MG	123	};
3f456cc1 MG	124
d528be50	125	SDMA1: sdma@6000 {
a1810b44	126	compatible = "marvell,mv64360-sdma";
d528be50 MG	127	reg = <0x6000 0xc18>;
d528be50 MG	128	virtual-reg = <0xf1006000>;
d528be50 MG	129	interrupts = <38>;
d528be50 MG	130	interrupt-parent = <&PIC>;
3f456cc1 MG	131	};
3f456cc1 MG	132
d528be50	133	BRG0: brg@b200 {
a1810b44	134	compatible = "marvell,mv64360-brg";
d528be50	135	reg = <0xb200 0x8>;
3f456cc1	136	clock-src = <8>;
fb9d93de	137	clock-frequency = <133333333>;
d528be50	138	current-speed = <9600>;
3f456cc1 MG	139	};
3f456cc1 MG	140
d528be50	141	BRG1: brg@b208 {
a1810b44	142	compatible = "marvell,mv64360-brg";
d528be50	143	reg = <0xb208 0x8>;
3f456cc1	144	clock-src = <8>;
fb9d93de	145	clock-frequency = <133333333>;
d528be50	146	current-speed = <9600>;
3f456cc1 MG	147	};
3f456cc1 MG	148
d528be50 MG	149	CUNIT: cunit@f200 {
d528be50 MG	150	reg = <0xf200 0x200>;
3f456cc1 MG	151	};
3f456cc1 MG	152
d528be50 MG	153	MPSCROUTING: mpscrouting@b400 {
d528be50 MG	154	reg = <0xb400 0xc>;
3f456cc1 MG	155	};
3f456cc1 MG	156
d528be50 MG	157	MPSCINTR: mpscintr@b800 {
	158	reg = <0xb800 0x100>;
	159	virtual-reg = <0xf100b800>;
3f456cc1 MG	160	};
3f456cc1 MG	161
d528be50	162	MPSC0: mpsc@8000 {
3f456cc1	163	device_type = "serial";
a1810b44	164	compatible = "marvell,mv64360-mpsc";
d528be50 MG	165	reg = <0x8000 0x38>;
	166	virtual-reg = <0xf1008000>;
	167	sdma = <&SDMA0>;
	168	brg = <&BRG0>;
	169	cunit = <&CUNIT>;
	170	mpscrouting = <&MPSCROUTING>;
	171	mpscintr = <&MPSCINTR>;
1791f91b	172	cell-index = <0>;
d528be50 MG	173	interrupts = <40>;
d528be50 MG	174	interrupt-parent = <&PIC>;
3f456cc1 MG	175	};
3f456cc1 MG	176
d528be50	177	MPSC1: mpsc@9000 {
3f456cc1	178	device_type = "serial";
a1810b44	179	compatible = "marvell,mv64360-mpsc";
d528be50 MG	180	reg = <0x9000 0x38>;
	181	virtual-reg = <0xf1009000>;
	182	sdma = <&SDMA1>;
	183	brg = <&BRG1>;
	184	cunit = <&CUNIT>;
	185	mpscrouting = <&MPSCROUTING>;
	186	mpscintr = <&MPSCINTR>;
1791f91b	187	cell-index = <1>;
d528be50 MG	188	interrupts = <42>;
d528be50 MG	189	interrupt-parent = <&PIC>;
3f456cc1 MG	190	};
3f456cc1 MG	191
7e07a159	192	wdt@b410 { /* watchdog timer */
a1810b44	193	compatible = "marvell,mv64360-wdt";
d528be50	194	reg = <0xb410 0x8>;
7e07a159 DF	195	};
7e07a159 DF	196
3f456cc1 MG	197	i2c@c000 {
3f456cc1 MG	198	device_type = "i2c";
a1810b44	199	compatible = "marvell,mv64360-i2c";
d528be50 MG	200	reg = <0xc000 0x20>;
d528be50 MG	201	virtual-reg = <0xf100c000>;
d528be50 MG	202	interrupts = <37>;
d528be50 MG	203	interrupt-parent = <&PIC>;
3f456cc1 MG	204	};
3f456cc1 MG	205
d528be50	206	PIC: pic {
3f456cc1 MG	207	#interrupt-cells = <1>;
3f456cc1 MG	208	#address-cells = <0>;
a1810b44	209	compatible = "marvell,mv64360-pic";
d528be50	210	reg = <0x0 0x88>;
3f456cc1 MG	211	interrupt-controller;
	212	};
	213
	214	mpp@f000 {
a1810b44	215	compatible = "marvell,mv64360-mpp";
d528be50	216	reg = <0xf000 0x10>;
3f456cc1 MG	217	};
	218
	219	gpp@f100 {
a1810b44	220	compatible = "marvell,mv64360-gpp";
d528be50	221	reg = <0xf100 0x20>;
3f456cc1 MG	222	};
	223
	224	pci@80000000 {
	225	#address-cells = <3>;
	226	#size-cells = <2>;
	227	#interrupt-cells = <1>;
	228	device_type = "pci";
a1810b44	229	compatible = "marvell,mv64360-pci";
d528be50 MG	230	reg = <0xcf8 0x8>;
	231	ranges = <0x01000000 0x0 0x0
	232	0x88000000 0x0 0x01000000
	233	0x02000000 0x0 0x80000000
	234	0x80000000 0x0 0x08000000>;
	235	bus-range = <0 255>;
	236	clock-frequency = <66000000>;
	237	interrupt-pci-iack = <0xc34>;
	238	interrupt-parent = <&PIC>;
	239	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
3f456cc1 MG	240	interrupt-map = <
3f456cc1 MG	241	/* IDSEL 0x0a */
d528be50 MG	242	0x5000 0 0 1 &PIC 80
	243	0x5000 0 0 2 &PIC 81
	244	0x5000 0 0 3 &PIC 91
	245	0x5000 0 0 4 &PIC 93
3f456cc1 MG	246
3f456cc1 MG	247	/* IDSEL 0x0b */
d528be50 MG	248	0x5800 0 0 1 &PIC 91
	249	0x5800 0 0 2 &PIC 93
	250	0x5800 0 0 3 &PIC 80
	251	0x5800 0 0 4 &PIC 81
3f456cc1 MG	252
3f456cc1 MG	253	/* IDSEL 0x0c */
d528be50 MG	254	0x6000 0 0 1 &PIC 91
	255	0x6000 0 0 2 &PIC 93
	256	0x6000 0 0 3 &PIC 80
	257	0x6000 0 0 4 &PIC 81
3f456cc1 MG	258
3f456cc1 MG	259	/* IDSEL 0x0d */
d528be50 MG	260	0x6800 0 0 1 &PIC 93
	261	0x6800 0 0 2 &PIC 80
	262	0x6800 0 0 3 &PIC 81
	263	0x6800 0 0 4 &PIC 91
3f456cc1 MG	264	>;
	265	};
	266
	267	cpu-error@0070 {
a1810b44	268	compatible = "marvell,mv64360-cpu-error";
d528be50 MG	269	reg = <0x70 0x10 0x128 0x28>;
	270	interrupts = <3>;
	271	interrupt-parent = <&PIC>;
3f456cc1 MG	272	};
	273
	274	sram-ctrl@0380 {
a1810b44	275	compatible = "marvell,mv64360-sram-ctrl";
d528be50 MG	276	reg = <0x380 0x80>;
	277	interrupts = <13>;
	278	interrupt-parent = <&PIC>;
3f456cc1 MG	279	};
	280
	281	pci-error@1d40 {
a1810b44	282	compatible = "marvell,mv64360-pci-error";
d528be50 MG	283	reg = <0x1d40 0x40 0xc28 0x4>;
	284	interrupts = <12>;
	285	interrupt-parent = <&PIC>;
3f456cc1 MG	286	};
	287
	288	mem-ctrl@1400 {
a1810b44	289	compatible = "marvell,mv64360-mem-ctrl";
d528be50 MG	290	reg = <0x1400 0x60>;
	291	interrupts = <17>;
	292	interrupt-parent = <&PIC>;
3f456cc1 MG	293	};
	294	};
	295
	296	chosen {
bb807e69	297	bootargs = "ip=on";
d528be50	298	linux,stdout-path = &MPSC0;
3f456cc1 MG	299	};
3f456cc1 MG	300	};