projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 30340998 PG |
1 | /* |
| 2 | * SBC8548 Device Tree Source | |
| 3 | * | |
| 4 | * Copyright 2007 Wind River Systems Inc. | |
| 5 | * | |
| 6 | * Paul Gortmaker (see MAINTAINERS for contact information) | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or modify it | |
| 9 | * under the terms of the GNU General Public License as published by the | |
| 10 | * Free Software Foundation; either version 2 of the License, or (at your | |
| 11 | * option) any later version. | |
| 12 | */ | |
| 13 | ||
| 14 | ||
| 15 | /dts-v1/; | |
| 16 | ||
| 17 | / { | |
| 18 | model = "SBC8548"; | |
| 19 | compatible = "SBC8548"; | |
| 20 | #address-cells = <1>; | |
| 21 | #size-cells = <1>; | |
| 22 | ||
| 23 | aliases { | |
| 24 | ethernet0 = &enet0; | |
| 25 | ethernet1 = &enet1; | |
| 26 | serial0 = &serial0; | |
| 27 | serial1 = &serial1; | |
| 28 | pci0 = &pci0; | |
| 29 | /* pci1 doesn't have a corresponding physical connector */ | |
| 30 | pci2 = &pci2; | |
| 31 | }; | |
| 32 | ||
| 33 | cpus { | |
| 34 | #address-cells = <1>; | |
| 35 | #size-cells = <0>; | |
| 36 | ||
| 37 | PowerPC,8548@0 { | |
| 38 | device_type = "cpu"; | |
| 39 | reg = <0>; | |
| 40 | d-cache-line-size = <0x20>; // 32 bytes | |
| 41 | i-cache-line-size = <0x20>; // 32 bytes | |
| 42 | d-cache-size = <0x8000>; // L1, 32K | |
| 43 | i-cache-size = <0x8000>; // L1, 32K | |
| 44 | timebase-frequency = <0>; // From uboot | |
| 45 | bus-frequency = <0>; | |
| 46 | clock-frequency = <0>; | |
| c054065b | 47 | next-level-cache = <&L2>; |
| 30340998 PG |
48 | }; |
| 49 | }; | |
| 50 | ||
| 51 | memory { | |
| 52 | device_type = "memory"; | |
| 53 | reg = <0x00000000 0x10000000>; | |
| 54 | }; | |
| 55 | ||
| bfd123bf JM |
56 | localbus@e0000000 { |
| 57 | #address-cells = <2>; | |
| 58 | #size-cells = <1>; | |
| 59 | compatible = "simple-bus"; | |
| 60 | reg = <0xe0000000 0x5000>; | |
| 61 | interrupt-parent = <&mpic>; | |
| 62 | ||
| 63 | ranges = <0x0 0x0 0xff800000 0x00800000 /*8MB Flash*/ | |
| 64 | 0x3 0x0 0xf0000000 0x04000000 /*64MB SDRAM*/ | |
| 65 | 0x4 0x0 0xf4000000 0x04000000 /*64MB SDRAM*/ | |
| 66 | 0x5 0x0 0xf8000000 0x00b10000 /* EPLD */ | |
| 67 | 0x6 0x0 0xfb800000 0x04000000>; /*64MB Flash*/ | |
| 68 | ||
| 69 | ||
| 70 | flash@0,0 { | |
| 71 | #address-cells = <1>; | |
| 72 | #size-cells = <1>; | |
| 73 | compatible = "cfi-flash"; | |
| 74 | reg = <0x0 0x0 0x800000>; | |
| 75 | bank-width = <1>; | |
| 76 | device-width = <1>; | |
| 77 | partition@0x0 { | |
| 78 | label = "space"; | |
| 79 | reg = <0x00000000 0x00100000>; | |
| 80 | }; | |
| 81 | partition@0x100000 { | |
| 82 | label = "bootloader"; | |
| 83 | reg = <0x00100000 0x00700000>; | |
| 84 | read-only; | |
| 85 | }; | |
| 86 | }; | |
| 87 | ||
| 88 | epld@5,0 { | |
| 89 | compatible = "wrs,epld-localbus"; | |
| 90 | #address-cells = <2>; | |
| 91 | #size-cells = <1>; | |
| 92 | reg = <0x5 0x0 0x00b10000>; | |
| 93 | ranges = < | |
| 94 | 0x0 0x0 0x5 0x000000 0x1fff /* LED */ | |
| 95 | 0x1 0x0 0x5 0x100000 0x1fff /* Switches */ | |
| 96 | 0x3 0x0 0x5 0x300000 0x1fff /* HW Rev. */ | |
| 97 | 0xb 0x0 0x5 0xb00000 0x1fff /* EEPROM */ | |
| 98 | >; | |
| 99 | ||
| 100 | led@0,0 { | |
| 101 | compatible = "led"; | |
| 102 | reg = <0x0 0x0 0x1fff>; | |
| 103 | }; | |
| 104 | ||
| 105 | switches@1,0 { | |
| 106 | compatible = "switches"; | |
| 107 | reg = <0x1 0x0 0x1fff>; | |
| 108 | }; | |
| 109 | ||
| 110 | hw-rev@3,0 { | |
| 111 | compatible = "hw-rev"; | |
| 112 | reg = <0x3 0x0 0x1fff>; | |
| 113 | }; | |
| 114 | ||
| 115 | eeprom@b,0 { | |
| 116 | compatible = "eeprom"; | |
| 117 | reg = <0xb 0 0x1fff>; | |
| 118 | }; | |
| 119 | ||
| 120 | }; | |
| 121 | ||
| 122 | alt-flash@6,0 { | |
| 123 | #address-cells = <1>; | |
| 124 | #size-cells = <1>; | |
| 125 | reg = <0x6 0x0 0x04000000>; | |
| 126 | compatible = "cfi-flash"; | |
| 127 | bank-width = <4>; | |
| 128 | device-width = <1>; | |
| 129 | partition@0x0 { | |
| 130 | label = "bootloader"; | |
| 131 | reg = <0x00000000 0x00100000>; | |
| 132 | read-only; | |
| 133 | }; | |
| 134 | partition@0x00100000 { | |
| 135 | label = "file-system"; | |
| 136 | reg = <0x00100000 0x01f00000>; | |
| 137 | }; | |
| 138 | partition@0x02000000 { | |
| 139 | label = "boot-config"; | |
| 140 | reg = <0x02000000 0x00100000>; | |
| 141 | }; | |
| 142 | partition@0x02100000 { | |
| 143 | label = "space"; | |
| 144 | reg = <0x02100000 0x01f00000>; | |
| 145 | }; | |
| 146 | }; | |
| 147 | }; | |
| 148 | ||
| 30340998 PG |
149 | soc8548@e0000000 { |
| 150 | #address-cells = <1>; | |
| 151 | #size-cells = <1>; | |
| 152 | device_type = "soc"; | |
| 153 | ranges = <0x00000000 0xe0000000 0x00100000>; | |
| 30340998 | 154 | bus-frequency = <0>; |
| bfd123bf | 155 | compatible = "simple-bus"; |
| 30340998 | 156 | |
| e1a22897 KG |
157 | ecm-law@0 { |
| 158 | compatible = "fsl,ecm-law"; | |
| 159 | reg = <0x0 0x1000>; | |
| 160 | fsl,num-laws = <10>; | |
| 161 | }; | |
| 162 | ||
| 163 | ecm@1000 { | |
| 164 | compatible = "fsl,mpc8548-ecm", "fsl,ecm"; | |
| 165 | reg = <0x1000 0x1000>; | |
| 166 | interrupts = <17 2>; | |
| 167 | interrupt-parent = <&mpic>; | |
| 168 | }; | |
| 169 | ||
| 30340998 | 170 | memory-controller@2000 { |
| fe671772 | 171 | compatible = "fsl,mpc8548-memory-controller"; |
| 30340998 PG |
172 | reg = <0x2000 0x1000>; |
| 173 | interrupt-parent = <&mpic>; | |
| 174 | interrupts = <0x12 0x2>; | |
| 175 | }; | |
| 176 | ||
| c054065b | 177 | L2: l2-cache-controller@20000 { |
| fe671772 | 178 | compatible = "fsl,mpc8548-l2-cache-controller"; |
| 30340998 PG |
179 | reg = <0x20000 0x1000>; |
| 180 | cache-line-size = <0x20>; // 32 bytes | |
| 181 | cache-size = <0x80000>; // L2, 512K | |
| 182 | interrupt-parent = <&mpic>; | |
| 183 | interrupts = <0x10 0x2>; | |
| 184 | }; | |
| 185 | ||
| 186 | i2c@3000 { | |
| 187 | #address-cells = <1>; | |
| 188 | #size-cells = <0>; | |
| 189 | cell-index = <0>; | |
| 190 | compatible = "fsl-i2c"; | |
| 191 | reg = <0x3000 0x100>; | |
| 192 | interrupts = <0x2b 0x2>; | |
| 193 | interrupt-parent = <&mpic>; | |
| 194 | dfsrr; | |
| 195 | }; | |
| 196 | ||
| 197 | i2c@3100 { | |
| 198 | #address-cells = <1>; | |
| 199 | #size-cells = <0>; | |
| 200 | cell-index = <1>; | |
| 201 | compatible = "fsl-i2c"; | |
| 202 | reg = <0x3100 0x100>; | |
| 203 | interrupts = <0x2b 0x2>; | |
| 204 | interrupt-parent = <&mpic>; | |
| 205 | dfsrr; | |
| 206 | }; | |
| 207 | ||
| dee80553 KG |
208 | dma@21300 { |
| 209 | #address-cells = <1>; | |
| 210 | #size-cells = <1>; | |
| 211 | compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma"; | |
| 212 | reg = <0x21300 0x4>; | |
| 213 | ranges = <0x0 0x21100 0x200>; | |
| 214 | cell-index = <0>; | |
| 215 | dma-channel@0 { | |
| 216 | compatible = "fsl,mpc8548-dma-channel", | |
| 217 | "fsl,eloplus-dma-channel"; | |
| 218 | reg = <0x0 0x80>; | |
| 219 | cell-index = <0>; | |
| 220 | interrupt-parent = <&mpic>; | |
| 221 | interrupts = <20 2>; | |
| 222 | }; | |
| 223 | dma-channel@80 { | |
| 224 | compatible = "fsl,mpc8548-dma-channel", | |
| 225 | "fsl,eloplus-dma-channel"; | |
| 226 | reg = <0x80 0x80>; | |
| 227 | cell-index = <1>; | |
| 228 | interrupt-parent = <&mpic>; | |
| 229 | interrupts = <21 2>; | |
| 230 | }; | |
| 231 | dma-channel@100 { | |
| 232 | compatible = "fsl,mpc8548-dma-channel", | |
| 233 | "fsl,eloplus-dma-channel"; | |
| 234 | reg = <0x100 0x80>; | |
| 235 | cell-index = <2>; | |
| 236 | interrupt-parent = <&mpic>; | |
| 237 | interrupts = <22 2>; | |
| 238 | }; | |
| 239 | dma-channel@180 { | |
| 240 | compatible = "fsl,mpc8548-dma-channel", | |
| 241 | "fsl,eloplus-dma-channel"; | |
| 242 | reg = <0x180 0x80>; | |
| 243 | cell-index = <3>; | |
| 244 | interrupt-parent = <&mpic>; | |
| 245 | interrupts = <23 2>; | |
| 246 | }; | |
| 247 | }; | |
| 248 | ||
| 30340998 | 249 | enet0: ethernet@24000 { |
| 84ba4a58 AV |
250 | #address-cells = <1>; |
| 251 | #size-cells = <1>; | |
| 30340998 PG |
252 | cell-index = <0>; |
| 253 | device_type = "network"; | |
| 254 | model = "eTSEC"; | |
| 255 | compatible = "gianfar"; | |
| 256 | reg = <0x24000 0x1000>; | |
| 84ba4a58 | 257 | ranges = <0x0 0x24000 0x1000>; |
| 30340998 PG |
258 | local-mac-address = [ 00 00 00 00 00 00 ]; |
| 259 | interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>; | |
| 260 | interrupt-parent = <&mpic>; | |
| b31a1d8b | 261 | tbi-handle = <&tbi0>; |
| 30340998 | 262 | phy-handle = <&phy0>; |
| 84ba4a58 AV |
263 | |
| 264 | mdio@520 { | |
| 265 | #address-cells = <1>; | |
| 266 | #size-cells = <0>; | |
| 267 | compatible = "fsl,gianfar-mdio"; | |
| 268 | reg = <0x520 0x20>; | |
| 269 | ||
| 270 | phy0: ethernet-phy@19 { | |
| 271 | interrupt-parent = <&mpic>; | |
| 272 | interrupts = <0x6 0x1>; | |
| 273 | reg = <0x19>; | |
| 274 | device_type = "ethernet-phy"; | |
| 275 | }; | |
| 276 | phy1: ethernet-phy@1a { | |
| 277 | interrupt-parent = <&mpic>; | |
| 278 | interrupts = <0x7 0x1>; | |
| 279 | reg = <0x1a>; | |
| 280 | device_type = "ethernet-phy"; | |
| 281 | }; | |
| 282 | tbi0: tbi-phy@11 { | |
| 283 | reg = <0x11>; | |
| 284 | device_type = "tbi-phy"; | |
| 285 | }; | |
| 286 | }; | |
| 30340998 PG |
287 | }; |
| 288 | ||
| 289 | enet1: ethernet@25000 { | |
| 84ba4a58 AV |
290 | #address-cells = <1>; |
| 291 | #size-cells = <1>; | |
| 30340998 PG |
292 | cell-index = <1>; |
| 293 | device_type = "network"; | |
| 294 | model = "eTSEC"; | |
| 295 | compatible = "gianfar"; | |
| 296 | reg = <0x25000 0x1000>; | |
| 84ba4a58 | 297 | ranges = <0x0 0x25000 0x1000>; |
| 30340998 PG |
298 | local-mac-address = [ 00 00 00 00 00 00 ]; |
| 299 | interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>; | |
| 300 | interrupt-parent = <&mpic>; | |
| b31a1d8b | 301 | tbi-handle = <&tbi1>; |
| 30340998 | 302 | phy-handle = <&phy1>; |
| 84ba4a58 AV |
303 | |
| 304 | mdio@520 { | |
| 305 | #address-cells = <1>; | |
| 306 | #size-cells = <0>; | |
| 307 | compatible = "fsl,gianfar-tbi"; | |
| 308 | reg = <0x520 0x20>; | |
| 309 | ||
| 310 | tbi1: tbi-phy@11 { | |
| 311 | reg = <0x11>; | |
| 312 | device_type = "tbi-phy"; | |
| 313 | }; | |
| 314 | }; | |
| 30340998 PG |
315 | }; |
| 316 | ||
| 317 | serial0: serial@4500 { | |
| 318 | cell-index = <0>; | |
| 319 | device_type = "serial"; | |
| 320 | compatible = "ns16550"; | |
| 321 | reg = <0x4500 0x100>; // reg base, size | |
| 322 | clock-frequency = <0>; // should we fill in in uboot? | |
| 323 | interrupts = <0x2a 0x2>; | |
| 324 | interrupt-parent = <&mpic>; | |
| 325 | }; | |
| 326 | ||
| 327 | serial1: serial@4600 { | |
| 328 | cell-index = <1>; | |
| 329 | device_type = "serial"; | |
| 330 | compatible = "ns16550"; | |
| 331 | reg = <0x4600 0x100>; // reg base, size | |
| 332 | clock-frequency = <0>; // should we fill in in uboot? | |
| 333 | interrupts = <0x2a 0x2>; | |
| 334 | interrupt-parent = <&mpic>; | |
| 335 | }; | |
| 336 | ||
| 337 | global-utilities@e0000 { //global utilities reg | |
| 338 | compatible = "fsl,mpc8548-guts"; | |
| 339 | reg = <0xe0000 0x1000>; | |
| 340 | fsl,has-rstcr; | |
| 341 | }; | |
| 342 | ||
| 3fd44736 KP |
343 | crypto@30000 { |
| 344 | compatible = "fsl,sec2.1", "fsl,sec2.0"; | |
| 345 | reg = <0x30000 0x10000>; | |
| 346 | interrupts = <45 2>; | |
| 347 | interrupt-parent = <&mpic>; | |
| 348 | fsl,num-channels = <4>; | |
| 349 | fsl,channel-fifo-len = <24>; | |
| 350 | fsl,exec-units-mask = <0xfe>; | |
| 351 | fsl,descriptor-types-mask = <0x12b0ebf>; | |
| 352 | }; | |
| 353 | ||
| 30340998 PG |
354 | mpic: pic@40000 { |
| 355 | interrupt-controller; | |
| 356 | #address-cells = <0>; | |
| 30340998 PG |
357 | #interrupt-cells = <2>; |
| 358 | reg = <0x40000 0x40000>; | |
| 359 | compatible = "chrp,open-pic"; | |
| 360 | device_type = "open-pic"; | |
| 30340998 PG |
361 | }; |
| 362 | }; | |
| 363 | ||
| 364 | pci0: pci@e0008000 { | |
| 30340998 PG |
365 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
| 366 | interrupt-map = < | |
| 3e0d65bf JM |
367 | /* IDSEL 0x01 (PCI-X slot) @66MHz */ |
| 368 | 0x0800 0x0 0x0 0x1 &mpic 0x2 0x1 | |
| 369 | 0x0800 0x0 0x0 0x2 &mpic 0x3 0x1 | |
| 370 | 0x0800 0x0 0x0 0x3 &mpic 0x4 0x1 | |
| 371 | 0x0800 0x0 0x0 0x4 &mpic 0x1 0x1 | |
| 372 | ||
| 373 | /* IDSEL 0x11 (PCI, 3.3V 32bit) @33MHz */ | |
| 374 | 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 | |
| 375 | 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1 | |
| 376 | 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1 | |
| 377 | 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1>; | |
| 30340998 PG |
378 | |
| 379 | interrupt-parent = <&mpic>; | |
| 380 | interrupts = <0x18 0x2>; | |
| 381 | bus-range = <0 0>; | |
| 382 | ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000 | |
| 383 | 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00800000>; | |
| 384 | clock-frequency = <66666666>; | |
| 385 | #interrupt-cells = <1>; | |
| 386 | #size-cells = <2>; | |
| 387 | #address-cells = <3>; | |
| 388 | reg = <0xe0008000 0x1000>; | |
| 389 | compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; | |
| 390 | device_type = "pci"; | |
| 391 | }; | |
| 392 | ||
| 393 | pci2: pcie@e000a000 { | |
| 30340998 PG |
394 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
| 395 | interrupt-map = < | |
| 396 | ||
| 397 | /* IDSEL 0x0 (PEX) */ | |
| 398 | 0x0000 0x0 0x0 0x1 &mpic 0x0 0x1 | |
| 399 | 0x0000 0x0 0x0 0x2 &mpic 0x1 0x1 | |
| 400 | 0x0000 0x0 0x0 0x3 &mpic 0x2 0x1 | |
| 401 | 0x0000 0x0 0x0 0x4 &mpic 0x3 0x1>; | |
| 402 | ||
| 403 | interrupt-parent = <&mpic>; | |
| 404 | interrupts = <0x1a 0x2>; | |
| 405 | bus-range = <0x0 0xff>; | |
| 406 | ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000 | |
| 407 | 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x08000000>; | |
| 408 | clock-frequency = <33333333>; | |
| 409 | #interrupt-cells = <1>; | |
| 410 | #size-cells = <2>; | |
| 411 | #address-cells = <3>; | |
| 412 | reg = <0xe000a000 0x1000>; | |
| 413 | compatible = "fsl,mpc8548-pcie"; | |
| 414 | device_type = "pci"; | |
| 415 | pcie@0 { | |
| 416 | reg = <0x0 0x0 0x0 0x0 0x0>; | |
| 417 | #size-cells = <2>; | |
| 418 | #address-cells = <3>; | |
| 419 | device_type = "pci"; | |
| 420 | ranges = <0x02000000 0x0 0xa0000000 | |
| 421 | 0x02000000 0x0 0xa0000000 | |
| 422 | 0x0 0x20000000 | |
| 423 | ||
| 424 | 0x01000000 0x0 0x00000000 | |
| 425 | 0x01000000 0x0 0x00000000 | |
| 426 | 0x0 0x08000000>; | |
| 427 | }; | |
| 428 | }; | |
| 429 | }; |