[deliverable/linux.git] / arch / powerpc / boot / dts / sbc8548.dts

/*
 * SBC8548 Device Tree Source
 *
 * Copyright 2007 Wind River Systems Inc.
 *
 * Paul Gortmaker (see MAINTAINERS for contact information)
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */


/dts-v1/;

/ {
	model = "SBC8548";
	compatible = "SBC8548";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
		/* pci1 doesn't have a corresponding physical connector */
		pci2 = &pci2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8548@0 {
			device_type = "cpu";
			reg = <0>;
			d-cache-line-size = <0x20>;	// 32 bytes
			i-cache-line-size = <0x20>;	// 32 bytes
			d-cache-size = <0x8000>;	// L1, 32K
			i-cache-size = <0x8000>;	// L1, 32K
			timebase-frequency = <0>;	// From uboot
			bus-frequency = <0>;
			clock-frequency = <0>;
			next-level-cache = <&L2>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x10000000>;
	};

	localbus@e0000000 {
		#address-cells = <2>;
		#size-cells = <1>;
		compatible = "simple-bus";
		reg = <0xe0000000 0x5000>;
		interrupt-parent = <&mpic>;

		ranges = <0x0 0x0 0xff800000 0x00800000		/*8MB Flash*/
			  0x3 0x0 0xf0000000 0x04000000		/*64MB SDRAM*/
			  0x4 0x0 0xf4000000 0x04000000 	/*64MB SDRAM*/
			  0x5 0x0 0xf8000000 0x00b10000		/* EPLD */
			  0x6 0x0 0xfb800000 0x04000000>;	/*64MB Flash*/


		flash@0,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "cfi-flash";
			reg = <0x0 0x0 0x800000>;
			bank-width = <1>;
			device-width = <1>;
			partition@0x0 {
				label = "space";
				reg = <0x00000000 0x00100000>;
			};
			partition@0x100000 {
				label = "bootloader";
				reg = <0x00100000 0x00700000>;
				read-only;
			};
		};

		epld@5,0 {
			compatible = "wrs,epld-localbus";
			#address-cells = <2>;
			#size-cells = <1>;
			reg = <0x5 0x0 0x00b10000>;
			ranges = <
				0x0 0x0 0x5 0x000000 0x1fff	/* LED */
				0x1 0x0 0x5 0x100000 0x1fff	/* Switches */
				0x3 0x0 0x5 0x300000 0x1fff	/* HW Rev. */
				0xb 0x0	0x5 0xb00000 0x1fff	/* EEPROM */
			>;

			led@0,0 {
				compatible = "led";
				reg = <0x0 0x0 0x1fff>;
			};

			switches@1,0 {
				compatible = "switches";
				reg = <0x1 0x0 0x1fff>;
			};

			hw-rev@3,0 {
				compatible = "hw-rev";
				reg = <0x3 0x0 0x1fff>;
			};

			eeprom@b,0 {
				compatible = "eeprom";
				reg = <0xb 0 0x1fff>;
			};

		};

		alt-flash@6,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x6 0x0 0x04000000>;
			compatible = "cfi-flash";
			bank-width = <4>;
			device-width = <1>;
			partition@0x0 {
				label = "bootloader";
				reg = <0x00000000 0x00100000>;
				read-only;
			};
			partition@0x00100000 {
				label = "file-system";
				reg = <0x00100000 0x01f00000>;
			};
			partition@0x02000000 {
				label = "boot-config";
				reg = <0x02000000 0x00100000>;
			};
			partition@0x02100000 {
				label = "space";
				reg = <0x02100000 0x01f00000>;
			};
                };
        };

	soc8548@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		ranges = <0x00000000 0xe0000000 0x00100000>;
		reg = <0xe0000000 0x00001000>;	// CCSRBAR
		bus-frequency = <0>;
		compatible = "simple-bus";

		memory-controller@2000 {
			compatible = "fsl,8548-memory-controller";
			reg = <0x2000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <0x12 0x2>;
		};

		L2: l2-cache-controller@20000 {
			compatible = "fsl,8548-l2-cache-controller";
			reg = <0x20000 0x1000>;
			cache-line-size = <0x20>;	// 32 bytes
			cache-size = <0x80000>;	// L2, 512K
			interrupt-parent = <&mpic>;
			interrupts = <0x10 0x2>;
		};

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <0x2b 0x2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <0x2b 0x2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		dma@21300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
			reg = <0x21300 0x4>;
			ranges = <0x0 0x21100 0x200>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,mpc8548-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x0 0x80>;
				cell-index = <0>;
				interrupt-parent = <&mpic>;
				interrupts = <20 2>;
			};
			dma-channel@80 {
				compatible = "fsl,mpc8548-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupt-parent = <&mpic>;
				interrupts = <21 2>;
			};
			dma-channel@100 {
				compatible = "fsl,mpc8548-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupt-parent = <&mpic>;
				interrupts = <22 2>;
			};
			dma-channel@180 {
				compatible = "fsl,mpc8548-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x180 0x80>;
				cell-index = <3>;
				interrupt-parent = <&mpic>;
				interrupts = <23 2>;
			};
		};

		mdio@24520 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,gianfar-mdio";
			reg = <0x24520 0x20>;

			phy0: ethernet-phy@19 {
				interrupt-parent = <&mpic>;
				interrupts = <0x6 0x1>;
				reg = <0x19>;
				device_type = "ethernet-phy";
			};
			phy1: ethernet-phy@1a {
				interrupt-parent = <&mpic>;
				interrupts = <0x7 0x1>;
				reg = <0x1a>;
				device_type = "ethernet-phy";
			};
		};

		enet0: ethernet@24000 {
			cell-index = <0>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x24000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy0>;
		};

		enet1: ethernet@25000 {
			cell-index = <1>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x25000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy1>;
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4500 0x100>;	// reg base, size
			clock-frequency = <0>;	// should we fill in in uboot?
			interrupts = <0x2a 0x2>;
			interrupt-parent = <&mpic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4600 0x100>;	// reg base, size
			clock-frequency = <0>;	// should we fill in in uboot?
			interrupts = <0x2a 0x2>;
			interrupt-parent = <&mpic>;
		};

		global-utilities@e0000 {	//global utilities reg
			compatible = "fsl,mpc8548-guts";
			reg = <0xe0000 0x1000>;
			fsl,has-rstcr;
		};

		mpic: pic@40000 {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x40000 0x40000>;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
		};
	};

	pci0: pci@e0008000 {
		cell-index = <0>;
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <
			/* IDSEL 0x01 (PCI-X slot) @66MHz */
			0x0800 0x0 0x0 0x1 &mpic 0x2 0x1
			0x0800 0x0 0x0 0x2 &mpic 0x3 0x1
			0x0800 0x0 0x0 0x3 &mpic 0x4 0x1
			0x0800 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x11 (PCI, 3.3V 32bit) @33MHz */
			0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
			0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
			0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
			0x8800 0x0 0x0 0x4 &mpic 0x1 0x1>;

		interrupt-parent = <&mpic>;
		interrupts = <0x18 0x2>;
		bus-range = <0 0>;
		ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
			  0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00800000>;
		clock-frequency = <66666666>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0008000 0x1000>;
		compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
		device_type = "pci";
	};

	pci2: pcie@e000a000 {
		cell-index = <2>;
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <

			/* IDSEL 0x0 (PEX) */
			0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
			0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
			0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
			0x0000 0x0 0x0 0x4 &mpic 0x3 0x1>;

		interrupt-parent = <&mpic>;
		interrupts = <0x1a 0x2>;
		bus-range = <0x0 0xff>;
		ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
			  0x01000000 0x0 0x00000000 0xe3000000 0x0 0x08000000>;
		clock-frequency = <33333333>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe000a000 0x1000>;
		compatible = "fsl,mpc8548-pcie";
		device_type = "pci";
		pcie@0 {
			reg = <0x0 0x0 0x0 0x0 0x0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x02000000 0x0 0xa0000000
				  0x02000000 0x0 0xa0000000
				  0x0 0x20000000

				  0x01000000 0x0 0x00000000
				  0x01000000 0x0 0x00000000
				  0x0 0x08000000>;
		};
	};
};
Commit	Line	Data
30340998 PG	1	/*
	2	* SBC8548 Device Tree Source
	3	*
	4	* Copyright 2007 Wind River Systems Inc.
	5	*
	6	* Paul Gortmaker (see MAINTAINERS for contact information)
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*/
	13
	14
	15	/dts-v1/;
	16
	17	/ {
	18	model = "SBC8548";
	19	compatible = "SBC8548";
	20	#address-cells = <1>;
	21	#size-cells = <1>;
	22
	23	aliases {
	24	ethernet0 = &enet0;
	25	ethernet1 = &enet1;
	26	serial0 = &serial0;
	27	serial1 = &serial1;
	28	pci0 = &pci0;
	29	/* pci1 doesn't have a corresponding physical connector */
	30	pci2 = &pci2;
	31	};
	32
	33	cpus {
	34	#address-cells = <1>;
	35	#size-cells = <0>;
	36
	37	PowerPC,8548@0 {
	38	device_type = "cpu";
	39	reg = <0>;
	40	d-cache-line-size = <0x20>; // 32 bytes
	41	i-cache-line-size = <0x20>; // 32 bytes
	42	d-cache-size = <0x8000>; // L1, 32K
	43	i-cache-size = <0x8000>; // L1, 32K
	44	timebase-frequency = <0>; // From uboot
	45	bus-frequency = <0>;
	46	clock-frequency = <0>;
c054065b	47	next-level-cache = <&L2>;
30340998 PG	48	};
	49	};
	50
	51	memory {
	52	device_type = "memory";
	53	reg = <0x00000000 0x10000000>;
	54	};
	55
bfd123bf JM	56	localbus@e0000000 {
	57	#address-cells = <2>;
	58	#size-cells = <1>;
	59	compatible = "simple-bus";
	60	reg = <0xe0000000 0x5000>;
	61	interrupt-parent = <&mpic>;
	62
	63	ranges = <0x0 0x0 0xff800000 0x00800000 /8MB Flash/
	64	0x3 0x0 0xf0000000 0x04000000 /64MB SDRAM/
	65	0x4 0x0 0xf4000000 0x04000000 /64MB SDRAM/
	66	0x5 0x0 0xf8000000 0x00b10000 /* EPLD */
	67	0x6 0x0 0xfb800000 0x04000000>; /64MB Flash/
	68
	69
	70	flash@0,0 {
	71	#address-cells = <1>;
	72	#size-cells = <1>;
	73	compatible = "cfi-flash";
	74	reg = <0x0 0x0 0x800000>;
	75	bank-width = <1>;
	76	device-width = <1>;
	77	partition@0x0 {
	78	label = "space";
	79	reg = <0x00000000 0x00100000>;
	80	};
	81	partition@0x100000 {
	82	label = "bootloader";
	83	reg = <0x00100000 0x00700000>;
	84	read-only;
	85	};
	86	};
	87
	88	epld@5,0 {
	89	compatible = "wrs,epld-localbus";
	90	#address-cells = <2>;
	91	#size-cells = <1>;
	92	reg = <0x5 0x0 0x00b10000>;
	93	ranges = <
	94	0x0 0x0 0x5 0x000000 0x1fff /* LED */
	95	0x1 0x0 0x5 0x100000 0x1fff /* Switches */
	96	0x3 0x0 0x5 0x300000 0x1fff /* HW Rev. */
	97	0xb 0x0 0x5 0xb00000 0x1fff /* EEPROM */
	98	>;
	99
	100	led@0,0 {
	101	compatible = "led";
	102	reg = <0x0 0x0 0x1fff>;
	103	};
	104
	105	switches@1,0 {
	106	compatible = "switches";
	107	reg = <0x1 0x0 0x1fff>;
	108	};
	109
	110	hw-rev@3,0 {
	111	compatible = "hw-rev";
	112	reg = <0x3 0x0 0x1fff>;
	113	};
	114
	115	eeprom@b,0 {
	116	compatible = "eeprom";
	117	reg = <0xb 0 0x1fff>;
	118	};
	119
120	};
121
122	alt-flash@6,0 {
123	#address-cells = <1>;
124	#size-cells = <1>;
125	reg = <0x6 0x0 0x04000000>;
126	compatible = "cfi-flash";
127	bank-width = <4>;
128	device-width = <1>;
129	partition@0x0 {
130	label = "bootloader";
131	reg = <0x00000000 0x00100000>;
132	read-only;
133	};
134	partition@0x00100000 {
135	label = "file-system";
136	reg = <0x00100000 0x01f00000>;
137	};
138	partition@0x02000000 {
139	label = "boot-config";
140	reg = <0x02000000 0x00100000>;
141	};
142	partition@0x02100000 {
143	label = "space";
144	reg = <0x02100000 0x01f00000>;
145	};
146	};
147	};
148
30340998 PG	149	soc8548@e0000000 {
	150	#address-cells = <1>;
	151	#size-cells = <1>;
	152	device_type = "soc";
	153	ranges = <0x00000000 0xe0000000 0x00100000>;
	154	reg = <0xe0000000 0x00001000>; // CCSRBAR
	155	bus-frequency = <0>;
bfd123bf	156	compatible = "simple-bus";
30340998 PG	157
	158	memory-controller@2000 {
	159	compatible = "fsl,8548-memory-controller";
	160	reg = <0x2000 0x1000>;
	161	interrupt-parent = <&mpic>;
	162	interrupts = <0x12 0x2>;
	163	};
	164
c054065b	165	L2: l2-cache-controller@20000 {
30340998 PG	166	compatible = "fsl,8548-l2-cache-controller";
	167	reg = <0x20000 0x1000>;
	168	cache-line-size = <0x20>; // 32 bytes
	169	cache-size = <0x80000>; // L2, 512K
	170	interrupt-parent = <&mpic>;
	171	interrupts = <0x10 0x2>;
	172	};
	173
	174	i2c@3000 {
	175	#address-cells = <1>;
	176	#size-cells = <0>;
	177	cell-index = <0>;
	178	compatible = "fsl-i2c";
	179	reg = <0x3000 0x100>;
	180	interrupts = <0x2b 0x2>;
	181	interrupt-parent = <&mpic>;
	182	dfsrr;
	183	};
	184
	185	i2c@3100 {
	186	#address-cells = <1>;
	187	#size-cells = <0>;
	188	cell-index = <1>;
	189	compatible = "fsl-i2c";
	190	reg = <0x3100 0x100>;
	191	interrupts = <0x2b 0x2>;
	192	interrupt-parent = <&mpic>;
	193	dfsrr;
	194	};
	195
dee80553 KG	196	dma@21300 {
	197	#address-cells = <1>;
	198	#size-cells = <1>;
	199	compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
	200	reg = <0x21300 0x4>;
	201	ranges = <0x0 0x21100 0x200>;
	202	cell-index = <0>;
	203	dma-channel@0 {
	204	compatible = "fsl,mpc8548-dma-channel",
	205	"fsl,eloplus-dma-channel";
	206	reg = <0x0 0x80>;
	207	cell-index = <0>;
	208	interrupt-parent = <&mpic>;
	209	interrupts = <20 2>;
	210	};
	211	dma-channel@80 {
	212	compatible = "fsl,mpc8548-dma-channel",
	213	"fsl,eloplus-dma-channel";
	214	reg = <0x80 0x80>;
	215	cell-index = <1>;
	216	interrupt-parent = <&mpic>;
	217	interrupts = <21 2>;
	218	};
	219	dma-channel@100 {
	220	compatible = "fsl,mpc8548-dma-channel",
	221	"fsl,eloplus-dma-channel";
	222	reg = <0x100 0x80>;
	223	cell-index = <2>;
	224	interrupt-parent = <&mpic>;
	225	interrupts = <22 2>;
	226	};
	227	dma-channel@180 {
	228	compatible = "fsl,mpc8548-dma-channel",
	229	"fsl,eloplus-dma-channel";
	230	reg = <0x180 0x80>;
	231	cell-index = <3>;
	232	interrupt-parent = <&mpic>;
	233	interrupts = <23 2>;
	234	};
	235	};
	236
30340998 PG	237	mdio@24520 {
	238	#address-cells = <1>;
	239	#size-cells = <0>;
	240	compatible = "fsl,gianfar-mdio";
	241	reg = <0x24520 0x20>;
	242
	243	phy0: ethernet-phy@19 {
	244	interrupt-parent = <&mpic>;
	245	interrupts = <0x6 0x1>;
	246	reg = <0x19>;
	247	device_type = "ethernet-phy";
	248	};
	249	phy1: ethernet-phy@1a {
	250	interrupt-parent = <&mpic>;
	251	interrupts = <0x7 0x1>;
	252	reg = <0x1a>;
	253	device_type = "ethernet-phy";
	254	};
	255	};
	256
	257	enet0: ethernet@24000 {
	258	cell-index = <0>;
	259	device_type = "network";
	260	model = "eTSEC";
	261	compatible = "gianfar";
	262	reg = <0x24000 0x1000>;
	263	local-mac-address = [ 00 00 00 00 00 00 ];
	264	interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
	265	interrupt-parent = <&mpic>;
	266	phy-handle = <&phy0>;
	267	};
	268
	269	enet1: ethernet@25000 {
	270	cell-index = <1>;
	271	device_type = "network";
	272	model = "eTSEC";
	273	compatible = "gianfar";
	274	reg = <0x25000 0x1000>;
	275	local-mac-address = [ 00 00 00 00 00 00 ];
	276	interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
	277	interrupt-parent = <&mpic>;
	278	phy-handle = <&phy1>;
	279	};
	280
	281	serial0: serial@4500 {
	282	cell-index = <0>;
	283	device_type = "serial";
	284	compatible = "ns16550";
	285	reg = <0x4500 0x100>; // reg base, size
	286	clock-frequency = <0>; // should we fill in in uboot?
	287	interrupts = <0x2a 0x2>;
	288	interrupt-parent = <&mpic>;
	289	};
	290
	291	serial1: serial@4600 {
	292	cell-index = <1>;
	293	device_type = "serial";
	294	compatible = "ns16550";
	295	reg = <0x4600 0x100>; // reg base, size
	296	clock-frequency = <0>; // should we fill in in uboot?
	297	interrupts = <0x2a 0x2>;
	298	interrupt-parent = <&mpic>;
	299	};
	300
301	global-utilities@e0000 { //global utilities reg
302	compatible = "fsl,mpc8548-guts";
303	reg = <0xe0000 0x1000>;
304	fsl,has-rstcr;
305	};
306
307	mpic: pic@40000 {
308	interrupt-controller;
309	#address-cells = <0>;
30340998 PG	310	#interrupt-cells = <2>;
	311	reg = <0x40000 0x40000>;
	312	compatible = "chrp,open-pic";
	313	device_type = "open-pic";
30340998 PG	314	};
	315	};
	316
	317	pci0: pci@e0008000 {
	318	cell-index = <0>;
	319	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
	320	interrupt-map = <
3e0d65bf JM	321	/* IDSEL 0x01 (PCI-X slot) @66MHz */
	322	0x0800 0x0 0x0 0x1 &mpic 0x2 0x1
	323	0x0800 0x0 0x0 0x2 &mpic 0x3 0x1
	324	0x0800 0x0 0x0 0x3 &mpic 0x4 0x1
	325	0x0800 0x0 0x0 0x4 &mpic 0x1 0x1
	326
	327	/* IDSEL 0x11 (PCI, 3.3V 32bit) @33MHz */
	328	0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
	329	0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
	330	0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
	331	0x8800 0x0 0x0 0x4 &mpic 0x1 0x1>;
30340998 PG	332
	333	interrupt-parent = <&mpic>;
	334	interrupts = <0x18 0x2>;
	335	bus-range = <0 0>;
	336	ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
	337	0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00800000>;
	338	clock-frequency = <66666666>;
	339	#interrupt-cells = <1>;
	340	#size-cells = <2>;
	341	#address-cells = <3>;
	342	reg = <0xe0008000 0x1000>;
	343	compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
	344	device_type = "pci";
	345	};
	346
	347	pci2: pcie@e000a000 {
	348	cell-index = <2>;
	349	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
	350	interrupt-map = <
	351
	352	/* IDSEL 0x0 (PEX) */
	353	0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
	354	0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
	355	0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
	356	0x0000 0x0 0x0 0x4 &mpic 0x3 0x1>;
	357
	358	interrupt-parent = <&mpic>;
	359	interrupts = <0x1a 0x2>;
	360	bus-range = <0x0 0xff>;
	361	ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
	362	0x01000000 0x0 0x00000000 0xe3000000 0x0 0x08000000>;
	363	clock-frequency = <33333333>;
	364	#interrupt-cells = <1>;
	365	#size-cells = <2>;
	366	#address-cells = <3>;
	367	reg = <0xe000a000 0x1000>;
	368	compatible = "fsl,mpc8548-pcie";
	369	device_type = "pci";
	370	pcie@0 {
	371	reg = <0x0 0x0 0x0 0x0 0x0>;
	372	#size-cells = <2>;
	373	#address-cells = <3>;
	374	device_type = "pci";
	375	ranges = <0x02000000 0x0 0xa0000000
	376	0x02000000 0x0 0xa0000000
	377	0x0 0x20000000
	378
	379	0x01000000 0x0 0x00000000
	380	0x01000000 0x0 0x00000000
	381	0x0 0x08000000>;
	382	};
	383	};
	384	};