[deliverable/linux.git] / arch / powerpc / boot / dts / sbc8560.dts

/*
 * SBC8560 Device Tree Source
 *
 * Copyright 2007 Wind River Systems Inc.
 *
 * Paul Gortmaker (see MAINTAINERS for contact information)
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/dts-v1/;

/ {
	model = "SBC8560";
	compatible = "SBC8560";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		ethernet2 = &enet2;
		ethernet3 = &enet3;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8560@0 {
			device_type = "cpu";
			reg = <0>;
			d-cache-line-size = <0x20>;	// 32 bytes
			i-cache-line-size = <0x20>;	// 32 bytes
			d-cache-size = <0x8000>;	// L1, 32K
			i-cache-size = <0x8000>;	// L1, 32K
			timebase-frequency = <0>;	// From uboot
			bus-frequency = <0>;
			clock-frequency = <0>;
			next-level-cache = <&L2>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x20000000>;
	};

	soc@ff700000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		ranges = <0x0 0xff700000 0x00100000>;
		clock-frequency = <0>;

		ecm-law@0 {
			compatible = "fsl,ecm-law";
			reg = <0x0 0x1000>;
			fsl,num-laws = <8>;
		};

		ecm@1000 {
			compatible = "fsl,mpc8560-ecm", "fsl,ecm";
			reg = <0x1000 0x1000>;
			interrupts = <17 2>;
			interrupt-parent = <&mpic>;
		};

		memory-controller@2000 {
			compatible = "fsl,mpc8560-memory-controller";
			reg = <0x2000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <0x12 0x2>;
		};

		L2: l2-cache-controller@20000 {
			compatible = "fsl,mpc8560-l2-cache-controller";
			reg = <0x20000 0x1000>;
			cache-line-size = <0x20>;	// 32 bytes
			cache-size = <0x40000>;		// L2, 256K
			interrupt-parent = <&mpic>;
			interrupts = <0x10 0x2>;
		};

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <0x2b 0x2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <0x2b 0x2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		dma@21300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
			reg = <0x21300 0x4>;
			ranges = <0x0 0x21100 0x200>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,mpc8560-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x0 0x80>;
				cell-index = <0>;
				interrupt-parent = <&mpic>;
				interrupts = <20 2>;
			};
			dma-channel@80 {
				compatible = "fsl,mpc8560-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupt-parent = <&mpic>;
				interrupts = <21 2>;
			};
			dma-channel@100 {
				compatible = "fsl,mpc8560-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupt-parent = <&mpic>;
				interrupts = <22 2>;
			};
			dma-channel@180 {
				compatible = "fsl,mpc8560-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x180 0x80>;
				cell-index = <3>;
				interrupt-parent = <&mpic>;
				interrupts = <23 2>;
			};
		};

		enet0: ethernet@24000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <0>;
			device_type = "network";
			model = "TSEC";
			compatible = "gianfar";
			reg = <0x24000 0x1000>;
			ranges = <0x0 0x24000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi0>;
			phy-handle = <&phy0>;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-mdio";
				reg = <0x520 0x20>;
				phy0: ethernet-phy@19 {
					interrupt-parent = <&mpic>;
					interrupts = <0x6 0x1>;
					reg = <0x19>;
					device_type = "ethernet-phy";
				};
				phy1: ethernet-phy@1a {
					interrupt-parent = <&mpic>;
					interrupts = <0x7 0x1>;
					reg = <0x1a>;
					device_type = "ethernet-phy";
				};
				phy2: ethernet-phy@1b {
					interrupt-parent = <&mpic>;
					interrupts = <0x8 0x1>;
					reg = <0x1b>;
					device_type = "ethernet-phy";
				};
				phy3: ethernet-phy@1c {
					interrupt-parent = <&mpic>;
					interrupts = <0x8 0x1>;
					reg = <0x1c>;
					device_type = "ethernet-phy";
				};
				tbi0: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		enet1: ethernet@25000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <1>;
			device_type = "network";
			model = "TSEC";
			compatible = "gianfar";
			reg = <0x25000 0x1000>;
			ranges = <0x0 0x25000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi1>;
			phy-handle = <&phy1>;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-tbi";
				reg = <0x520 0x20>;

				tbi1: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		mpic: pic@40000 {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			compatible = "chrp,open-pic";
			reg = <0x40000 0x40000>;
			device_type = "open-pic";
		};

		cpm@919c0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8560-cpm", "fsl,cpm2";
			reg = <0x919c0 0x30>;
			ranges;

			muram@80000 {
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0x80000 0x10000>;

				data@0 {
					compatible = "fsl,cpm-muram-data";
					reg = <0x0 0x4000 0x9000 0x2000>;
				};
			};

			brg@919f0 {
				compatible = "fsl,mpc8560-brg",
				             "fsl,cpm2-brg",
				             "fsl,cpm-brg";
				reg = <0x919f0 0x10 0x915f0 0x10>;
				clock-frequency = <165000000>;
			};

			cpmpic: pic@90c00 {
				interrupt-controller;
				#address-cells = <0>;
				#interrupt-cells = <2>;
				interrupts = <0x2e 0x2>;
				interrupt-parent = <&mpic>;
				reg = <0x90c00 0x80>;
				compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
			};

			enet2: ethernet@91320 {
				device_type = "network";
				compatible = "fsl,mpc8560-fcc-enet",
				             "fsl,cpm2-fcc-enet";
				reg = <0x91320 0x20 0x88500 0x100 0x913b0 0x1>;
				local-mac-address = [ 00 00 00 00 00 00 ];
				fsl,cpm-command = <0x16200300>;
				interrupts = <0x21 0x8>;
				interrupt-parent = <&cpmpic>;
				phy-handle = <&phy2>;
			};

			enet3: ethernet@91340 {
				device_type = "network";
				compatible = "fsl,mpc8560-fcc-enet",
				             "fsl,cpm2-fcc-enet";
				reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
				local-mac-address = [ 00 00 00 00 00 00 ];
				fsl,cpm-command = <0x1a400300>;
				interrupts = <0x22 0x8>;
				interrupt-parent = <&cpmpic>;
				phy-handle = <&phy3>;
			};
		};

		global-utilities@e0000 {
			compatible = "fsl,mpc8560-guts";
			reg = <0xe0000 0x1000>;
		};
	};

	pci0: pci@ff708000 {
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
		device_type = "pci";
		reg = <0xff708000 0x1000>;
		clock-frequency = <66666666>;
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <

			/* IDSEL 0x02 */
			0x1000 0x0 0x0 0x1 &mpic 0x2 0x1
			0x1000 0x0 0x0 0x2 &mpic 0x3 0x1
			0x1000 0x0 0x0 0x3 &mpic 0x4 0x1
			0x1000 0x0 0x0 0x4 &mpic 0x5 0x1>;

		interrupt-parent = <&mpic>;
		interrupts = <0x18 0x2>;
		bus-range = <0x0 0x0>;
		ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
			  0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
	};

	localbus@ff705000 {
		compatible = "fsl,mpc8560-localbus", "simple-bus";
		#address-cells = <2>;
		#size-cells = <1>;
		reg = <0xff705000 0x100>;	// BRx, ORx, etc.

		ranges = <
			0x0 0x0 0xff800000 0x0800000	// 8MB boot flash
			0x1 0x0 0xe4000000 0x4000000	// 64MB flash
			0x3 0x0 0x20000000 0x4000000	// 64MB SDRAM
			0x4 0x0 0x24000000 0x4000000	// 64MB SDRAM
			0x5 0x0 0xfc000000 0x0c00000	// EPLD
			0x6 0x0 0xe0000000 0x4000000	// 64MB flash
			0x7 0x0 0x80000000 0x0200000	// ATM1,2
		>;

		epld@5,0 {
			compatible = "wrs,epld-localbus";
			#address-cells = <2>;
			#size-cells = <1>;
			reg = <0x5 0x0 0xc00000>;
			ranges = <
				0x0 0x0 0x5 0x000000 0x1fff	// LED disp.
				0x1 0x0 0x5 0x100000 0x1fff	// switches
				0x2 0x0 0x5 0x200000 0x1fff	// ID reg.
				0x3 0x0 0x5 0x300000 0x1fff	// status reg.
				0x4 0x0 0x5 0x400000 0x1fff	// reset reg.
				0x5 0x0 0x5 0x500000 0x1fff	// Wind port
				0x7 0x0 0x5 0x700000 0x1fff	// UART #1
				0x8 0x0 0x5 0x800000 0x1fff	// UART #2
				0x9 0x0 0x5 0x900000 0x1fff	// RTC
				0xb 0x0 0x5 0xb00000 0x1fff	// EEPROM
			>;

			bidr@2,0 {
				compatible = "wrs,sbc8560-bidr";
				reg = <0x2 0x0 0x10>;
			};

			bcsr@3,0 {
				compatible = "wrs,sbc8560-bcsr";
				reg = <0x3 0x0 0x10>;
			};

			brstcr@4,0 {
				compatible = "wrs,sbc8560-brstcr";
				reg = <0x4 0x0 0x10>;
			};

			serial0: serial@7,0 {
				device_type = "serial";
				compatible = "ns16550";
				reg = <0x7 0x0 0x100>;
				clock-frequency = <1843200>;
				interrupts = <0x9 0x2>;
				interrupt-parent = <&mpic>;
			};

			serial1: serial@8,0 {
				device_type = "serial";
				compatible = "ns16550";
				reg = <0x8 0x0 0x100>;
				clock-frequency = <1843200>;
				interrupts = <0xa 0x2>;
				interrupt-parent = <&mpic>;
			};

			rtc@9,0 {
				compatible = "m48t59";
				reg = <0x9 0x0 0x1fff>;
			};
		};
	};
};
Commit	Line	Data
6a35b6f0 PG	1	/*
	2	* SBC8560 Device Tree Source
	3	*
	4	* Copyright 2007 Wind River Systems Inc.
	5	*
	6	* Paul Gortmaker (see MAINTAINERS for contact information)
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*/
	13
	14	/dts-v1/;
	15
	16	/ {
	17	model = "SBC8560";
	18	compatible = "SBC8560";
	19	#address-cells = <1>;
	20	#size-cells = <1>;
	21
	22	aliases {
	23	ethernet0 = &enet0;
	24	ethernet1 = &enet1;
	25	ethernet2 = &enet2;
	26	ethernet3 = &enet3;
	27	serial0 = &serial0;
	28	serial1 = &serial1;
	29	pci0 = &pci0;
	30	};
	31
	32	cpus {
	33	#address-cells = <1>;
	34	#size-cells = <0>;
	35
	36	PowerPC,8560@0 {
	37	device_type = "cpu";
	38	reg = <0>;
	39	d-cache-line-size = <0x20>; // 32 bytes
	40	i-cache-line-size = <0x20>; // 32 bytes
	41	d-cache-size = <0x8000>; // L1, 32K
	42	i-cache-size = <0x8000>; // L1, 32K
	43	timebase-frequency = <0>; // From uboot
	44	bus-frequency = <0>;
	45	clock-frequency = <0>;
c054065b	46	next-level-cache = <&L2>;
6a35b6f0 PG	47	};
	48	};
	49
	50	memory {
	51	device_type = "memory";
	52	reg = <0x00000000 0x20000000>;
	53	};
	54
	55	soc@ff700000 {
	56	#address-cells = <1>;
	57	#size-cells = <1>;
	58	device_type = "soc";
	59	ranges = <0x0 0xff700000 0x00100000>;
6a35b6f0 PG	60	clock-frequency = <0>;
6a35b6f0 PG	61
e1a22897 KG	62	ecm-law@0 {
	63	compatible = "fsl,ecm-law";
	64	reg = <0x0 0x1000>;
	65	fsl,num-laws = <8>;
	66	};
	67
	68	ecm@1000 {
	69	compatible = "fsl,mpc8560-ecm", "fsl,ecm";
	70	reg = <0x1000 0x1000>;
	71	interrupts = <17 2>;
	72	interrupt-parent = <&mpic>;
	73	};
	74
6a35b6f0	75	memory-controller@2000 {
fe671772	76	compatible = "fsl,mpc8560-memory-controller";
6a35b6f0 PG	77	reg = <0x2000 0x1000>;
	78	interrupt-parent = <&mpic>;
	79	interrupts = <0x12 0x2>;
	80	};
	81
c054065b	82	L2: l2-cache-controller@20000 {
fe671772	83	compatible = "fsl,mpc8560-l2-cache-controller";
6a35b6f0 PG	84	reg = <0x20000 0x1000>;
	85	cache-line-size = <0x20>; // 32 bytes
	86	cache-size = <0x40000>; // L2, 256K
	87	interrupt-parent = <&mpic>;
	88	interrupts = <0x10 0x2>;
	89	};
	90
	91	i2c@3000 {
	92	#address-cells = <1>;
	93	#size-cells = <0>;
	94	cell-index = <0>;
	95	compatible = "fsl-i2c";
	96	reg = <0x3000 0x100>;
	97	interrupts = <0x2b 0x2>;
	98	interrupt-parent = <&mpic>;
	99	dfsrr;
	100	};
	101
	102	i2c@3100 {
	103	#address-cells = <1>;
	104	#size-cells = <0>;
	105	cell-index = <1>;
	106	compatible = "fsl-i2c";
	107	reg = <0x3100 0x100>;
	108	interrupts = <0x2b 0x2>;
	109	interrupt-parent = <&mpic>;
	110	dfsrr;
	111	};
	112
dee80553 KG	113	dma@21300 {
	114	#address-cells = <1>;
	115	#size-cells = <1>;
	116	compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
	117	reg = <0x21300 0x4>;
	118	ranges = <0x0 0x21100 0x200>;
	119	cell-index = <0>;
	120	dma-channel@0 {
	121	compatible = "fsl,mpc8560-dma-channel",
	122	"fsl,eloplus-dma-channel";
	123	reg = <0x0 0x80>;
	124	cell-index = <0>;
	125	interrupt-parent = <&mpic>;
	126	interrupts = <20 2>;
	127	};
	128	dma-channel@80 {
	129	compatible = "fsl,mpc8560-dma-channel",
	130	"fsl,eloplus-dma-channel";
	131	reg = <0x80 0x80>;
	132	cell-index = <1>;
	133	interrupt-parent = <&mpic>;
	134	interrupts = <21 2>;
	135	};
	136	dma-channel@100 {
	137	compatible = "fsl,mpc8560-dma-channel",
	138	"fsl,eloplus-dma-channel";
	139	reg = <0x100 0x80>;
	140	cell-index = <2>;
	141	interrupt-parent = <&mpic>;
	142	interrupts = <22 2>;
	143	};
	144	dma-channel@180 {
	145	compatible = "fsl,mpc8560-dma-channel",
	146	"fsl,eloplus-dma-channel";
	147	reg = <0x180 0x80>;
	148	cell-index = <3>;
	149	interrupt-parent = <&mpic>;
	150	interrupts = <23 2>;
	151	};
	152	};
	153
6a35b6f0	154	enet0: ethernet@24000 {
84ba4a58 AV	155	#address-cells = <1>;
84ba4a58 AV	156	#size-cells = <1>;
6a35b6f0 PG	157	cell-index = <0>;
	158	device_type = "network";
	159	model = "TSEC";
	160	compatible = "gianfar";
	161	reg = <0x24000 0x1000>;
84ba4a58	162	ranges = <0x0 0x24000 0x1000>;
6a35b6f0 PG	163	local-mac-address = [ 00 00 00 00 00 00 ];
	164	interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
	165	interrupt-parent = <&mpic>;
b31a1d8b	166	tbi-handle = <&tbi0>;
6a35b6f0	167	phy-handle = <&phy0>;
84ba4a58 AV	168
	169	mdio@520 {
	170	#address-cells = <1>;
	171	#size-cells = <0>;
	172	compatible = "fsl,gianfar-mdio";
	173	reg = <0x520 0x20>;
	174	phy0: ethernet-phy@19 {
	175	interrupt-parent = <&mpic>;
	176	interrupts = <0x6 0x1>;
	177	reg = <0x19>;
	178	device_type = "ethernet-phy";
	179	};
	180	phy1: ethernet-phy@1a {
	181	interrupt-parent = <&mpic>;
	182	interrupts = <0x7 0x1>;
	183	reg = <0x1a>;
	184	device_type = "ethernet-phy";
	185	};
	186	phy2: ethernet-phy@1b {
	187	interrupt-parent = <&mpic>;
	188	interrupts = <0x8 0x1>;
	189	reg = <0x1b>;
	190	device_type = "ethernet-phy";
	191	};
	192	phy3: ethernet-phy@1c {
	193	interrupt-parent = <&mpic>;
	194	interrupts = <0x8 0x1>;
	195	reg = <0x1c>;
	196	device_type = "ethernet-phy";
	197	};
	198	tbi0: tbi-phy@11 {
	199	reg = <0x11>;
	200	device_type = "tbi-phy";
	201	};
	202	};
6a35b6f0 PG	203	};
	204
	205	enet1: ethernet@25000 {
84ba4a58 AV	206	#address-cells = <1>;
84ba4a58 AV	207	#size-cells = <1>;
6a35b6f0 PG	208	cell-index = <1>;
	209	device_type = "network";
	210	model = "TSEC";
	211	compatible = "gianfar";
	212	reg = <0x25000 0x1000>;
84ba4a58	213	ranges = <0x0 0x25000 0x1000>;
6a35b6f0 PG	214	local-mac-address = [ 00 00 00 00 00 00 ];
	215	interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
	216	interrupt-parent = <&mpic>;
b31a1d8b	217	tbi-handle = <&tbi1>;
6a35b6f0	218	phy-handle = <&phy1>;
84ba4a58 AV	219
	220	mdio@520 {
	221	#address-cells = <1>;
	222	#size-cells = <0>;
	223	compatible = "fsl,gianfar-tbi";
	224	reg = <0x520 0x20>;
	225
	226	tbi1: tbi-phy@11 {
	227	reg = <0x11>;
	228	device_type = "tbi-phy";
	229	};
	230	};
6a35b6f0 PG	231	};
	232
	233	mpic: pic@40000 {
	234	interrupt-controller;
	235	#address-cells = <0>;
6a35b6f0	236	#interrupt-cells = <2>;
acd4b715	237	compatible = "chrp,open-pic";
6a35b6f0 PG	238	reg = <0x40000 0x40000>;
	239	device_type = "open-pic";
	240	};
	241
	242	cpm@919c0 {
	243	#address-cells = <1>;
	244	#size-cells = <1>;
	245	compatible = "fsl,mpc8560-cpm", "fsl,cpm2";
	246	reg = <0x919c0 0x30>;
	247	ranges;
	248
	249	muram@80000 {
	250	#address-cells = <1>;
	251	#size-cells = <1>;
	252	ranges = <0x0 0x80000 0x10000>;
	253
	254	data@0 {
	255	compatible = "fsl,cpm-muram-data";
	256	reg = <0x0 0x4000 0x9000 0x2000>;
	257	};
	258	};
	259
	260	brg@919f0 {
	261	compatible = "fsl,mpc8560-brg",
	262	"fsl,cpm2-brg",
	263	"fsl,cpm-brg";
	264	reg = <0x919f0 0x10 0x915f0 0x10>;
	265	clock-frequency = <165000000>;
	266	};
	267
	268	cpmpic: pic@90c00 {
	269	interrupt-controller;
	270	#address-cells = <0>;
	271	#interrupt-cells = <2>;
	272	interrupts = <0x2e 0x2>;
	273	interrupt-parent = <&mpic>;
	274	reg = <0x90c00 0x80>;
	275	compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
	276	};
	277
	278	enet2: ethernet@91320 {
	279	device_type = "network";
	280	compatible = "fsl,mpc8560-fcc-enet",
	281	"fsl,cpm2-fcc-enet";
	282	reg = <0x91320 0x20 0x88500 0x100 0x913b0 0x1>;
	283	local-mac-address = [ 00 00 00 00 00 00 ];
	284	fsl,cpm-command = <0x16200300>;
	285	interrupts = <0x21 0x8>;
	286	interrupt-parent = <&cpmpic>;
	287	phy-handle = <&phy2>;
	288	};
	289
	290	enet3: ethernet@91340 {
	291	device_type = "network";
	292	compatible = "fsl,mpc8560-fcc-enet",
	293	"fsl,cpm2-fcc-enet";
	294	reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
	295	local-mac-address = [ 00 00 00 00 00 00 ];
	296	fsl,cpm-command = <0x1a400300>;
	297	interrupts = <0x22 0x8>;
	298	interrupt-parent = <&cpmpic>;
	299	phy-handle = <&phy3>;
	300	};
	301	};
302
303	global-utilities@e0000 {
304	compatible = "fsl,mpc8560-guts";
305	reg = <0xe0000 0x1000>;
6a35b6f0 PG	306	};
	307	};
	308
	309	pci0: pci@ff708000 {
6a35b6f0 PG	310	#interrupt-cells = <1>;
	311	#size-cells = <2>;
	312	#address-cells = <3>;
	313	compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
	314	device_type = "pci";
	315	reg = <0xff708000 0x1000>;
	316	clock-frequency = <66666666>;
	317	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
	318	interrupt-map = <
	319
	320	/* IDSEL 0x02 */
	321	0x1000 0x0 0x0 0x1 &mpic 0x2 0x1
	322	0x1000 0x0 0x0 0x2 &mpic 0x3 0x1
	323	0x1000 0x0 0x0 0x3 &mpic 0x4 0x1
	324	0x1000 0x0 0x0 0x4 &mpic 0x5 0x1>;
	325
	326	interrupt-parent = <&mpic>;
	327	interrupts = <0x18 0x2>;
	328	bus-range = <0x0 0x0>;
	329	ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
	330	0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
	331	};
	332
	333	localbus@ff705000 {
385c056b	334	compatible = "fsl,mpc8560-localbus", "simple-bus";
6a35b6f0 PG	335	#address-cells = <2>;
	336	#size-cells = <1>;
	337	reg = <0xff705000 0x100>; // BRx, ORx, etc.
	338
	339	ranges = <
	340	0x0 0x0 0xff800000 0x0800000 // 8MB boot flash
	341	0x1 0x0 0xe4000000 0x4000000 // 64MB flash
	342	0x3 0x0 0x20000000 0x4000000 // 64MB SDRAM
	343	0x4 0x0 0x24000000 0x4000000 // 64MB SDRAM
	344	0x5 0x0 0xfc000000 0x0c00000 // EPLD
	345	0x6 0x0 0xe0000000 0x4000000 // 64MB flash
	346	0x7 0x0 0x80000000 0x0200000 // ATM1,2
	347	>;
	348
	349	epld@5,0 {
	350	compatible = "wrs,epld-localbus";
	351	#address-cells = <2>;
	352	#size-cells = <1>;
	353	reg = <0x5 0x0 0xc00000>;
	354	ranges = <
	355	0x0 0x0 0x5 0x000000 0x1fff // LED disp.
	356	0x1 0x0 0x5 0x100000 0x1fff // switches
	357	0x2 0x0 0x5 0x200000 0x1fff // ID reg.
	358	0x3 0x0 0x5 0x300000 0x1fff // status reg.
	359	0x4 0x0 0x5 0x400000 0x1fff // reset reg.
	360	0x5 0x0 0x5 0x500000 0x1fff // Wind port
	361	0x7 0x0 0x5 0x700000 0x1fff // UART #1
	362	0x8 0x0 0x5 0x800000 0x1fff // UART #2
	363	0x9 0x0 0x5 0x900000 0x1fff // RTC
	364	0xb 0x0 0x5 0xb00000 0x1fff // EEPROM
	365	>;
	366
	367	bidr@2,0 {
	368	compatible = "wrs,sbc8560-bidr";
	369	reg = <0x2 0x0 0x10>;
	370	};
	371
	372	bcsr@3,0 {
	373	compatible = "wrs,sbc8560-bcsr";
	374	reg = <0x3 0x0 0x10>;
	375	};
	376
	377	brstcr@4,0 {
	378	compatible = "wrs,sbc8560-brstcr";
	379	reg = <0x4 0x0 0x10>;
	380	};
	381
	382	serial0: serial@7,0 {
	383	device_type = "serial";
	384	compatible = "ns16550";
	385	reg = <0x7 0x0 0x100>;
	386	clock-frequency = <1843200>;
	387	interrupts = <0x9 0x2>;
	388	interrupt-parent = <&mpic>;
	389	};
	390
	391	serial1: serial@8,0 {
	392	device_type = "serial";
	393	compatible = "ns16550";
	394	reg = <0x8 0x0 0x100>;
	395	clock-frequency = <1843200>;
	396	interrupts = <0xa 0x2>;
	397	interrupt-parent = <&mpic>;
	398	};
399
400	rtc@9,0 {
401	compatible = "m48t59";
402	reg = <0x9 0x0 0x1fff>;
403	};
404	};
405	};
406	};