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77e03a22 KG |
1 | /* |
2 | * STX GP3 - 8560 ADS Device Tree Source | |
3 | * | |
4 | * Copyright 2008 Freescale Semiconductor Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation; either version 2 of the License, or (at your | |
9 | * option) any later version. | |
10 | */ | |
11 | ||
12 | /dts-v1/; | |
13 | ||
14 | / { | |
15 | model = "stx,gp3"; | |
16 | compatible = "stx,gp3-8560", "stx,gp3"; | |
17 | #address-cells = <1>; | |
18 | #size-cells = <1>; | |
19 | ||
20 | aliases { | |
21 | ethernet0 = &enet0; | |
22 | ethernet1 = &enet1; | |
23 | serial0 = &serial0; | |
24 | pci0 = &pci0; | |
25 | }; | |
26 | ||
27 | cpus { | |
28 | #address-cells = <1>; | |
29 | #size-cells = <0>; | |
30 | ||
31 | PowerPC,8560@0 { | |
32 | device_type = "cpu"; | |
33 | reg = <0>; | |
34 | d-cache-line-size = <32>; | |
35 | i-cache-line-size = <32>; | |
36 | d-cache-size = <32768>; | |
37 | i-cache-size = <32768>; | |
38 | timebase-frequency = <0>; | |
39 | bus-frequency = <0>; | |
40 | clock-frequency = <0>; | |
c054065b | 41 | next-level-cache = <&L2>; |
77e03a22 KG |
42 | }; |
43 | }; | |
44 | ||
45 | memory { | |
46 | device_type = "memory"; | |
47 | reg = <0x00000000 0x10000000>; | |
48 | }; | |
49 | ||
f67be814 | 50 | soc@fdf00000 { |
77e03a22 KG |
51 | #address-cells = <1>; |
52 | #size-cells = <1>; | |
53 | device_type = "soc"; | |
54 | ranges = <0 0xfdf00000 0x100000>; | |
77e03a22 KG |
55 | bus-frequency = <0>; |
56 | compatible = "fsl,mpc8560-immr", "simple-bus"; | |
57 | ||
e1a22897 KG |
58 | ecm-law@0 { |
59 | compatible = "fsl,ecm-law"; | |
60 | reg = <0x0 0x1000>; | |
61 | fsl,num-laws = <8>; | |
62 | }; | |
63 | ||
64 | ecm@1000 { | |
65 | compatible = "fsl,mpc8560-ecm", "fsl,ecm"; | |
66 | reg = <0x1000 0x1000>; | |
67 | interrupts = <17 2>; | |
68 | interrupt-parent = <&mpic>; | |
69 | }; | |
70 | ||
77e03a22 | 71 | memory-controller@2000 { |
fe671772 | 72 | compatible = "fsl,mpc8540-memory-controller"; |
77e03a22 KG |
73 | reg = <0x2000 0x1000>; |
74 | interrupt-parent = <&mpic>; | |
75 | interrupts = <18 2>; | |
76 | }; | |
77 | ||
c054065b | 78 | L2: l2-cache-controller@20000 { |
fe671772 | 79 | compatible = "fsl,mpc8540-l2-cache-controller"; |
77e03a22 KG |
80 | reg = <0x20000 0x1000>; |
81 | cache-line-size = <32>; | |
82 | cache-size = <0x40000>; // L2, 256K | |
83 | interrupt-parent = <&mpic>; | |
84 | interrupts = <16 2>; | |
85 | }; | |
86 | ||
87 | i2c@3000 { | |
88 | #address-cells = <1>; | |
89 | #size-cells = <0>; | |
90 | cell-index = <0>; | |
91 | compatible = "fsl-i2c"; | |
92 | reg = <0x3000 0x100>; | |
93 | interrupts = <43 2>; | |
94 | interrupt-parent = <&mpic>; | |
95 | dfsrr; | |
96 | }; | |
97 | ||
dee80553 KG |
98 | dma@21300 { |
99 | #address-cells = <1>; | |
100 | #size-cells = <1>; | |
101 | compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma"; | |
102 | reg = <0x21300 0x4>; | |
103 | ranges = <0x0 0x21100 0x200>; | |
104 | cell-index = <0>; | |
105 | dma-channel@0 { | |
106 | compatible = "fsl,mpc8560-dma-channel", | |
107 | "fsl,eloplus-dma-channel"; | |
108 | reg = <0x0 0x80>; | |
109 | cell-index = <0>; | |
110 | interrupt-parent = <&mpic>; | |
111 | interrupts = <20 2>; | |
112 | }; | |
113 | dma-channel@80 { | |
114 | compatible = "fsl,mpc8560-dma-channel", | |
115 | "fsl,eloplus-dma-channel"; | |
116 | reg = <0x80 0x80>; | |
117 | cell-index = <1>; | |
118 | interrupt-parent = <&mpic>; | |
119 | interrupts = <21 2>; | |
120 | }; | |
121 | dma-channel@100 { | |
122 | compatible = "fsl,mpc8560-dma-channel", | |
123 | "fsl,eloplus-dma-channel"; | |
124 | reg = <0x100 0x80>; | |
125 | cell-index = <2>; | |
126 | interrupt-parent = <&mpic>; | |
127 | interrupts = <22 2>; | |
128 | }; | |
129 | dma-channel@180 { | |
130 | compatible = "fsl,mpc8560-dma-channel", | |
131 | "fsl,eloplus-dma-channel"; | |
132 | reg = <0x180 0x80>; | |
133 | cell-index = <3>; | |
134 | interrupt-parent = <&mpic>; | |
135 | interrupts = <23 2>; | |
136 | }; | |
137 | }; | |
138 | ||
77e03a22 | 139 | enet0: ethernet@24000 { |
84ba4a58 AV |
140 | #address-cells = <1>; |
141 | #size-cells = <1>; | |
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142 | cell-index = <0>; |
143 | device_type = "network"; | |
144 | model = "TSEC"; | |
145 | compatible = "gianfar"; | |
146 | reg = <0x24000 0x1000>; | |
84ba4a58 | 147 | ranges = <0x0 0x24000 0x1000>; |
77e03a22 KG |
148 | local-mac-address = [ 00 00 00 00 00 00 ]; |
149 | interrupts = <29 2 30 2 34 2>; | |
150 | interrupt-parent = <&mpic>; | |
b31a1d8b | 151 | tbi-handle = <&tbi0>; |
77e03a22 | 152 | phy-handle = <&phy2>; |
84ba4a58 AV |
153 | |
154 | mdio@520 { | |
155 | #address-cells = <1>; | |
156 | #size-cells = <0>; | |
157 | compatible = "fsl,gianfar-mdio"; | |
158 | reg = <0x520 0x20>; | |
159 | ||
160 | phy2: ethernet-phy@2 { | |
161 | interrupt-parent = <&mpic>; | |
162 | interrupts = <5 4>; | |
163 | reg = <2>; | |
164 | device_type = "ethernet-phy"; | |
165 | }; | |
166 | phy4: ethernet-phy@4 { | |
167 | interrupt-parent = <&mpic>; | |
168 | interrupts = <5 4>; | |
169 | reg = <4>; | |
170 | device_type = "ethernet-phy"; | |
171 | }; | |
172 | tbi0: tbi-phy@11 { | |
173 | reg = <0x11>; | |
174 | device_type = "tbi-phy"; | |
175 | }; | |
176 | }; | |
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177 | }; |
178 | ||
179 | enet1: ethernet@25000 { | |
84ba4a58 AV |
180 | #address-cells = <1>; |
181 | #size-cells = <1>; | |
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182 | cell-index = <1>; |
183 | device_type = "network"; | |
184 | model = "TSEC"; | |
185 | compatible = "gianfar"; | |
186 | reg = <0x25000 0x1000>; | |
84ba4a58 | 187 | ranges = <0x0 0x25000 0x1000>; |
77e03a22 KG |
188 | local-mac-address = [ 00 00 00 00 00 00 ]; |
189 | interrupts = <35 2 36 2 40 2>; | |
190 | interrupt-parent = <&mpic>; | |
b31a1d8b | 191 | tbi-handle = <&tbi1>; |
77e03a22 | 192 | phy-handle = <&phy4>; |
84ba4a58 AV |
193 | |
194 | mdio@520 { | |
195 | #address-cells = <1>; | |
196 | #size-cells = <0>; | |
197 | compatible = "fsl,gianfar-tbi"; | |
198 | reg = <0x520 0x20>; | |
199 | ||
200 | tbi1: tbi-phy@11 { | |
201 | reg = <0x11>; | |
202 | device_type = "tbi-phy"; | |
203 | }; | |
204 | }; | |
77e03a22 KG |
205 | }; |
206 | ||
207 | mpic: pic@40000 { | |
208 | interrupt-controller; | |
209 | #address-cells = <0>; | |
210 | #interrupt-cells = <2>; | |
211 | reg = <0x40000 0x40000>; | |
acd4b715 | 212 | compatible = "chrp,open-pic"; |
77e03a22 KG |
213 | device_type = "open-pic"; |
214 | }; | |
215 | ||
216 | cpm@919c0 { | |
217 | #address-cells = <1>; | |
218 | #size-cells = <1>; | |
219 | compatible = "fsl,mpc8560-cpm", "fsl,cpm2", "simple-bus"; | |
220 | reg = <0x919c0 0x30>; | |
221 | ranges; | |
222 | ||
223 | muram@80000 { | |
224 | #address-cells = <1>; | |
225 | #size-cells = <1>; | |
226 | ranges = <0 0x80000 0x10000>; | |
227 | ||
228 | data@0 { | |
229 | compatible = "fsl,cpm-muram-data"; | |
230 | reg = <0 0x4000 0x9000 0x2000>; | |
231 | }; | |
232 | }; | |
233 | ||
234 | brg@919f0 { | |
235 | compatible = "fsl,mpc8560-brg", | |
236 | "fsl,cpm2-brg", | |
237 | "fsl,cpm-brg"; | |
238 | reg = <0x919f0 0x10 0x915f0 0x10>; | |
239 | clock-frequency = <0>; | |
240 | }; | |
241 | ||
242 | cpmpic: pic@90c00 { | |
243 | interrupt-controller; | |
244 | #address-cells = <0>; | |
245 | #interrupt-cells = <2>; | |
246 | interrupts = <46 2>; | |
247 | interrupt-parent = <&mpic>; | |
248 | reg = <0x90c00 0x80>; | |
249 | compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic"; | |
250 | }; | |
251 | ||
252 | serial0: serial@91a20 { | |
253 | device_type = "serial"; | |
254 | compatible = "fsl,mpc8560-scc-uart", | |
255 | "fsl,cpm2-scc-uart"; | |
256 | reg = <0x91a20 0x20 0x88100 0x100>; | |
257 | fsl,cpm-brg = <2>; | |
258 | fsl,cpm-command = <0x4a00000>; | |
259 | interrupts = <41 8>; | |
260 | interrupt-parent = <&cpmpic>; | |
261 | }; | |
262 | }; | |
263 | }; | |
264 | ||
265 | pci0: pci@fdf08000 { | |
77e03a22 KG |
266 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
267 | interrupt-map = < | |
268 | ||
269 | /* IDSEL 0x0c */ | |
270 | 0x6000 0 0 1 &mpic 1 1 | |
271 | 0x6000 0 0 2 &mpic 2 1 | |
272 | 0x6000 0 0 3 &mpic 3 1 | |
273 | 0x6000 0 0 4 &mpic 4 1 | |
274 | ||
275 | /* IDSEL 0x0d */ | |
276 | 0x6800 0 0 1 &mpic 4 1 | |
277 | 0x6800 0 0 2 &mpic 1 1 | |
278 | 0x6800 0 0 3 &mpic 2 1 | |
279 | 0x6800 0 0 4 &mpic 3 1 | |
280 | ||
281 | /* IDSEL 0x0e */ | |
282 | 0x7000 0 0 1 &mpic 3 1 | |
283 | 0x7000 0 0 2 &mpic 4 1 | |
284 | 0x7000 0 0 3 &mpic 1 1 | |
285 | 0x7000 0 0 4 &mpic 2 1 | |
286 | ||
287 | /* IDSEL 0x0f */ | |
288 | 0x7800 0 0 1 &mpic 2 1 | |
289 | 0x7800 0 0 2 &mpic 3 1 | |
290 | 0x7800 0 0 3 &mpic 4 1 | |
291 | 0x7800 0 0 4 &mpic 1 1>; | |
292 | ||
293 | interrupt-parent = <&mpic>; | |
294 | interrupts = <24 2>; | |
295 | bus-range = <0 0>; | |
296 | ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 | |
297 | 0x01000000 0 0x00000000 0xe2000000 0 0x00100000>; | |
298 | clock-frequency = <66666666>; | |
299 | #interrupt-cells = <1>; | |
300 | #size-cells = <2>; | |
301 | #address-cells = <3>; | |
302 | reg = <0xfdf08000 0x1000>; | |
303 | compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; | |
304 | device_type = "pci"; | |
305 | }; | |
306 | }; |