projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 0052bc5d KG |
1 | /* |
| 2 | * TQM 8540 Device Tree Source | |
| 3 | * | |
| 4 | * Copyright 2008 Freescale Semiconductor Inc. | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or modify it | |
| 7 | * under the terms of the GNU General Public License as published by the | |
| 8 | * Free Software Foundation; either version 2 of the License, or (at your | |
| 9 | * option) any later version. | |
| 10 | */ | |
| 11 | ||
| 12 | /dts-v1/; | |
| 13 | ||
| 14 | / { | |
| 4fb035f6 WG |
15 | model = "tqc,tqm8540"; |
| 16 | compatible = "tqc,tqm8540"; | |
| 0052bc5d KG |
17 | #address-cells = <1>; |
| 18 | #size-cells = <1>; | |
| 19 | ||
| 20 | aliases { | |
| 21 | ethernet0 = &enet0; | |
| 22 | ethernet1 = &enet1; | |
| 23 | ethernet2 = &enet2; | |
| 24 | serial0 = &serial0; | |
| 25 | serial1 = &serial1; | |
| 26 | pci0 = &pci0; | |
| 27 | }; | |
| 28 | ||
| 29 | cpus { | |
| 30 | #address-cells = <1>; | |
| 31 | #size-cells = <0>; | |
| 32 | ||
| 33 | PowerPC,8540@0 { | |
| 34 | device_type = "cpu"; | |
| 35 | reg = <0>; | |
| 36 | d-cache-line-size = <32>; | |
| 37 | i-cache-line-size = <32>; | |
| 38 | d-cache-size = <32768>; | |
| 39 | i-cache-size = <32768>; | |
| 40 | timebase-frequency = <0>; | |
| 41 | bus-frequency = <0>; | |
| 42 | clock-frequency = <0>; | |
| c054065b | 43 | next-level-cache = <&L2>; |
| 0052bc5d KG |
44 | }; |
| 45 | }; | |
| 46 | ||
| 47 | memory { | |
| 48 | device_type = "memory"; | |
| 49 | reg = <0x00000000 0x10000000>; | |
| 50 | }; | |
| 51 | ||
| f67be814 | 52 | soc@e0000000 { |
| 0052bc5d KG |
53 | #address-cells = <1>; |
| 54 | #size-cells = <1>; | |
| 55 | device_type = "soc"; | |
| 56 | ranges = <0x0 0xe0000000 0x100000>; | |
| 0052bc5d KG |
57 | bus-frequency = <0>; |
| 58 | compatible = "fsl,mpc8540-immr", "simple-bus"; | |
| 59 | ||
| e1a22897 KG |
60 | ecm-law@0 { |
| 61 | compatible = "fsl,ecm-law"; | |
| 62 | reg = <0x0 0x1000>; | |
| 63 | fsl,num-laws = <8>; | |
| 64 | }; | |
| 65 | ||
| 66 | ecm@1000 { | |
| 67 | compatible = "fsl,mpc8540-ecm", "fsl,ecm"; | |
| 68 | reg = <0x1000 0x1000>; | |
| 69 | interrupts = <17 2>; | |
| 70 | interrupt-parent = <&mpic>; | |
| 71 | }; | |
| 72 | ||
| 0052bc5d | 73 | memory-controller@2000 { |
| fe671772 | 74 | compatible = "fsl,mpc8540-memory-controller"; |
| 0052bc5d KG |
75 | reg = <0x2000 0x1000>; |
| 76 | interrupt-parent = <&mpic>; | |
| 77 | interrupts = <18 2>; | |
| 78 | }; | |
| 79 | ||
| c054065b | 80 | L2: l2-cache-controller@20000 { |
| fe671772 | 81 | compatible = "fsl,mpc8540-l2-cache-controller"; |
| 0052bc5d KG |
82 | reg = <0x20000 0x1000>; |
| 83 | cache-line-size = <32>; | |
| 84 | cache-size = <0x40000>; // L2, 256K | |
| 85 | interrupt-parent = <&mpic>; | |
| 86 | interrupts = <16 2>; | |
| 87 | }; | |
| 88 | ||
| 89 | i2c@3000 { | |
| 90 | #address-cells = <1>; | |
| 91 | #size-cells = <0>; | |
| 92 | cell-index = <0>; | |
| 93 | compatible = "fsl-i2c"; | |
| 94 | reg = <0x3000 0x100>; | |
| 95 | interrupts = <43 2>; | |
| 96 | interrupt-parent = <&mpic>; | |
| 97 | dfsrr; | |
| 98 | ||
| 6467cae3 | 99 | dtt@48 { |
| 0f73a449 | 100 | compatible = "national,lm75"; |
| 6467cae3 | 101 | reg = <0x48>; |
| 0f73a449 WG |
102 | }; |
| 103 | ||
| 0052bc5d KG |
104 | rtc@68 { |
| 105 | compatible = "dallas,ds1337"; | |
| 106 | reg = <0x68>; | |
| 107 | }; | |
| 108 | }; | |
| 109 | ||
| dee80553 KG |
110 | dma@21300 { |
| 111 | #address-cells = <1>; | |
| 112 | #size-cells = <1>; | |
| 113 | compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma"; | |
| 114 | reg = <0x21300 0x4>; | |
| 115 | ranges = <0x0 0x21100 0x200>; | |
| 116 | cell-index = <0>; | |
| 117 | dma-channel@0 { | |
| 118 | compatible = "fsl,mpc8540-dma-channel", | |
| 119 | "fsl,eloplus-dma-channel"; | |
| 120 | reg = <0x0 0x80>; | |
| 121 | cell-index = <0>; | |
| 122 | interrupt-parent = <&mpic>; | |
| 123 | interrupts = <20 2>; | |
| 124 | }; | |
| 125 | dma-channel@80 { | |
| 126 | compatible = "fsl,mpc8540-dma-channel", | |
| 127 | "fsl,eloplus-dma-channel"; | |
| 128 | reg = <0x80 0x80>; | |
| 129 | cell-index = <1>; | |
| 130 | interrupt-parent = <&mpic>; | |
| 131 | interrupts = <21 2>; | |
| 132 | }; | |
| 133 | dma-channel@100 { | |
| 134 | compatible = "fsl,mpc8540-dma-channel", | |
| 135 | "fsl,eloplus-dma-channel"; | |
| 136 | reg = <0x100 0x80>; | |
| 137 | cell-index = <2>; | |
| 138 | interrupt-parent = <&mpic>; | |
| 139 | interrupts = <22 2>; | |
| 140 | }; | |
| 141 | dma-channel@180 { | |
| 142 | compatible = "fsl,mpc8540-dma-channel", | |
| 143 | "fsl,eloplus-dma-channel"; | |
| 144 | reg = <0x180 0x80>; | |
| 145 | cell-index = <3>; | |
| 146 | interrupt-parent = <&mpic>; | |
| 147 | interrupts = <23 2>; | |
| 148 | }; | |
| 149 | }; | |
| 150 | ||
| 0052bc5d | 151 | enet0: ethernet@24000 { |
| 84ba4a58 AV |
152 | #address-cells = <1>; |
| 153 | #size-cells = <1>; | |
| 0052bc5d KG |
154 | cell-index = <0>; |
| 155 | device_type = "network"; | |
| 156 | model = "TSEC"; | |
| 157 | compatible = "gianfar"; | |
| 158 | reg = <0x24000 0x1000>; | |
| 84ba4a58 | 159 | ranges = <0x0 0x24000 0x1000>; |
| 0052bc5d KG |
160 | local-mac-address = [ 00 00 00 00 00 00 ]; |
| 161 | interrupts = <29 2 30 2 34 2>; | |
| 162 | interrupt-parent = <&mpic>; | |
| 163 | phy-handle = <&phy2>; | |
| 84ba4a58 AV |
164 | |
| 165 | mdio@520 { | |
| 166 | #address-cells = <1>; | |
| 167 | #size-cells = <0>; | |
| 168 | compatible = "fsl,gianfar-mdio"; | |
| 169 | reg = <0x520 0x20>; | |
| 170 | ||
| 171 | phy1: ethernet-phy@1 { | |
| 172 | interrupt-parent = <&mpic>; | |
| 173 | interrupts = <8 1>; | |
| 174 | reg = <1>; | |
| 175 | device_type = "ethernet-phy"; | |
| 176 | }; | |
| 177 | phy2: ethernet-phy@2 { | |
| 178 | interrupt-parent = <&mpic>; | |
| 179 | interrupts = <8 1>; | |
| 180 | reg = <2>; | |
| 181 | device_type = "ethernet-phy"; | |
| 182 | }; | |
| 183 | phy3: ethernet-phy@3 { | |
| 184 | interrupt-parent = <&mpic>; | |
| 185 | interrupts = <8 1>; | |
| 186 | reg = <3>; | |
| 187 | device_type = "ethernet-phy"; | |
| 188 | }; | |
| 189 | tbi0: tbi-phy@11 { | |
| 190 | reg = <0x11>; | |
| 191 | device_type = "tbi-phy"; | |
| 192 | }; | |
| 193 | }; | |
| 0052bc5d KG |
194 | }; |
| 195 | ||
| 196 | enet1: ethernet@25000 { | |
| 84ba4a58 AV |
197 | #address-cells = <1>; |
| 198 | #size-cells = <1>; | |
| 0052bc5d KG |
199 | cell-index = <1>; |
| 200 | device_type = "network"; | |
| 201 | model = "TSEC"; | |
| 202 | compatible = "gianfar"; | |
| 203 | reg = <0x25000 0x1000>; | |
| 84ba4a58 | 204 | ranges = <0x0 0x25000 0x1000>; |
| 0052bc5d KG |
205 | local-mac-address = [ 00 00 00 00 00 00 ]; |
| 206 | interrupts = <35 2 36 2 40 2>; | |
| 207 | interrupt-parent = <&mpic>; | |
| 208 | phy-handle = <&phy1>; | |
| 84ba4a58 AV |
209 | |
| 210 | mdio@520 { | |
| 211 | #address-cells = <1>; | |
| 212 | #size-cells = <0>; | |
| 213 | compatible = "fsl,gianfar-tbi"; | |
| 214 | reg = <0x520 0x20>; | |
| 215 | ||
| 216 | tbi1: tbi-phy@11 { | |
| 217 | reg = <0x11>; | |
| 218 | device_type = "tbi-phy"; | |
| 219 | }; | |
| 220 | }; | |
| 0052bc5d KG |
221 | }; |
| 222 | ||
| 223 | enet2: ethernet@26000 { | |
| 84ba4a58 AV |
224 | #address-cells = <1>; |
| 225 | #size-cells = <1>; | |
| 0052bc5d KG |
226 | cell-index = <2>; |
| 227 | device_type = "network"; | |
| 228 | model = "FEC"; | |
| 229 | compatible = "gianfar"; | |
| 230 | reg = <0x26000 0x1000>; | |
| 84ba4a58 | 231 | ranges = <0x0 0x26000 0x1000>; |
| 0052bc5d KG |
232 | local-mac-address = [ 00 00 00 00 00 00 ]; |
| 233 | interrupts = <41 2>; | |
| 234 | interrupt-parent = <&mpic>; | |
| 235 | phy-handle = <&phy3>; | |
| 84ba4a58 AV |
236 | |
| 237 | mdio@520 { | |
| 238 | #address-cells = <1>; | |
| 239 | #size-cells = <0>; | |
| 240 | compatible = "fsl,gianfar-tbi"; | |
| 241 | reg = <0x520 0x20>; | |
| 242 | ||
| 243 | tbi2: tbi-phy@11 { | |
| 244 | reg = <0x11>; | |
| 245 | device_type = "tbi-phy"; | |
| 246 | }; | |
| 247 | }; | |
| 0052bc5d KG |
248 | }; |
| 249 | ||
| 250 | serial0: serial@4500 { | |
| 251 | cell-index = <0>; | |
| 252 | device_type = "serial"; | |
| 253 | compatible = "ns16550"; | |
| 254 | reg = <0x4500 0x100>; // reg base, size | |
| 255 | clock-frequency = <0>; // should we fill in in uboot? | |
| 256 | interrupts = <42 2>; | |
| 257 | interrupt-parent = <&mpic>; | |
| 258 | }; | |
| 259 | ||
| 260 | serial1: serial@4600 { | |
| 261 | cell-index = <1>; | |
| 262 | device_type = "serial"; | |
| 263 | compatible = "ns16550"; | |
| 264 | reg = <0x4600 0x100>; // reg base, size | |
| 265 | clock-frequency = <0>; // should we fill in in uboot? | |
| 266 | interrupts = <42 2>; | |
| 267 | interrupt-parent = <&mpic>; | |
| 268 | }; | |
| 269 | ||
| 270 | mpic: pic@40000 { | |
| 271 | interrupt-controller; | |
| 272 | #address-cells = <0>; | |
| 273 | #interrupt-cells = <2>; | |
| 274 | reg = <0x40000 0x40000>; | |
| 275 | device_type = "open-pic"; | |
| acd4b715 | 276 | compatible = "chrp,open-pic"; |
| 0052bc5d KG |
277 | }; |
| 278 | }; | |
| 279 | ||
| 280 | pci0: pci@e0008000 { | |
| 0052bc5d KG |
281 | #interrupt-cells = <1>; |
| 282 | #size-cells = <2>; | |
| 283 | #address-cells = <3>; | |
| 284 | compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; | |
| 285 | device_type = "pci"; | |
| 286 | reg = <0xe0008000 0x1000>; | |
| 287 | clock-frequency = <66666666>; | |
| 288 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | |
| 289 | interrupt-map = < | |
| 290 | /* IDSEL 28 */ | |
| 291 | 0xe000 0 0 1 &mpic 2 1 | |
| 292 | 0xe000 0 0 2 &mpic 3 1>; | |
| 293 | ||
| 294 | interrupt-parent = <&mpic>; | |
| 295 | interrupts = <24 2>; | |
| 296 | bus-range = <0 0>; | |
| 297 | ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 | |
| 298 | 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>; | |
| 299 | }; | |
| 300 | }; |