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powerpc/mm: Abstraction for vmemmap and map_kernel_page()
[deliverable/linux.git] / arch / powerpc / include / asm / book3s / 64 / pgtable.h
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3dfcb315
AK		 1#ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
2#define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
2e873519
AK		 3
4/*
5 * Common bits between hash and Radix page table
6 */
7#define _PAGE_BIT_SWAP_TYPE 0
8
9#define _PAGE_EXEC 0x00001 /* execute permission */
10#define _PAGE_WRITE 0x00002 /* write access allowed */
11#define _PAGE_READ 0x00004 /* read access allowed */
12#define _PAGE_RW (_PAGE_READ | _PAGE_WRITE)
13#define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)
14#define _PAGE_PRIVILEGED 0x00008 /* kernel access only */
15#define _PAGE_SAO 0x00010 /* Strong access order */
16#define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */
17#define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */
18#define _PAGE_DIRTY 0x00080 /* C: page changed */
19#define _PAGE_ACCESSED 0x00100 /* R: page referenced */
20/*
21 * Software bits
22 */
23#ifdef CONFIG_MEM_SOFT_DIRTY
24#define _PAGE_SOFT_DIRTY 0x00200 /* software: software dirty tracking */
25#else
26#define _PAGE_SOFT_DIRTY 0x00000
27#endif
28#define _PAGE_SPECIAL 0x00400 /* software: special page */
29
30
31#define _PAGE_PTE (1ul << 62) /* distinguishes PTEs from pointers */
32#define _PAGE_PRESENT (1ul << 63) /* pte contains a translation */
33/*
34 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE
35 * Instead of fixing all of them, add an alternate define which
36 * maps CI pte mapping.
37 */
38#define _PAGE_NO_CACHE _PAGE_TOLERANT
39/*
40 * We support 57 bit real address in pte. Clear everything above 57, and
41 * every thing below PAGE_SHIFT;
42 */
43#define PTE_RPN_MASK (((1UL << 57) - 1) & (PAGE_MASK))
44/*
45 * set of bits not changed in pmd_modify. Even though we have hash specific bits
46 * in here, on radix we expect them to be zero.
47 */
48#define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
49 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \
50 _PAGE_SOFT_DIRTY)
51/*
52 * user access blocked by key
53 */
54#define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY)
55#define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ)
56#define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \
57 _PAGE_RW | _PAGE_EXEC)
58/*
59 * No page size encoding in the linux PTE
60 */
61#define _PAGE_PSIZE 0
62/*
63 * _PAGE_CHG_MASK masks of bits that are to be preserved across
64 * pgprot changes
65 */
66#define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
67 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \
68 _PAGE_SOFT_DIRTY)
69/*
70 * Mask of bits returned by pte_pgprot()
71 */
72#define PAGE_PROT_BITS (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT | \
73 H_PAGE_4K_PFN | _PAGE_PRIVILEGED | _PAGE_ACCESSED | \
74 _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_EXEC | \
75 _PAGE_SOFT_DIRTY)
3dfcb315 76/*
2e873519
AK		 77 * We define 2 sets of base prot bits, one for basic pages (ie,
78 * cacheable kernel and user pages) and one for non cacheable
79 * pages. We always set _PAGE_COHERENT when SMP is enabled or
80 * the processor might need it for DMA coherency.
3dfcb315 81 */
2e873519
AK		 82#define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE)
83#define _PAGE_BASE (_PAGE_BASE_NC)
84
85/* Permission masks used to generate the __P and __S table,
86 *
87 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h
88 *
89 * Write permissions imply read permissions for now (we could make write-only
90 * pages on BookE but we don't bother for now). Execute permission control is
91 * possible on platforms that define _PAGE_EXEC
92 *
93 * Note due to the way vm flags are laid out, the bits are XWR
94 */
95#define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED)
96#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW)
97#define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC)
98#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ)
99#define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
100#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ)
101#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
102
103#define __P000 PAGE_NONE
104#define __P001 PAGE_READONLY
105#define __P010 PAGE_COPY
106#define __P011 PAGE_COPY
107#define __P100 PAGE_READONLY_X
108#define __P101 PAGE_READONLY_X
109#define __P110 PAGE_COPY_X
110#define __P111 PAGE_COPY_X
111
112#define __S000 PAGE_NONE
113#define __S001 PAGE_READONLY
114#define __S010 PAGE_SHARED
115#define __S011 PAGE_SHARED
116#define __S100 PAGE_READONLY_X
117#define __S101 PAGE_READONLY_X
118#define __S110 PAGE_SHARED_X
119#define __S111 PAGE_SHARED_X
120
121/* Permission masks used for kernel mappings */
122#define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW)
123#define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
124 _PAGE_TOLERANT)
125#define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
126 _PAGE_NON_IDEMPOTENT)
127#define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX)
128#define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO)
129#define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX)
130
131/*
132 * Protection used for kernel text. We want the debuggers to be able to
133 * set breakpoints anywhere, so don't write protect the kernel text
134 * on platforms where such control is possible.
135 */
136#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \
137 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE)
138#define PAGE_KERNEL_TEXT PAGE_KERNEL_X
139#else
140#define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX
141#endif
142
143/* Make modules code happy. We don't set RO yet */
144#define PAGE_KERNEL_EXEC PAGE_KERNEL_X
145#define PAGE_AGP (PAGE_KERNEL_NC)
3dfcb315 146
dd1842a2
AK		 147#ifndef __ASSEMBLY__
148/*
149 * page table defines
150 */
151extern unsigned long __pte_index_size;
152extern unsigned long __pmd_index_size;
153extern unsigned long __pud_index_size;
154extern unsigned long __pgd_index_size;
155extern unsigned long __pmd_cache_index;
156#define PTE_INDEX_SIZE __pte_index_size
157#define PMD_INDEX_SIZE __pmd_index_size
158#define PUD_INDEX_SIZE __pud_index_size
159#define PGD_INDEX_SIZE __pgd_index_size
160#define PMD_CACHE_INDEX __pmd_cache_index
161/*
162 * Because of use of pte fragments and THP, size of page table
163 * are not always derived out of index size above.
164 */
165extern unsigned long __pte_table_size;
166extern unsigned long __pmd_table_size;
167extern unsigned long __pud_table_size;
168extern unsigned long __pgd_table_size;
169#define PTE_TABLE_SIZE __pte_table_size
170#define PMD_TABLE_SIZE __pmd_table_size
171#define PUD_TABLE_SIZE __pud_table_size
172#define PGD_TABLE_SIZE __pgd_table_size
173/*
174 * Pgtable size used by swapper, init in asm code
175 * We will switch this later to radix PGD
176 */
177#define MAX_PGD_TABLE_SIZE (sizeof(pgd_t) << H_PGD_INDEX_SIZE)
178
179#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
180#define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
181#define PTRS_PER_PUD (1 << PUD_INDEX_SIZE)
182#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
183
184/* PMD_SHIFT determines what a second-level page table entry can map */
185#define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
186#define PMD_SIZE (1UL << PMD_SHIFT)
187#define PMD_MASK (~(PMD_SIZE-1))
188
189/* PUD_SHIFT determines what a third-level page table entry can map */
190#define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
191#define PUD_SIZE (1UL << PUD_SHIFT)
192#define PUD_MASK (~(PUD_SIZE-1))
193
194/* PGDIR_SHIFT determines what a fourth-level page table entry can map */
195#define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE)
196#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
197#define PGDIR_MASK (~(PGDIR_SIZE-1))
198
199/* Bits to mask out from a PMD to get to the PTE page */
200#define PMD_MASKED_BITS 0xc0000000000000ffUL
201/* Bits to mask out from a PUD to get to the PMD page */
202#define PUD_MASKED_BITS 0xc0000000000000ffUL
203/* Bits to mask out from a PGD to get to the PUD page */
204#define PGD_MASKED_BITS 0xc0000000000000ffUL
205#endif /* __ASSEMBLY__ */
206
ab537dca 207#include <asm/book3s/64/hash.h>
b0b5e9b1 208#include <asm/book3s/64/radix.h>
a9252aae
AK		 209
210#ifdef CONFIG_PPC_64K_PAGES
211#include <asm/book3s/64/pgtable-64k.h>
212#else
213#include <asm/book3s/64/pgtable-4k.h>
214#endif
215
3dfcb315
AK		 216#include <asm/barrier.h>
217
3dfcb315
AK		 218/*
219 * The second half of the kernel virtual space is used for IO mappings,
220 * it's itself carved into the PIO region (ISA and PHB IO space) and
221 * the ioremap space
222 *
223 * ISA_IO_BASE = KERN_IO_START, 64K reserved area
224 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces
225 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE
226 */
227#define KERN_IO_START (KERN_VIRT_START + (KERN_VIRT_SIZE >> 1))
228#define FULL_IO_SIZE 0x80000000ul
229#define ISA_IO_BASE (KERN_IO_START)
230#define ISA_IO_END (KERN_IO_START + 0x10000ul)
231#define PHB_IO_BASE (ISA_IO_END)
232#define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE)
233#define IOREMAP_BASE (PHB_IO_END)
234#define IOREMAP_END (KERN_VIRT_START + KERN_VIRT_SIZE)
235
3dfcb315
AK		 236#define vmemmap ((struct page *)VMEMMAP_BASE)
237
b0412ea9 238/* Advertise special mapping type for AGP */
b0412ea9
AK		 239#define HAVE_PAGE_AGP
240
241/* Advertise support for _PAGE_SPECIAL */
242#define __HAVE_ARCH_PTE_SPECIAL
243
3dfcb315
AK		 244#ifndef __ASSEMBLY__
245
246/*
247 * This is the default implementation of various PTE accessors, it's
248 * used in all cases except Book3S with 64K pages where we have a
249 * concept of sub-pages
250 */
251#ifndef __real_pte
252
3dfcb315
AK		 253#define __real_pte(e,p) ((real_pte_t){(e)})
254#define __rpte_to_pte(r) ((r).pte)
945537df 255#define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT)
3dfcb315
AK		 256
257#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
258 do { \
259 index = 0; \
260 shift = mmu_psize_defs[psize].shift; \
261
262#define pte_iterate_hashed_end() } while(0)
263
264/*
265 * We expect this to be called only for user addresses or kernel virtual
266 * addresses other than the linear mapping.
267 */
268#define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K
269
270#endif /* __real_pte */
271
ac94ac79
AK		 272static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr,
273 pte_t *ptep, unsigned long clr,
274 unsigned long set, int huge)
275{
276 if (radix_enabled())
277 return radix__pte_update(mm, addr, ptep, clr, set, huge);
278 return hash__pte_update(mm, addr, ptep, clr, set, huge);
279}
13f829a5
AK		 280/*
281 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update.
282 * We currently remove entries from the hashtable regardless of whether
283 * the entry was young or dirty.
284 *
285 * We should be more intelligent about this but for the moment we override
286 * these functions and force a tlb flush unconditionally
287 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same
288 * function for both hash and radix.
289 */
290static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
291 unsigned long addr, pte_t *ptep)
292{
293 unsigned long old;
294
295 if ((pte_val(*ptep) & (_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
296 return 0;
297 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0);
298 return (old & _PAGE_ACCESSED) != 0;
299}
300
301#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
302#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
303({ \
304 int __r; \
305 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
306 __r; \
307})
308
309#define __HAVE_ARCH_PTEP_SET_WRPROTECT
310static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
311 pte_t *ptep)
312{
313
314 if ((pte_val(*ptep) & _PAGE_WRITE) == 0)
315 return;
316
317 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0);
318}
319
320static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
321 unsigned long addr, pte_t *ptep)
322{
323 if ((pte_val(*ptep) & _PAGE_WRITE) == 0)
324 return;
325
326 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1);
327}
328
329#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
330static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
331 unsigned long addr, pte_t *ptep)
332{
333 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0);
334 return __pte(old);
335}
336
337static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
338 pte_t * ptep)
339{
340 pte_update(mm, addr, ptep, ~0UL, 0, 0);
341}
342static inline int pte_write(pte_t pte) { return !!(pte_val(pte) & _PAGE_WRITE);}
343static inline int pte_dirty(pte_t pte) { return !!(pte_val(pte) & _PAGE_DIRTY); }
344static inline int pte_young(pte_t pte) { return !!(pte_val(pte) & _PAGE_ACCESSED); }
345static inline int pte_special(pte_t pte) { return !!(pte_val(pte) & _PAGE_SPECIAL); }
346static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); }
347
348#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
349static inline bool pte_soft_dirty(pte_t pte)
350{
351 return !!(pte_val(pte) & _PAGE_SOFT_DIRTY);
352}
353static inline pte_t pte_mksoft_dirty(pte_t pte)
354{
355 return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
356}
357
358static inline pte_t pte_clear_soft_dirty(pte_t pte)
359{
360 return __pte(pte_val(pte) & ~_PAGE_SOFT_DIRTY);
361}
362#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
363
364#ifdef CONFIG_NUMA_BALANCING
365/*
366 * These work without NUMA balancing but the kernel does not care. See the
367 * comment in include/asm-generic/pgtable.h . On powerpc, this will only
368 * work for user pages and always return true for kernel pages.
369 */
370static inline int pte_protnone(pte_t pte)
371{
372 return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PRIVILEGED)) ==
373 (_PAGE_PRESENT | _PAGE_PRIVILEGED);
374}
375#endif /* CONFIG_NUMA_BALANCING */
376
377static inline int pte_present(pte_t pte)
378{
379 return !!(pte_val(pte) & _PAGE_PRESENT);
380}
381/*
382 * Conversion functions: convert a page and protection to a page entry,
383 * and a page entry and page directory to the page they refer to.
384 *
385 * Even if PTEs can be unsigned long long, a PFN is always an unsigned
386 * long for now.
387 */
388static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
389{
390 return __pte((((pte_basic_t)(pfn) << PAGE_SHIFT) & PTE_RPN_MASK) |
391 pgprot_val(pgprot));
392}
393
394static inline unsigned long pte_pfn(pte_t pte)
395{
396 return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT;
397}
398
399/* Generic modifiers for PTE bits */
400static inline pte_t pte_wrprotect(pte_t pte)
401{
402 return __pte(pte_val(pte) & ~_PAGE_WRITE);
403}
404
405static inline pte_t pte_mkclean(pte_t pte)
406{
407 return __pte(pte_val(pte) & ~_PAGE_DIRTY);
408}
409
410static inline pte_t pte_mkold(pte_t pte)
411{
412 return __pte(pte_val(pte) & ~_PAGE_ACCESSED);
413}
414
415static inline pte_t pte_mkwrite(pte_t pte)
416{
417 /*
418 * write implies read, hence set both
419 */
420 return __pte(pte_val(pte) | _PAGE_RW);
421}
422
423static inline pte_t pte_mkdirty(pte_t pte)
424{
425 return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
426}
427
428static inline pte_t pte_mkyoung(pte_t pte)
429{
430 return __pte(pte_val(pte) | _PAGE_ACCESSED);
431}
432
433static inline pte_t pte_mkspecial(pte_t pte)
434{
435 return __pte(pte_val(pte) | _PAGE_SPECIAL);
436}
437
438static inline pte_t pte_mkhuge(pte_t pte)
439{
440 return pte;
441}
442
443static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
444{
445 /* FIXME!! check whether this need to be a conditional */
446 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
447}
448
34fbadd8
AK		 449static inline bool pte_user(pte_t pte)
450{
451 return !(pte_val(pte) & _PAGE_PRIVILEGED);
452}
453
454/* Encode and de-code a swap entry */
455#define MAX_SWAPFILES_CHECK() do { \
456 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \
457 /* \
458 * Don't have overlapping bits with _PAGE_HPTEFLAGS \
459 * We filter HPTEFLAGS on set_pte. \
460 */ \
461 BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \
462 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \
463 } while (0)
464/*
465 * on pte we don't need handle RADIX_TREE_EXCEPTIONAL_SHIFT;
466 */
467#define SWP_TYPE_BITS 5
468#define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \
469 & ((1UL << SWP_TYPE_BITS) - 1))
470#define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT)
471#define __swp_entry(type, offset) ((swp_entry_t) { \
472 ((type) << _PAGE_BIT_SWAP_TYPE) \
473 | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)})
474/*
475 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from
476 * swap type and offset we get from swap and convert that to pte to find a
477 * matching pte in linux page table.
478 * Clear bits not found in swap entries here.
479 */
480#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE })
481#define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE)
482
483#ifdef CONFIG_MEM_SOFT_DIRTY
484#define _PAGE_SWP_SOFT_DIRTY (1UL << (SWP_TYPE_BITS + _PAGE_BIT_SWAP_TYPE))
485#else
486#define _PAGE_SWP_SOFT_DIRTY 0UL
487#endif /* CONFIG_MEM_SOFT_DIRTY */
488
489#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
490static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
491{
492 return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
493}
494static inline bool pte_swp_soft_dirty(pte_t pte)
495{
496 return !!(pte_val(pte) & _PAGE_SWP_SOFT_DIRTY);
497}
498static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
499{
500 return __pte(pte_val(pte) & ~_PAGE_SWP_SOFT_DIRTY);
501}
502#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
503
504static inline bool check_pte_access(unsigned long access, unsigned long ptev)
505{
506 /*
507 * This check for _PAGE_RWX and _PAGE_PRESENT bits
508 */
509 if (access & ~ptev)
510 return false;
511 /*
512 * This check for access to privilege space
513 */
514 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED))
515 return false;
516
517 return true;
518}
ac94ac79
AK		 519/*
520 * Generic functions with hash/radix callbacks
521 */
522
523static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
524{
525 if (radix_enabled())
526 return radix__ptep_set_access_flags(ptep, entry);
527 return hash__ptep_set_access_flags(ptep, entry);
528}
529
530#define __HAVE_ARCH_PTE_SAME
531static inline int pte_same(pte_t pte_a, pte_t pte_b)
532{
533 if (radix_enabled())
534 return radix__pte_same(pte_a, pte_b);
535 return hash__pte_same(pte_a, pte_b);
536}
537
538static inline int pte_none(pte_t pte)
539{
540 if (radix_enabled())
541 return radix__pte_none(pte);
542 return hash__pte_none(pte);
543}
544
545static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
546 pte_t *ptep, pte_t pte, int percpu)
547{
548 if (radix_enabled())
549 return radix__set_pte_at(mm, addr, ptep, pte, percpu);
550 return hash__set_pte_at(mm, addr, ptep, pte, percpu);
551}
34fbadd8 552
13f829a5
AK		 553#define _PAGE_CACHE_CTL (_PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT)
554
555#define pgprot_noncached pgprot_noncached
556static inline pgprot_t pgprot_noncached(pgprot_t prot)
557{
558 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
559 _PAGE_NON_IDEMPOTENT);
560}
561
562#define pgprot_noncached_wc pgprot_noncached_wc
563static inline pgprot_t pgprot_noncached_wc(pgprot_t prot)
564{
565 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
566 _PAGE_TOLERANT);
567}
568
569#define pgprot_cached pgprot_cached
570static inline pgprot_t pgprot_cached(pgprot_t prot)
571{
572 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL));
573}
574
575#define pgprot_writecombine pgprot_writecombine
576static inline pgprot_t pgprot_writecombine(pgprot_t prot)
577{
578 return pgprot_noncached_wc(prot);
579}
580/*
581 * check a pte mapping have cache inhibited property
582 */
583static inline bool pte_ci(pte_t pte)
584{
585 unsigned long pte_v = pte_val(pte);
586
587 if (((pte_v & _PAGE_CACHE_CTL) == _PAGE_TOLERANT) ||
588 ((pte_v & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT))
589 return true;
590 return false;
591}
592
f281b5d5
AK		 593static inline void pmd_set(pmd_t *pmdp, unsigned long val)
594{
595 *pmdp = __pmd(val);
596}
597
598static inline void pmd_clear(pmd_t *pmdp)
599{
600 *pmdp = __pmd(0);
601}
602
3dfcb315 603#define pmd_none(pmd) (!pmd_val(pmd))
3dfcb315 604#define pmd_present(pmd) (!pmd_none(pmd))
3dfcb315 605
ac94ac79
AK		 606static inline int pmd_bad(pmd_t pmd)
607{
608 if (radix_enabled())
609 return radix__pmd_bad(pmd);
610 return hash__pmd_bad(pmd);
611}
612
f281b5d5
AK		 613static inline void pud_set(pud_t *pudp, unsigned long val)
614{
615 *pudp = __pud(val);
616}
617
618static inline void pud_clear(pud_t *pudp)
619{
620 *pudp = __pud(0);
621}
622
3dfcb315 623#define pud_none(pud) (!pud_val(pud))
3dfcb315 624#define pud_present(pud) (pud_val(pud) != 0)
3dfcb315
AK		 625
626extern struct page *pud_page(pud_t pud);
371352ca 627extern struct page *pmd_page(pmd_t pmd);
3dfcb315
AK		 628static inline pte_t pud_pte(pud_t pud)
629{
630 return __pte(pud_val(pud));
631}
632
633static inline pud_t pte_pud(pte_t pte)
634{
635 return __pud(pte_val(pte));
636}
637#define pud_write(pud) pte_write(pud_pte(pud))
ac94ac79
AK		 638
639static inline int pud_bad(pud_t pud)
640{
641 if (radix_enabled())
642 return radix__pud_bad(pud);
643 return hash__pud_bad(pud);
644}
645
646
3dfcb315 647#define pgd_write(pgd) pte_write(pgd_pte(pgd))
f281b5d5
AK		 648static inline void pgd_set(pgd_t *pgdp, unsigned long val)
649{
650 *pgdp = __pgd(val);
651}
3dfcb315 652
368ced78
AK		 653static inline void pgd_clear(pgd_t *pgdp)
654{
655 *pgdp = __pgd(0);
656}
657
658#define pgd_none(pgd) (!pgd_val(pgd))
659#define pgd_present(pgd) (!pgd_none(pgd))
660
661static inline pte_t pgd_pte(pgd_t pgd)
662{
663 return __pte(pgd_val(pgd));
664}
665
666static inline pgd_t pte_pgd(pte_t pte)
667{
668 return __pgd(pte_val(pte));
669}
670
ac94ac79
AK		 671static inline int pgd_bad(pgd_t pgd)
672{
673 if (radix_enabled())
674 return radix__pgd_bad(pgd);
675 return hash__pgd_bad(pgd);
676}
677
368ced78
AK		 678extern struct page *pgd_page(pgd_t pgd);
679
aba480e1
AK		 680/* Pointers in the page table tree are physical addresses */
681#define __pgtable_ptr_val(ptr) __pa(ptr)
682
683#define pmd_page_vaddr(pmd) __va(pmd_val(pmd) & ~PMD_MASKED_BITS)
684#define pud_page_vaddr(pud) __va(pud_val(pud) & ~PUD_MASKED_BITS)
685#define pgd_page_vaddr(pgd) __va(pgd_val(pgd) & ~PGD_MASKED_BITS)
686
687#define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1))
688#define pud_index(address) (((address) >> (PUD_SHIFT)) & (PTRS_PER_PUD - 1))
689#define pmd_index(address) (((address) >> (PMD_SHIFT)) & (PTRS_PER_PMD - 1))
690#define pte_index(address) (((address) >> (PAGE_SHIFT)) & (PTRS_PER_PTE - 1))
691
3dfcb315
AK		 692/*
693 * Find an entry in a page-table-directory. We combine the address region
694 * (the high order N bits) and the pgd portion of the address.
695 */
3dfcb315
AK		 696
697#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
698
368ced78
AK		 699#define pud_offset(pgdp, addr) \
700 (((pud_t *) pgd_page_vaddr(*(pgdp))) + pud_index(addr))
3dfcb315 701#define pmd_offset(pudp,addr) \
371352ca 702 (((pmd_t *) pud_page_vaddr(*(pudp))) + pmd_index(addr))
3dfcb315 703#define pte_offset_kernel(dir,addr) \
371352ca 704 (((pte_t *) pmd_page_vaddr(*(dir))) + pte_index(addr))
3dfcb315
AK		 705
706#define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
707#define pte_unmap(pte) do { } while(0)
708
709/* to find an entry in a kernel page-table-directory */
710/* This now only contains the vmalloc pages */
711#define pgd_offset_k(address) pgd_offset(&init_mm, address)
3dfcb315
AK		 712
713#define pte_ERROR(e) \
714 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
715#define pmd_ERROR(e) \
716 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
368ced78
AK		 717#define pud_ERROR(e) \
718 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
3dfcb315
AK		 719#define pgd_ERROR(e) \
720 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
721
3dfcb315
AK		 722void pgtable_cache_add(unsigned shift, void (*ctor)(void *));
723void pgtable_cache_init(void);
3dfcb315 724
31a14fae
AK		 725static inline int map_kernel_page(unsigned long ea, unsigned long pa,
726 unsigned long flags)
727{
728 return hash__map_kernel_page(ea, pa, flags);
729}
730
731static inline int __meminit vmemmap_create_mapping(unsigned long start,
732 unsigned long page_size,
733 unsigned long phys)
734{
735 return hash__vmemmap_create_mapping(start, page_size, phys);
736}
737
738#ifdef CONFIG_MEMORY_HOTPLUG
739static inline void vmemmap_remove_mapping(unsigned long start,
740 unsigned long page_size)
741{
742 return hash__vmemmap_remove_mapping(start, page_size);
743}
744#endif
3dfcb315
AK		 745struct page *realmode_pfn_to_page(unsigned long pfn);
746
3dfcb315 747#ifdef CONFIG_TRANSPARENT_HUGEPAGE
3dfcb315
AK		 748extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot);
749extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot);
750extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot);
751extern void set_pmd_at(struct mm_struct *mm, unsigned long addr,
752 pmd_t *pmdp, pmd_t pmd);
753extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
754 pmd_t *pmd);
3dfcb315 755extern int has_transparent_hugepage(void);
3dfcb315
AK		 756#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
757
3dfcb315
AK		 758
759static inline pte_t pmd_pte(pmd_t pmd)
760{
761 return __pte(pmd_val(pmd));
762}
763
764static inline pmd_t pte_pmd(pte_t pte)
765{
766 return __pmd(pte_val(pte));
767}
768
769static inline pte_t *pmdp_ptep(pmd_t *pmd)
770{
771 return (pte_t *)pmd;
772}
773
774#define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd))
775#define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
776#define pmd_young(pmd) pte_young(pmd_pte(pmd))
777#define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
778#define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
779#define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
d5d6a443 780#define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
3dfcb315
AK		 781#define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
782#define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
7207f436
LD		 783
784#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
785#define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd))
786#define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)))
787#define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)))
788#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
789
1ca72129
AK		 790#ifdef CONFIG_NUMA_BALANCING
791static inline int pmd_protnone(pmd_t pmd)
792{
793 return pte_protnone(pmd_pte(pmd));
794}
795#endif /* CONFIG_NUMA_BALANCING */
3dfcb315
AK		 796
797#define __HAVE_ARCH_PMD_WRITE
798#define pmd_write(pmd) pte_write(pmd_pte(pmd))
799
800static inline pmd_t pmd_mkhuge(pmd_t pmd)
801{
945537df 802 return __pmd(pmd_val(pmd) | (_PAGE_PTE | H_PAGE_THP_HUGE));
3dfcb315
AK		 803}
804
3dfcb315
AK		 805#define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
806extern int pmdp_set_access_flags(struct vm_area_struct *vma,
807 unsigned long address, pmd_t *pmdp,
808 pmd_t entry, int dirty);
809
3dfcb315
AK		 810#define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
811extern int pmdp_test_and_clear_young(struct vm_area_struct *vma,
812 unsigned long address, pmd_t *pmdp);
3dfcb315
AK		 813
814#define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
815extern pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
816 unsigned long addr, pmd_t *pmdp);
817
3dfcb315
AK		 818extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
819 unsigned long address, pmd_t *pmdp);
820#define pmdp_collapse_flush pmdp_collapse_flush
821
822#define __HAVE_ARCH_PGTABLE_DEPOSIT
823extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
824 pgtable_t pgtable);
825#define __HAVE_ARCH_PGTABLE_WITHDRAW
826extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
827
828#define __HAVE_ARCH_PMDP_INVALIDATE
829extern void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
830 pmd_t *pmdp);
831
c777e2a8
AK		 832#define __HAVE_ARCH_PMDP_HUGE_SPLIT_PREPARE
833extern void pmdp_huge_split_prepare(struct vm_area_struct *vma,
834 unsigned long address, pmd_t *pmdp);
835
3dfcb315
AK		 836#define pmd_move_must_withdraw pmd_move_must_withdraw
837struct spinlock;
838static inline int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl,
839 struct spinlock *old_pmd_ptl)
840{
841 /*
842 * Archs like ppc64 use pgtable to store per pmd
843 * specific information. So when we switch the pmd,
844 * we should also withdraw and deposit the pgtable
845 */
846 return true;
847}
848#endif /* __ASSEMBLY__ */
849#endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */
Linux kernel - Deliverables
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