projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 26ef5c09 DG |
1 | /* |
| 2 | * This program is free software; you can redistribute it and/or | |
| 3 | * modify it under the terms of the GNU General Public License | |
| 4 | * as published by the Free Software Foundation; either version | |
| 5 | * 2 of the License, or (at your option) any later version. | |
| 6 | */ | |
| 7 | #ifndef _ASM_POWERPC_CACHEFLUSH_H | |
| 8 | #define _ASM_POWERPC_CACHEFLUSH_H | |
| 9 | ||
| 10 | #ifdef __KERNEL__ | |
| 1da177e4 LT |
11 | |
| 12 | #include <linux/mm.h> | |
| 13 | #include <asm/cputable.h> | |
| 14 | ||
| 15 | /* | |
| 26ef5c09 DG |
16 | * No cache flushing is required when address mappings are changed, |
| 17 | * because the caches on PowerPCs are physically addressed. | |
| 1da177e4 LT |
18 | */ |
| 19 | #define flush_cache_all() do { } while (0) | |
| 20 | #define flush_cache_mm(mm) do { } while (0) | |
| ec8c0446 | 21 | #define flush_cache_dup_mm(mm) do { } while (0) |
| 1da177e4 LT |
22 | #define flush_cache_range(vma, start, end) do { } while (0) |
| 23 | #define flush_cache_page(vma, vmaddr, pfn) do { } while (0) | |
| 24 | #define flush_icache_page(vma, page) do { } while (0) | |
| 25 | #define flush_cache_vmap(start, end) do { } while (0) | |
| 26 | #define flush_cache_vunmap(start, end) do { } while (0) | |
| 27 | ||
| 2d4dc890 | 28 | #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 |
| 1da177e4 LT |
29 | extern void flush_dcache_page(struct page *page); |
| 30 | #define flush_dcache_mmap_lock(mapping) do { } while (0) | |
| 31 | #define flush_dcache_mmap_unlock(mapping) do { } while (0) | |
| 32 | ||
| d0832a75 ZC |
33 | extern void __flush_disable_L1(void); |
| 34 | ||
| 1da177e4 | 35 | extern void __flush_icache_range(unsigned long, unsigned long); |
| 26ef5c09 DG |
36 | static inline void flush_icache_range(unsigned long start, unsigned long stop) |
| 37 | { | |
| 38 | if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE)) | |
| 39 | __flush_icache_range(start, stop); | |
| 40 | } | |
| 41 | ||
| 1da177e4 LT |
42 | extern void flush_icache_user_range(struct vm_area_struct *vma, |
| 43 | struct page *page, unsigned long addr, | |
| 44 | int len); | |
| 26ef5c09 DG |
45 | extern void __flush_dcache_icache(void *page_va); |
| 46 | extern void flush_dcache_icache_page(struct page *page); | |
| 47 | #if defined(CONFIG_PPC32) && !defined(CONFIG_BOOKE) | |
| 48 | extern void __flush_dcache_icache_phys(unsigned long physaddr); | |
| 49 | #endif /* CONFIG_PPC32 && !CONFIG_BOOKE */ | |
| 1da177e4 LT |
50 | |
| 51 | extern void flush_dcache_range(unsigned long start, unsigned long stop); | |
| 26ef5c09 DG |
52 | #ifdef CONFIG_PPC32 |
| 53 | extern void clean_dcache_range(unsigned long start, unsigned long stop); | |
| 54 | extern void invalidate_dcache_range(unsigned long start, unsigned long stop); | |
| 55 | #endif /* CONFIG_PPC32 */ | |
| 56 | #ifdef CONFIG_PPC64 | |
| 1da177e4 | 57 | extern void flush_inval_dcache_range(unsigned long start, unsigned long stop); |
| 26ef5c09 DG |
58 | extern void flush_dcache_phys_range(unsigned long start, unsigned long stop); |
| 59 | #endif | |
| 1da177e4 LT |
60 | |
| 61 | #define copy_to_user_page(vma, page, vaddr, dst, src, len) \ | |
| 26ef5c09 DG |
62 | do { \ |
| 63 | memcpy(dst, src, len); \ | |
| 64 | flush_icache_user_range(vma, page, vaddr, len); \ | |
| 65 | } while (0) | |
| 1da177e4 LT |
66 | #define copy_from_user_page(vma, page, vaddr, dst, src, len) \ |
| 67 | memcpy(dst, src, len) | |
| 68 | ||
| 1da177e4 | 69 | |
| 88df6e90 BH |
70 | |
| 71 | #ifdef CONFIG_DEBUG_PAGEALLOC | |
| 72 | /* internal debugging function */ | |
| 73 | void kernel_map_pages(struct page *page, int numpages, int enable); | |
| 74 | #endif | |
| 75 | ||
| 26ef5c09 | 76 | #endif /* __KERNEL__ */ |
| 1da177e4 | 77 | |
| 26ef5c09 | 78 | #endif /* _ASM_POWERPC_CACHEFLUSH_H */ |