projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 15f8c604 SW |
1 | #ifndef __CPM_H |
| 2 | #define __CPM_H | |
| 3 | ||
| 4 | #include <linux/compiler.h> | |
| 5 | #include <linux/types.h> | |
| e193325e | 6 | #include <linux/of.h> |
| 15f8c604 | 7 | |
| e24e788a LP |
8 | /* Opcodes common to CPM1 and CPM2 |
| 9 | */ | |
| 10 | #define CPM_CR_INIT_TRX ((ushort)0x0000) | |
| 11 | #define CPM_CR_INIT_RX ((ushort)0x0001) | |
| 12 | #define CPM_CR_INIT_TX ((ushort)0x0002) | |
| 13 | #define CPM_CR_HUNT_MODE ((ushort)0x0003) | |
| 14 | #define CPM_CR_STOP_TX ((ushort)0x0004) | |
| 15 | #define CPM_CR_GRA_STOP_TX ((ushort)0x0005) | |
| 16 | #define CPM_CR_RESTART_TX ((ushort)0x0006) | |
| 17 | #define CPM_CR_CLOSE_RX_BD ((ushort)0x0007) | |
| 18 | #define CPM_CR_SET_GADDR ((ushort)0x0008) | |
| 19 | #define CPM_CR_SET_TIMER ((ushort)0x0008) | |
| 20 | #define CPM_CR_STOP_IDMA ((ushort)0x000b) | |
| 21 | ||
| 44f25fb4 JF |
22 | /* Buffer descriptors used by many of the CPM protocols. */ |
| 23 | typedef struct cpm_buf_desc { | |
| 24 | ushort cbd_sc; /* Status and Control */ | |
| 25 | ushort cbd_datlen; /* Data length in buffer */ | |
| 26 | uint cbd_bufaddr; /* Buffer address in host memory */ | |
| 27 | } cbd_t; | |
| 28 | ||
| 29 | /* Buffer descriptor control/status used by serial | |
| 30 | */ | |
| 31 | ||
| 32 | #define BD_SC_EMPTY (0x8000) /* Receive is empty */ | |
| 33 | #define BD_SC_READY (0x8000) /* Transmit is ready */ | |
| 34 | #define BD_SC_WRAP (0x2000) /* Last buffer descriptor */ | |
| 35 | #define BD_SC_INTRPT (0x1000) /* Interrupt on change */ | |
| 36 | #define BD_SC_LAST (0x0800) /* Last buffer in frame */ | |
| 37 | #define BD_SC_TC (0x0400) /* Transmit CRC */ | |
| 38 | #define BD_SC_CM (0x0200) /* Continous mode */ | |
| 39 | #define BD_SC_ID (0x0100) /* Rec'd too many idles */ | |
| 40 | #define BD_SC_P (0x0100) /* xmt preamble */ | |
| 41 | #define BD_SC_BR (0x0020) /* Break received */ | |
| 42 | #define BD_SC_FR (0x0010) /* Framing error */ | |
| 43 | #define BD_SC_PR (0x0008) /* Parity error */ | |
| 44 | #define BD_SC_NAK (0x0004) /* NAK - did not respond */ | |
| 45 | #define BD_SC_OV (0x0002) /* Overrun */ | |
| 46 | #define BD_SC_UN (0x0002) /* Underrun */ | |
| 47 | #define BD_SC_CD (0x0001) /* */ | |
| 48 | #define BD_SC_CL (0x0001) /* Collision */ | |
| 49 | ||
| 50 | /* Buffer descriptor control/status used by Ethernet receive. | |
| 51 | * Common to SCC and FCC. | |
| 52 | */ | |
| 53 | #define BD_ENET_RX_EMPTY (0x8000) | |
| 54 | #define BD_ENET_RX_WRAP (0x2000) | |
| 55 | #define BD_ENET_RX_INTR (0x1000) | |
| 56 | #define BD_ENET_RX_LAST (0x0800) | |
| 57 | #define BD_ENET_RX_FIRST (0x0400) | |
| 58 | #define BD_ENET_RX_MISS (0x0100) | |
| 59 | #define BD_ENET_RX_BC (0x0080) /* FCC Only */ | |
| 60 | #define BD_ENET_RX_MC (0x0040) /* FCC Only */ | |
| 61 | #define BD_ENET_RX_LG (0x0020) | |
| 62 | #define BD_ENET_RX_NO (0x0010) | |
| 63 | #define BD_ENET_RX_SH (0x0008) | |
| 64 | #define BD_ENET_RX_CR (0x0004) | |
| 65 | #define BD_ENET_RX_OV (0x0002) | |
| 66 | #define BD_ENET_RX_CL (0x0001) | |
| 67 | #define BD_ENET_RX_STATS (0x01ff) /* All status bits */ | |
| 68 | ||
| 69 | /* Buffer descriptor control/status used by Ethernet transmit. | |
| 70 | * Common to SCC and FCC. | |
| 71 | */ | |
| 72 | #define BD_ENET_TX_READY (0x8000) | |
| 73 | #define BD_ENET_TX_PAD (0x4000) | |
| 74 | #define BD_ENET_TX_WRAP (0x2000) | |
| 75 | #define BD_ENET_TX_INTR (0x1000) | |
| 76 | #define BD_ENET_TX_LAST (0x0800) | |
| 77 | #define BD_ENET_TX_TC (0x0400) | |
| 78 | #define BD_ENET_TX_DEF (0x0200) | |
| 79 | #define BD_ENET_TX_HB (0x0100) | |
| 80 | #define BD_ENET_TX_LC (0x0080) | |
| 81 | #define BD_ENET_TX_RL (0x0040) | |
| 82 | #define BD_ENET_TX_RCMASK (0x003c) | |
| 83 | #define BD_ENET_TX_UN (0x0002) | |
| 84 | #define BD_ENET_TX_CSL (0x0001) | |
| 85 | #define BD_ENET_TX_STATS (0x03ff) /* All status bits */ | |
| 86 | ||
| 87 | /* Buffer descriptor control/status used by Transparent mode SCC. | |
| 88 | */ | |
| 89 | #define BD_SCC_TX_LAST (0x0800) | |
| 90 | ||
| 91 | /* Buffer descriptor control/status used by I2C. | |
| 92 | */ | |
| 93 | #define BD_I2C_START (0x0400) | |
| 94 | ||
| 15f8c604 SW |
95 | int cpm_muram_init(void); |
| 96 | unsigned long cpm_muram_alloc(unsigned long size, unsigned long align); | |
| 97 | int cpm_muram_free(unsigned long offset); | |
| 98 | unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size); | |
| 99 | void __iomem *cpm_muram_addr(unsigned long offset); | |
| 5093bb96 | 100 | unsigned long cpm_muram_offset(void __iomem *addr); |
| 15f8c604 | 101 | dma_addr_t cpm_muram_dma(void __iomem *addr); |
| 362f9b6f | 102 | int cpm_command(u32 command, u8 opcode); |
| 15f8c604 | 103 | |
| e193325e LP |
104 | int cpm2_gpiochip_add32(struct device_node *np); |
| 105 | ||
| 15f8c604 | 106 | #endif |